From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751706AbeD0EuC (ORCPT ); Fri, 27 Apr 2018 00:50:02 -0400 Received: from mail-oi0-f65.google.com ([209.85.218.65]:38731 "EHLO mail-oi0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750982AbeD0EuA (ORCPT ); Fri, 27 Apr 2018 00:50:00 -0400 X-Google-Smtp-Source: AB8JxZrow633CUs4FZZ4GtEBiH8hNgs6Q0+SSyfxEQUX9A9WTDwKsu3wsgW//lrQzHc7Vaf3Nw8E/OiWXqBDgJgL5QU= MIME-Version: 1.0 In-Reply-To: <7c8ff675-2b27-8e7b-f046-513b73f1ae5f@infradead.org> References: <20180425090047.6485-1-ganapatrao.kulkarni@cavium.com> <20180425090047.6485-2-ganapatrao.kulkarni@cavium.com> <7c8ff675-2b27-8e7b-f046-513b73f1ae5f@infradead.org> From: Ganapatrao Kulkarni Date: Fri, 27 Apr 2018 10:19:59 +0530 Message-ID: Subject: Re: [PATCH v4 1/2] perf: uncore: Adding documentation for ThunderX2 pmu uncore driver To: Randy Dunlap Cc: Ganapatrao Kulkarni , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will Deacon , mark.rutland@arm.com, jnair@caviumnetworks.com, Robert Richter , Vadim.Lomovtsev@cavium.com, Jan.Glauber@cavium.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 27, 2018 at 2:25 AM, Randy Dunlap wrote: > Hi, > > Just a few typo corrections... > > On 04/25/2018 02:00 AM, Ganapatrao Kulkarni wrote: >> Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC. >> The SoC has PMU support in its L3 cache controller (L3C) and in the >> DDR4 Memory Controller (DMC). >> >> Signed-off-by: Ganapatrao Kulkarni >> --- >> Documentation/perf/thunderx2-pmu.txt | 66 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 66 insertions(+) >> create mode 100644 Documentation/perf/thunderx2-pmu.txt >> >> diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt >> new file mode 100644 >> index 0000000..9e9f535 >> --- /dev/null >> +++ b/Documentation/perf/thunderx2-pmu.txt >> @@ -0,0 +1,66 @@ >> + >> +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) >> +========================================================================== >> + >> +ThunderX2 SoC PMU consists of independent system wide per Socket PMUs such >> +as Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). >> + >> +It has 8 independent DMC PMUs to capture performance events corresponding >> +to 8 channels of DDR4 Memory Controller. There are 16 independent L3C PMUs >> +to capture events corresponding to 16 tiles of L3 cache. Each PMU supports >> +up to 4 counters. >> + >> +Counters are independent programmable and can be started and stopped > > independently thanks, will update. > >> +individually. Each counter can be set to sample specific perf events. >> +Counters are 32 bit and does not support overflow interrupt, they are > > do not interrupt; they are > > >> +sampled at every 2 seconds. The Counters register access are multiplexed >> +across channels of DMC and L3C. The muxing(select channel) is done through >> +write to a Secure register using smcc calls. >> + >> +PMU UNCORE (perf) driver: >> + >> +The thunderx2-pmu driver registers several perf PMUs for DMC and L3C devices. >> +Each of the PMU provides description of its available events > > of the PMUs > >> +and configuration options in sysfs. >> + see /sys/devices/uncore_ >> + >> +S is socket id and X represents channel number. >> +Each PMU can be used to sample up to 4 events simultaneously. >> + >> +The "format" directory describes format of the config (event ID). >> +The "events" directory provides configuration templates for all >> +supported event types that can be used with perf tool. >> + >> +For example, "uncore_dmc_0_0/cnt_cycles/" is an >> +equivalent of "uncore_dmc_0_0/config=0x1/". >> + >> +Each perf driver also provides a "cpumask" sysfs attribute, which contains a >> +single CPU ID of the processor which is likely to be used to handle all the >> +PMU events. It will be the first online CPU from the NUMA node of PMU device. >> + >> +Example for perf tool use: >> + >> +perf stat -a -e \ >> +uncore_dmc_0_0/cnt_cycles/,\ >> +uncore_dmc_0_1/cnt_cycles/,\ >> +uncore_dmc_0_2/cnt_cycles/,\ >> +uncore_dmc_0_3/cnt_cycles/,\ >> +uncore_dmc_0_4/cnt_cycles/,\ >> +uncore_dmc_0_5/cnt_cycles/,\ >> +uncore_dmc_0_6/cnt_cycles/,\ >> +uncore_dmc_0_7/cnt_cycles/ sleep 1 >> + >> +perf stat -a -e \ >> +uncore_dmc_0_0/cancelled_read_txns/,\ >> +uncore_dmc_0_0/cnt_cycles/,\ >> +uncore_dmc_0_0/consumed_read_txns/,\ >> +uncore_dmc_0_0/data_transfers/ sleep 1 >> + >> +perf stat -a -e \ >> +uncore_l3c_0_0/l3_retry/,\ >> +uncore_l3c_0_0/read_hit/,\ >> +uncore_l3c_0_0/read_request/,\ >> +uncore_l3c_0_0/inv_request/ sleep 1 >> + >> +The driver does not support sampling, therefore "perf record" will >> +not work. Per-task (without "-a") perf sessions are not supported. >> > > > -- > ~Randy thanks Ganapat From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-5.6 required=5.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham autolearn_force=no version=3.4.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id 3936F7DD32 for ; Fri, 27 Apr 2018 04:50:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751348AbeD0EuB (ORCPT ); Fri, 27 Apr 2018 00:50:01 -0400 Received: from mail-oi0-f65.google.com ([209.85.218.65]:38731 "EHLO mail-oi0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750982AbeD0EuA (ORCPT ); Fri, 27 Apr 2018 00:50:00 -0400 Received: by mail-oi0-f65.google.com with SMTP id k17-v6so522359oih.5; Thu, 26 Apr 2018 21:50:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=C/YyO0R/ioT71070NtRH9V1ic7TZ7hKiabRfsKTocWM=; b=h6qlXJ6kjg950X8KX5IW2stcedLUdFxwXJhz5BWWuKPxNMTaBeco4BC0lHtrgJcAnv 4ch4E7UPOlo95hdq3ZHO9rTS7RSfm8wSvvBWEfbzS9GRZgsIaS52ys4SWTOXkpw7PJad Rz2w0qdntZq66yKZQrxMsrX90RDd1ILgWofiA/iGj7jEeku+Ze6bqMfNDiDpYULTdxW7 y+4TTXL9KV89YM64JV7QdjxRPwaC2lBT359j2o45Z8If9xLSI3g6QhB6ZPmukl4V1Qne zDk2czQmqL4qtixwuBjp4/AJK4oJ0aNGvw7EdsY/eQ26aa2ardgUNa1o19W0bqPozFve Vuzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=C/YyO0R/ioT71070NtRH9V1ic7TZ7hKiabRfsKTocWM=; b=QdDt58Aecr5XoimmVeBZt7dOHF9JKIF8aV8XmwELJ7PQ9qvE7KmXTXyK95vzNlbuX4 9d/dXCMPrERrbMF2v/GyBBh9jgPr4v27KqumNwBXPWdvf/vA8MPVFbAiFNHtDVCKt+es 3F4MML4A2zSYlTjgZ5mFAdqH/is3D2yD+mzHXVzsuzEnhhjRga2o/SOcLsUN0IhYHoMq 8VTnhvFoJ3NM12P1Z3KM0eRi4wNP532Zr71e/+IdjfVoOa6DqWdi5JdgokSSJY754ovC fz9HjEVCOqB+C/yLzZTUns3Mi/op1OXzepTqFN4g+L90J+zoScQjziNA/3rMmR5BPQuO BjJg== X-Gm-Message-State: ALQs6tCNwtaAOqtHq1JRlDB2PZxRtnHm+2KZ2/JTjqbg2pSc+pWNRWcg ne/9JO6Q2y4Zd+0zpSxkP2G82QDL++cgPXGVshE= X-Google-Smtp-Source: AB8JxZrow633CUs4FZZ4GtEBiH8hNgs6Q0+SSyfxEQUX9A9WTDwKsu3wsgW//lrQzHc7Vaf3Nw8E/OiWXqBDgJgL5QU= X-Received: by 2002:aca:4e15:: with SMTP id c21-v6mr394772oib.254.1524804599971; Thu, 26 Apr 2018 21:49:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.201.88.68 with HTTP; Thu, 26 Apr 2018 21:49:59 -0700 (PDT) In-Reply-To: <7c8ff675-2b27-8e7b-f046-513b73f1ae5f@infradead.org> References: <20180425090047.6485-1-ganapatrao.kulkarni@cavium.com> <20180425090047.6485-2-ganapatrao.kulkarni@cavium.com> <7c8ff675-2b27-8e7b-f046-513b73f1ae5f@infradead.org> From: Ganapatrao Kulkarni Date: Fri, 27 Apr 2018 10:19:59 +0530 Message-ID: Subject: Re: [PATCH v4 1/2] perf: uncore: Adding documentation for ThunderX2 pmu uncore driver To: Randy Dunlap Cc: Ganapatrao Kulkarni , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will Deacon , mark.rutland@arm.com, jnair@caviumnetworks.com, Robert Richter , Vadim.Lomovtsev@cavium.com, Jan.Glauber@cavium.com Content-Type: text/plain; charset="UTF-8" Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Fri, Apr 27, 2018 at 2:25 AM, Randy Dunlap wrote: > Hi, > > Just a few typo corrections... > > On 04/25/2018 02:00 AM, Ganapatrao Kulkarni wrote: >> Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC. >> The SoC has PMU support in its L3 cache controller (L3C) and in the >> DDR4 Memory Controller (DMC). >> >> Signed-off-by: Ganapatrao Kulkarni >> --- >> Documentation/perf/thunderx2-pmu.txt | 66 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 66 insertions(+) >> create mode 100644 Documentation/perf/thunderx2-pmu.txt >> >> diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt >> new file mode 100644 >> index 0000000..9e9f535 >> --- /dev/null >> +++ b/Documentation/perf/thunderx2-pmu.txt >> @@ -0,0 +1,66 @@ >> + >> +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) >> +========================================================================== >> + >> +ThunderX2 SoC PMU consists of independent system wide per Socket PMUs such >> +as Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). >> + >> +It has 8 independent DMC PMUs to capture performance events corresponding >> +to 8 channels of DDR4 Memory Controller. There are 16 independent L3C PMUs >> +to capture events corresponding to 16 tiles of L3 cache. Each PMU supports >> +up to 4 counters. >> + >> +Counters are independent programmable and can be started and stopped > > independently thanks, will update. > >> +individually. Each counter can be set to sample specific perf events. >> +Counters are 32 bit and does not support overflow interrupt, they are > > do not interrupt; they are > > >> +sampled at every 2 seconds. The Counters register access are multiplexed >> +across channels of DMC and L3C. The muxing(select channel) is done through >> +write to a Secure register using smcc calls. >> + >> +PMU UNCORE (perf) driver: >> + >> +The thunderx2-pmu driver registers several perf PMUs for DMC and L3C devices. >> +Each of the PMU provides description of its available events > > of the PMUs > >> +and configuration options in sysfs. >> + see /sys/devices/uncore_ >> + >> +S is socket id and X represents channel number. >> +Each PMU can be used to sample up to 4 events simultaneously. >> + >> +The "format" directory describes format of the config (event ID). >> +The "events" directory provides configuration templates for all >> +supported event types that can be used with perf tool. >> + >> +For example, "uncore_dmc_0_0/cnt_cycles/" is an >> +equivalent of "uncore_dmc_0_0/config=0x1/". >> + >> +Each perf driver also provides a "cpumask" sysfs attribute, which contains a >> +single CPU ID of the processor which is likely to be used to handle all the >> +PMU events. It will be the first online CPU from the NUMA node of PMU device. >> + >> +Example for perf tool use: >> + >> +perf stat -a -e \ >> +uncore_dmc_0_0/cnt_cycles/,\ >> +uncore_dmc_0_1/cnt_cycles/,\ >> +uncore_dmc_0_2/cnt_cycles/,\ >> +uncore_dmc_0_3/cnt_cycles/,\ >> +uncore_dmc_0_4/cnt_cycles/,\ >> +uncore_dmc_0_5/cnt_cycles/,\ >> +uncore_dmc_0_6/cnt_cycles/,\ >> +uncore_dmc_0_7/cnt_cycles/ sleep 1 >> + >> +perf stat -a -e \ >> +uncore_dmc_0_0/cancelled_read_txns/,\ >> +uncore_dmc_0_0/cnt_cycles/,\ >> +uncore_dmc_0_0/consumed_read_txns/,\ >> +uncore_dmc_0_0/data_transfers/ sleep 1 >> + >> +perf stat -a -e \ >> +uncore_l3c_0_0/l3_retry/,\ >> +uncore_l3c_0_0/read_hit/,\ >> +uncore_l3c_0_0/read_request/,\ >> +uncore_l3c_0_0/inv_request/ sleep 1 >> + >> +The driver does not support sampling, therefore "perf record" will >> +not work. Per-task (without "-a") perf sessions are not supported. >> > > > -- > ~Randy thanks Ganapat -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: gklkml16@gmail.com (Ganapatrao Kulkarni) Date: Fri, 27 Apr 2018 10:19:59 +0530 Subject: [PATCH v4 1/2] perf: uncore: Adding documentation for ThunderX2 pmu uncore driver In-Reply-To: <7c8ff675-2b27-8e7b-f046-513b73f1ae5f@infradead.org> References: <20180425090047.6485-1-ganapatrao.kulkarni@cavium.com> <20180425090047.6485-2-ganapatrao.kulkarni@cavium.com> <7c8ff675-2b27-8e7b-f046-513b73f1ae5f@infradead.org> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Apr 27, 2018 at 2:25 AM, Randy Dunlap wrote: > Hi, > > Just a few typo corrections... > > On 04/25/2018 02:00 AM, Ganapatrao Kulkarni wrote: >> Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC. >> The SoC has PMU support in its L3 cache controller (L3C) and in the >> DDR4 Memory Controller (DMC). >> >> Signed-off-by: Ganapatrao Kulkarni >> --- >> Documentation/perf/thunderx2-pmu.txt | 66 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 66 insertions(+) >> create mode 100644 Documentation/perf/thunderx2-pmu.txt >> >> diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt >> new file mode 100644 >> index 0000000..9e9f535 >> --- /dev/null >> +++ b/Documentation/perf/thunderx2-pmu.txt >> @@ -0,0 +1,66 @@ >> + >> +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) >> +========================================================================== >> + >> +ThunderX2 SoC PMU consists of independent system wide per Socket PMUs such >> +as Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). >> + >> +It has 8 independent DMC PMUs to capture performance events corresponding >> +to 8 channels of DDR4 Memory Controller. There are 16 independent L3C PMUs >> +to capture events corresponding to 16 tiles of L3 cache. Each PMU supports >> +up to 4 counters. >> + >> +Counters are independent programmable and can be started and stopped > > independently thanks, will update. > >> +individually. Each counter can be set to sample specific perf events. >> +Counters are 32 bit and does not support overflow interrupt, they are > > do not interrupt; they are > > >> +sampled at every 2 seconds. The Counters register access are multiplexed >> +across channels of DMC and L3C. The muxing(select channel) is done through >> +write to a Secure register using smcc calls. >> + >> +PMU UNCORE (perf) driver: >> + >> +The thunderx2-pmu driver registers several perf PMUs for DMC and L3C devices. >> +Each of the PMU provides description of its available events > > of the PMUs > >> +and configuration options in sysfs. >> + see /sys/devices/uncore_ >> + >> +S is socket id and X represents channel number. >> +Each PMU can be used to sample up to 4 events simultaneously. >> + >> +The "format" directory describes format of the config (event ID). >> +The "events" directory provides configuration templates for all >> +supported event types that can be used with perf tool. >> + >> +For example, "uncore_dmc_0_0/cnt_cycles/" is an >> +equivalent of "uncore_dmc_0_0/config=0x1/". >> + >> +Each perf driver also provides a "cpumask" sysfs attribute, which contains a >> +single CPU ID of the processor which is likely to be used to handle all the >> +PMU events. It will be the first online CPU from the NUMA node of PMU device. >> + >> +Example for perf tool use: >> + >> +perf stat -a -e \ >> +uncore_dmc_0_0/cnt_cycles/,\ >> +uncore_dmc_0_1/cnt_cycles/,\ >> +uncore_dmc_0_2/cnt_cycles/,\ >> +uncore_dmc_0_3/cnt_cycles/,\ >> +uncore_dmc_0_4/cnt_cycles/,\ >> +uncore_dmc_0_5/cnt_cycles/,\ >> +uncore_dmc_0_6/cnt_cycles/,\ >> +uncore_dmc_0_7/cnt_cycles/ sleep 1 >> + >> +perf stat -a -e \ >> +uncore_dmc_0_0/cancelled_read_txns/,\ >> +uncore_dmc_0_0/cnt_cycles/,\ >> +uncore_dmc_0_0/consumed_read_txns/,\ >> +uncore_dmc_0_0/data_transfers/ sleep 1 >> + >> +perf stat -a -e \ >> +uncore_l3c_0_0/l3_retry/,\ >> +uncore_l3c_0_0/read_hit/,\ >> +uncore_l3c_0_0/read_request/,\ >> +uncore_l3c_0_0/inv_request/ sleep 1 >> + >> +The driver does not support sampling, therefore "perf record" will >> +not work. Per-task (without "-a") perf sessions are not supported. >> > > > -- > ~Randy thanks Ganapat