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Wed, 11 Aug 2021 02:56:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=d79Tf0Zb7I6G6e12dIIYv9kMTOu17xxaJFmQXGUEDBk=; b=KA6WCr8ys3IPV39ETR4eeVQP+GzggvE9KSJ5Zad9qcZ+LsIt+nIXf5KtAmV7oG4BzU urFwhr7BUzO/QIWATU+iYSijVFz59goBrQ14/nB8ikPZTbPirYimre9zeD43OwOAmK2u MuL2x8FxrP+/oJ/7/wI4dL1a6Rn88MyJA/iIWOUnv60dpp16PK8XvINjRuSSWzm23ZyO 1Zr7QxWQ6JPowycnmWSwPee+koa0TAW2NdLNEQB9LEh0GuyebvWsdFKUIJTVGPgLgm4j fX+0kx/1+k2r9WefcmlGzxFqwB25aokM76Dlo05rxFHH+LHIy9aNwwHTmthHERxnNxQn aZJA== X-Gm-Message-State: AOAM530+h4qZsEvffRn1DFACFAYoyI6CR4A5e4CYBcRuOn2/rWn441/Z rMxeb1nXiPtsLmnqDecemZToYaDTJphGmKw1Iug= X-Google-Smtp-Source: ABdhPJzkBspVRfyE21UfAtjlGSrMcJp0pzMW83Ccl9aUOUjqnhgTLRkXcJVutzGDo8BYcyeTvRCvCgFRKeAkCuMABq0= X-Received: by 2002:a6b:fc1a:: with SMTP id r26mr108436ioh.30.1628675795392; Wed, 11 Aug 2021 02:56:35 -0700 (PDT) MIME-Version: 1.0 References: <20210629082443.22308-1-yifeng.zhao@rock-chips.com> <20210629082443.22308-3-yifeng.zhao@rock-chips.com> In-Reply-To: <20210629082443.22308-3-yifeng.zhao@rock-chips.com> From: Kever Yang Date: Wed, 11 Aug 2021 17:56:24 +0800 Message-ID: Subject: Re: [PATCH v3 2/3] mmc: rockchip_sdhci: Add support for RK3568 To: Yifeng Zhao Cc: Jaehoon Chung , sjg , Kever Yang , Peng Fan , Philipp Tomsich , U-Boot-Denx Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Yifeng Zhao =E4=BA=8E2021=E5=B9=B46=E6=9C=8829= =E6=97=A5=E5=91=A8=E4=BA=8C =E4=B8=8B=E5=8D=887:40=E5=86=99=E9=81=93=EF=BC= =9A > > This patch adds support for the RK3568 platform to this driver. > > Signed-off-by: Yifeng Zhao Reviewed-by: Kever Yang Thanks, - Kever > --- > > Changes in v3: > - Config the interface clock by clk_set_rate directly > > Changes in v2: > - Used sdhci_set_clock api to set clock. > - Used read_poll_timeout api to check dll status. > > drivers/mmc/rockchip_sdhci.c | 109 +++++++++++++++++++++++++++++++++++ > 1 file changed, 109 insertions(+) > > diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c > index eff134c8f5..1ac00587d4 100644 > --- a/drivers/mmc/rockchip_sdhci.c > +++ b/drivers/mmc/rockchip_sdhci.c > @@ -42,6 +42,34 @@ > ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) =3D=3D\ > PHYCTRL_DLLRDY_DONE) > > +/* Rockchip specific Registers */ > +#define DWCMSHC_EMMC_DLL_CTRL 0x800 > +#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) > +#define DWCMSHC_EMMC_DLL_RXCLK 0x804 > +#define DWCMSHC_EMMC_DLL_TXCLK 0x808 > +#define DWCMSHC_EMMC_DLL_STRBIN 0x80c > +#define DWCMSHC_EMMC_DLL_STATUS0 0x840 > +#define DWCMSHC_EMMC_DLL_STATUS1 0x844 > +#define DWCMSHC_EMMC_DLL_START BIT(0) > +#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 > +#define DWCMSHC_EMMC_DLL_START_POINT 16 > +#define DWCMSHC_EMMC_DLL_START_DEFAULT 5 > +#define DWCMSHC_EMMC_DLL_INC_VALUE 2 > +#define DWCMSHC_EMMC_DLL_INC 8 > +#define DWCMSHC_EMMC_DLL_DLYENA BIT(27) > +#define DLL_TXCLK_TAPNUM_DEFAULT 0x10 > +#define DLL_STRBIN_TAPNUM_DEFAULT 0x3 > +#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) > +#define DWCMSHC_EMMC_DLL_LOCKED BIT(8) > +#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) > +#define DLL_RXCLK_NO_INVERTER 1 > +#define DLL_RXCLK_INVERTER 0 > +#define DWCMSHC_ENHANCED_STROBE BIT(8) > +#define DLL_LOCK_WO_TMOUT(x) \ > + ((((x) & DWCMSHC_EMMC_DLL_LOCKED) =3D=3D DWCMSHC_EMMC_DLL_LOCKED)= && \ > + (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) =3D=3D 0)) > +#define ROCKCHIP_MAX_CLKS 3 > + > struct rockchip_sdhc_plat { > struct mmc_config cfg; > struct mmc mmc; > @@ -167,6 +195,77 @@ static int rk3399_sdhci_emmc_set_clock(struct sdhci_= host *host, unsigned int clo > return 0; > } > > +static int rk3568_emmc_phy_init(struct udevice *dev) > +{ > + struct rockchip_sdhc *prv =3D dev_get_priv(dev); > + struct sdhci_host *host =3D &prv->host; > + u32 extra; > + > + extra =3D DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; > + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); > + > + return 0; > +} > + > +static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned= int clock) > +{ > + struct rockchip_sdhc *priv =3D container_of(host, struct rockchip= _sdhc, host); > + int val, ret; > + u32 extra; > + > + if (clock > host->max_clk) > + clock =3D host->max_clk; > + if (clock) > + clk_set_rate(&priv->emmc_clk, clock); > + > + sdhci_set_clock(host->mmc, clock); > + > + if (clock >=3D 100 * MHz) { > + /* reset DLL */ > + sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_E= MMC_DLL_CTRL); > + udelay(1); > + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); > + > + /* Init DLL settings */ > + extra =3D DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_= DLL_START_POINT | > + DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_IN= C | > + DWCMSHC_EMMC_DLL_START; > + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); > + > + ret =3D read_poll_timeout(readl, host->ioaddr + DWCMSHC_E= MMC_DLL_STATUS0, > + val, DLL_LOCK_WO_TMOUT(val), 1, 5= 00); > + if (ret) > + return ret; > + > + extra =3D DWCMSHC_EMMC_DLL_DLYENA | > + DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_S= RCSEL; > + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); > + > + extra =3D DWCMSHC_EMMC_DLL_DLYENA | > + DLL_TXCLK_TAPNUM_DEFAULT | > + DLL_TXCLK_TAPNUM_FROM_SW; > + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); > + > + extra =3D DWCMSHC_EMMC_DLL_DLYENA | > + DLL_STRBIN_TAPNUM_DEFAULT; > + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); > + } else { > + /* reset the clock phase when the frequency is lower than= 100MHz */ > + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); > + extra =3D DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK= _SRCSEL; > + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); > + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); > + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); > + } > + > + return 0; > +} > + > +static int rk3568_emmc_get_phy(struct udevice *dev) > +{ > + return 0; > +} > + > static int rockchip_sdhci_set_ios_post(struct sdhci_host *host) > { > struct rockchip_sdhc *priv =3D container_of(host, struct rockchip= _sdhc, host); > @@ -339,11 +438,21 @@ static const struct sdhci_data rk3399_data =3D { > .emmc_phy_init =3D rk3399_emmc_phy_init, > }; > > +static const struct sdhci_data rk3568_data =3D { > + .emmc_set_clock =3D rk3568_sdhci_emmc_set_clock, > + .get_phy =3D rk3568_emmc_get_phy, > + .emmc_phy_init =3D rk3568_emmc_phy_init, > +}; > + > static const struct udevice_id sdhci_ids[] =3D { > { > .compatible =3D "arasan,sdhci-5.1", > .data =3D (ulong)&rk3399_data, > }, > + { > + .compatible =3D "rockchip,rk3568-dwcmshc", > + .data =3D (ulong)&rk3568_data, > + }, > { } > }; > > -- > 2.17.1 > > >