[Qemu-devel] [PATCH] target-arm: Don't permit ARMv8-only Neon insns on ARMv7

[Qemu-devel] [PATCH] target-arm: Don't permit ARMv8-only Neon insns on ARMv7

[Peter Maydell]

The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM,
VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8,
so they need a guard to make them UNDEF if the CPU only supports ARMv7.
(We got this right for all the other new-in-v8 insns, but forgot
it for these Neon 2-reg-misc ops.)

Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Christophe: I'd appreciate it if you could give this a quick test
and confirm that it fixes the bug for you.

 target-arm/translate.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6815bc1..3e71467 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -5311,6 +5311,30 @@ static int neon_2rm_is_float_op(int op)
             op >= NEON_2RM_VRECPE_F);
 }
 
+static bool neon_2rm_is_v8_op(int op)
+{
+    /* Return true if this neon 2reg-misc op is ARMv8 and up */
+    switch (op) {
+    case NEON_2RM_VRINTN:
+    case NEON_2RM_VRINTA:
+    case NEON_2RM_VRINTM:
+    case NEON_2RM_VRINTP:
+    case NEON_2RM_VRINTZ:
+    case NEON_2RM_VRINTX:
+    case NEON_2RM_VCVTAU:
+    case NEON_2RM_VCVTAS:
+    case NEON_2RM_VCVTNU:
+    case NEON_2RM_VCVTNS:
+    case NEON_2RM_VCVTPU:
+    case NEON_2RM_VCVTPS:
+    case NEON_2RM_VCVTMU:
+    case NEON_2RM_VCVTMS:
+        return true;
+    default:
+        return false;
+    }
+}
+
 /* Each entry in this array has bit n set if the insn allows
  * size value n (otherwise it will UNDEF). Since unallocated
  * op values will have no bits set they always UNDEF.
@@ -6798,6 +6822,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
                     return 1;
                 }
+                if (neon_2rm_is_v8_op(op) &&
+                    !arm_dc_feature(s, ARM_FEATURE_V8)) {
+                    return 1;
+                }
                 if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
                     q && ((rm | rd) & 1)) {
                     return 1;
-- 
1.9.1

Re: [Qemu-devel] [PATCH] target-arm: Don't permit ARMv8-only Neon insns on ARMv7

[Christophe Lyon]

On 9 June 2016 at 19:15, Peter Maydell <peter.maydell@linaro.org> wrote:
> The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM,
> VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8,
> so they need a guard to make them UNDEF if the CPU only supports ARMv7.
> (We got this right for all the other new-in-v8 insns, but forgot
> it for these Neon 2-reg-misc ops.)
>
> Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Christophe: I'd appreciate it if you could give this a quick test
> and confirm that it fixes the bug for you.
>

I confirm it does, thanks!


>  target-arm/translate.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 6815bc1..3e71467 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -5311,6 +5311,30 @@ static int neon_2rm_is_float_op(int op)
>              op >= NEON_2RM_VRECPE_F);
>  }
>
> +static bool neon_2rm_is_v8_op(int op)
> +{
> +    /* Return true if this neon 2reg-misc op is ARMv8 and up */
> +    switch (op) {
> +    case NEON_2RM_VRINTN:
> +    case NEON_2RM_VRINTA:
> +    case NEON_2RM_VRINTM:
> +    case NEON_2RM_VRINTP:
> +    case NEON_2RM_VRINTZ:
> +    case NEON_2RM_VRINTX:
> +    case NEON_2RM_VCVTAU:
> +    case NEON_2RM_VCVTAS:
> +    case NEON_2RM_VCVTNU:
> +    case NEON_2RM_VCVTNS:
> +    case NEON_2RM_VCVTPU:
> +    case NEON_2RM_VCVTPS:
> +    case NEON_2RM_VCVTMU:
> +    case NEON_2RM_VCVTMS:
> +        return true;
> +    default:
> +        return false;
> +    }
> +}
> +
>  /* Each entry in this array has bit n set if the insn allows
>   * size value n (otherwise it will UNDEF). Since unallocated
>   * op values will have no bits set they always UNDEF.
> @@ -6798,6 +6822,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>                  if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
>                      return 1;
>                  }
> +                if (neon_2rm_is_v8_op(op) &&
> +                    !arm_dc_feature(s, ARM_FEATURE_V8)) {
> +                    return 1;
> +                }
>                  if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
>                      q && ((rm | rd) & 1)) {
>                      return 1;
> --
> 1.9.1
>