Re: Questions about bringing up MT7623 board

[Kristian Evensen <kristian.evensen-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

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Hello,

On Mon, Feb 12, 2018 at 3:49 PM, Kristian Evensen
<kristian.evensen-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Great, thanks for letting me know. My 4.9-DTS is just a slightly
> modified version of the eMMC-DTS, the only changes I made was to
> update bootargs and switch configuration. So adding upstream support
> should, fingers crossed, be quite fast. My main motivation for adding
> upstream support, in addition to it being fun, interesting and maybe
> can help someone else, is to see if I can get the USB OTG port on the
> board working. The port works with proprietary firmware I got with the
> device, but not with 4.9 and I was not able to get a good answer on
> how to enable it from the vendor. I see patches related to MT7623 and
> USB, but nothing mentioning USB OTG specifically. Has there been any
> work on the OTG-port, or should it "just" work out of the box? The
> reason I am trying to get the OTG-port to work, is that the vendor has
> connect a modem (via mini-PCIe) to this port.

I finally got around to working on my mt7623-board again. As a
starting point for having an easy way of building kernel + rootfs, I
used OpenWRT and the eMMC reference board-dts. I copied the dts,
updated the bootargs + memory node and then added missing nodes by
copying the most recent DTS' that I could find (usually in patches on
the mailing list or the linux-mediatek Github repo). For example, my
board uses pcie, which is not in the OpenWRT reference board dts. I
have attached my WIP patch in case anyone is curios or has time to
look. My DTS probably contains several nodes that are not needed, but
I would like to have as much as possible up and running before putting
the file on a diet.

With the patch above, I am able to bring the board up, networking
works, the USB port on the front of my device works and I can mess
around with the rootfs. However, two things do not not work and I am
starting to run out of ideas of what to try:

* My board is equipped with a 2.4GHz and a 5GHz wifi card, both
connected via PCIe. The 2.4 card is connected to a "pure" PCIe-slot
(pcie@1,0), while the 5GHz uses the slot that is shared between PCIe
and USB3.0 (I think this is pcie@2,0). Based on my naive
understanding, in order to enable this slot (as PCIe), I should set
u3phy2 to okay (since phy is u3port1 in dtsi), but not enable usb2.
However, when I set u3phy2 to okay, the 2.4GHz card disappears as well
and I can no long see the PCI bridge (output from lspci is empty). If
I don't add the u3phy2-node, then the 2.4Ghz card appears, but no
5GHz. Does anyone know how to make this slot work in PCIe-mode? I
tried with pcie@0,0 instead of pcie@2,0 as well, but it did not have
an effect.

* The board has a PCIe slot connected to the USB OTG-port, intended
for use together with modems. This slot is not working with my kernel
and for example the modem does not show up when I do lsusb. I have
been doing some digging, but so far turned up blank. Does anyone have
any pointers on where to look or where to start in order to add
support for this port? I see that the port + modem works with the
vendor firmware, but I have not been able to figure out which steps
they take to activate it.

* The following message is written to the log a couple of times during boot:

[    2.341219] ------------[ cut here ]------------
[    2.341225] WARNING: CPU: 3 PID: 65 at drivers/clk/clk.c:476
clk_unprepare+0x24/0x2c
[    2.341227] Modules linked in:
[    2.341233] CPU: 3 PID: 65 Comm: kworker/3:1 Tainted: G        W
   4.14.36 #0
[    2.341236] Hardware name: Mediatek Cortex-A7 (Device Tree)
[    2.341241] Workqueue: pm genpd_power_off_work_fn
[    2.341250] [<c010f054>] (unwind_backtrace) from [<c010b1f4>]
(show_stack+0x10/0x14)
[    2.341259] [<c010b1f4>] (show_stack) from [<c0540f9c>]
(dump_stack+0x78/0x8c)
[    2.341267] [<c0540f9c>] (dump_stack) from [<c01172e8>] (__warn+0xe4/0x100)
[    2.341273] [<c01172e8>] (__warn) from [<c01173b4>]
(warn_slowpath_null+0x20/0x28)
[    2.341281] [<c01173b4>] (warn_slowpath_null) from [<c031c4d4>]
(clk_unprepare+0x24/0x2c)
[    2.341289] [<c031c4d4>] (clk_unprepare) from [<c03260c0>]
(scpsys_power_off+0x130/0x1cc)
[    2.341297] [<c03260c0>] (scpsys_power_off) from [<c0361348>]
(genpd_power_off+0x17c/0x244)
[    2.341305] [<c0361348>] (genpd_power_off) from [<c0361bf8>]
(genpd_power_off_work_fn+0x2c/0x40)
[    2.341313] [<c0361bf8>] (genpd_power_off_work_fn) from
[<c012cd4c>] (process_one_work+0x22c/0x3d0)
[    2.341320] [<c012cd4c>] (process_one_work) from [<c012dc14>]
(worker_thread+0x308/0x524)
[    2.341327] [<c012dc14>] (worker_thread) from [<c0132464>]
(kthread+0x12c/0x138)
[    2.341335] [<c0132464>] (kthread) from [<c0107a08>]
(ret_from_fork+0x14/0x2c)
[    2.341337] ---[ end trace 7b1c61fe23a78e39 ]---

Error does not seem critical, board works fine, so not sure if this is
something to worry about or not.

Thanks in advance for any help!

BR,
Kristian

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From b2c29ea45d5df714e94bb278d53daafe9274f596 Mon Sep 17 00:00:00 2001
From: Kristian Evensen <kristian.evensen@gmail.com>
Date: Sun, 29 Apr 2018 17:07:36 +0200
Subject: [PATCH] U7623 4.14 patch

---
 .../mediatek/base-files/etc/board.d/02_network     |   3 +-
 .../mediatek/base-files/lib/upgrade/platform.sh    |   3 +-
 target/linux/mediatek/image/32.mk                  |   2 +
 .../mediatek/patches-4.14/0065-u7623-dts.patch     | 676 +++++++++++++++++++++
 4 files changed, 682 insertions(+), 2 deletions(-)
 create mode 100644 target/linux/mediatek/patches-4.14/0065-u7623-dts.patch

diff --git a/target/linux/mediatek/base-files/etc/board.d/02_network b/target/linux/mediatek/base-files/etc/board.d/02_network
index 8015cf3cc2..39d9ca8cc5 100755
--- a/target/linux/mediatek/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/base-files/etc/board.d/02_network
@@ -13,7 +13,8 @@ mediatek_setup_interfaces()
 		ucidef_set_interface_lan "lan0 lan1 lan2 lan3"
 		ucidef_set_interface_wan eth1
 		;;
-	'bananapi,bpi-r2') 
+	'bananapi,bpi-r2'|\
+	'unielec,u7623')
 		ucidef_set_interface_lan "lan0 lan1 lan2 lan3"
 		ucidef_set_interface_wan wan
 		;;
diff --git a/target/linux/mediatek/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/base-files/lib/upgrade/platform.sh
index 0429ca8b89..de78193f37 100755
--- a/target/linux/mediatek/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/base-files/lib/upgrade/platform.sh
@@ -29,7 +29,8 @@ platform_check_image() {
 
 	case "$board" in
 	bananapi,bpi-r2 |\
-	mediatek,mt7623a-rfb-emmc)
+	mediatek,mt7623a-rfb-emmc |\
+	unielec,u7623)
 		local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null`
 		local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null`
 		;;
diff --git a/target/linux/mediatek/image/32.mk b/target/linux/mediatek/image/32.mk
index 7b7e303124..83127592ed 100644
--- a/target/linux/mediatek/image/32.mk
+++ b/target/linux/mediatek/image/32.mk
@@ -22,6 +22,7 @@ endef
 
 COMPAT_BPI-R2:=bananapi,bpi-r2
 COMPAT_EMMC:=mediatek,mt7623a-rfb-emmc
+COMPAT_U7623:=unielec,u7623
 
 define Image/Build/squashfs
 	$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
@@ -29,4 +30,5 @@ define Image/Build/squashfs
 
 	$(call Image/Build/SysupgradeCombined,mt7623n-bananapi-bpi-r2,squashfs,$$(COMPAT_BPI-R2))
 	$(call Image/Build/SysupgradeCombined,mt7623a-rfb-emmc,squashfs,$$(COMPAT_EMMC))
+	$(call Image/Build/SysupgradeCombined,mt7623a-unielec-u7623,squashfs,$$(COMPAT_U7623))
 endef
diff --git a/target/linux/mediatek/patches-4.14/0065-u7623-dts.patch b/target/linux/mediatek/patches-4.14/0065-u7623-dts.patch
new file mode 100644
index 0000000000..4368f7ba2e
--- /dev/null
+++ b/target/linux/mediatek/patches-4.14/0065-u7623-dts.patch
@@ -0,0 +1,676 @@
+From 8b580250d31b679f9e3a71f5f9dc2edd883b0a34 Mon Sep 17 00:00:00 2001
+From: Kristian Evensen <kristian.evensen@gmail.com>
+Date: Sun, 29 Apr 2018 17:01:58 +0200
+Subject: [PATCH] Add U7623 DTS
+
+---
+ arch/arm/boot/dts/Makefile                  |   1 +
+ arch/arm/boot/dts/mt7623.dtsi               | 104 ++++++
+ arch/arm/boot/dts/mt7623a-unielec-u7623.dts | 528 ++++++++++++++++++++++++++++
+ 3 files changed, 633 insertions(+)
+ create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 3fec84fa0..3fdda8427 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ 	mt6589-aquaris5.dtb \
+ 	mt6592-evb.dtb \
+ 	mt7623a-rfb-emmc.dtb \
++	mt7623a-unielec-u7623.dtb \
+ 	mt7623n-rfb-nand.dtb \
+ 	mt7623n-bananapi-bpi-r2.dtb \
+ 	mt8127-moose.dtb \
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+index 09798f37a..a027a4975 100644
+--- a/arch/arm/boot/dts/mt7623.dtsi
++++ b/arch/arm/boot/dts/mt7623.dtsi
+@@ -670,6 +670,110 @@
+ 		#reset-cells = <1>;
+ 	};
+ 
++	pcie: pcie@1a140000 {
++		compatible = "mediatek,mt7623-pcie";
++		device_type = "pci";
++		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
++		      <0 0x1a142000 0 0x1000>, /* Port0 registers */
++		      <0 0x1a143000 0 0x1000>, /* Port1 registers */
++		      <0 0x1a144000 0 0x1000>; /* Port2 registers */
++		reg-names = "subsys", "port0", "port1", "port2";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0xf800 0 0 0>;
++		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
++				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
++				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
++			 <&hifsys CLK_HIFSYS_PCIE0>,
++			 <&hifsys CLK_HIFSYS_PCIE1>,
++			 <&hifsys CLK_HIFSYS_PCIE2>;
++		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
++		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
++			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
++			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
++		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
++		phys = <&pcie0_port PHY_TYPE_PCIE>,
++		       <&pcie1_port PHY_TYPE_PCIE>,
++		       <&u3port1 PHY_TYPE_PCIE>;
++		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
++		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
++		bus-range = <0x00 0xff>;
++		status = "disabled";
++		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
++			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
++
++		pcie@0,0 {
++			reg = <0x0000 0 0 0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
++			ranges;
++			num-lanes = <1>;
++			status = "disabled";
++		};
++		pcie@1,0 {
++			reg = <0x0800 0 0 0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
++			ranges;
++			num-lanes = <1>;
++			status = "disabled";
++		};
++
++		pcie@2,0 {
++			reg = <0x1000 0 0 0 0>;
++			#address-cells = <3>;
++			#size-cells = <2>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0>;
++			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
++			ranges;
++			num-lanes = <1>;
++			status = "disabled";
++		};
++	};
++
++	pcie0_phy: pcie-phy@1a149000 {
++		compatible = "mediatek,generic-tphy-v1";
++		reg = <0 0x1a149000 0 0x0700>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		status = "disabled";
++
++		pcie0_port: pcie-phy@1a149900 {
++			reg = <0 0x1a149900 0 0x0700>;
++			clocks = <&clk26m>;
++			clock-names = "ref";
++			#phy-cells = <1>;
++			status = "okay";
++		};
++	};
++
++	pcie1_phy: pcie-phy@1a14a000 {
++		compatible = "mediatek,generic-tphy-v1";
++		reg = <0 0x1a14a000 0 0x0700>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		status = "disabled";
++
++		pcie1_port: pcie-phy@1a14a900 {
++			reg = <0 0x1a14a900 0 0x0700>;
++			clocks = <&clk26m>;
++			clock-names = "ref";
++			#phy-cells = <1>;
++			status = "okay";
++		};
++	};
++
+ 	usb1: usb@1a1c0000 {
+ 		compatible = "mediatek,mt7623-xhci",
+ 			     "mediatek,mt8173-xhci";
+diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623.dts
+new file mode 100644
+index 000000000..066b25bb4
+--- /dev/null
++++ b/arch/arm/boot/dts/mt7623a-unielec-u7623.dts
+@@ -0,0 +1,528 @@
++/*
++ * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++ */
++
++/dts-v1/;
++#include <dt-bindings/input/input.h>
++#include "mt7623.dtsi"
++#include "mt6323.dtsi"
++
++/ {
++	model = "Unielec U7623 512MB RAM/8GB eMMC";
++	compatible = "unielec,u7623", "mediatek,mt7623";
++
++	aliases {
++		serial2 = &uart2;
++	};
++
++	chosen {
++		bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),6144M(userdata),-(bmtpool) root=/dev/mtdblock6 rootfstype=squashfs,jffs2";
++		stdout-path = "serial2:115200n8";
++	};
++
++	memory {
++		reg = <0 0x80000000 0 0x10000000>;
++	};
++
++	cpus {
++		cpu@0 {
++			proc-supply = <&mt6323_vproc_reg>;
++		};
++
++		cpu@1 {
++			proc-supply = <&mt6323_vproc_reg>;
++		};
++
++		cpu@2 {
++			proc-supply = <&mt6323_vproc_reg>;
++		};
++
++		cpu@3 {
++			proc-supply = <&mt6323_vproc_reg>;
++		};
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_5v: regulator-5v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-5V";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	memory@80000000 {
++		reg = <0 0x80000000 0 0x40000000>;
++	};
++
++	mt7530: switch@0 {
++		compatible = "mediatek,mt7530";
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++};
++
++&crypto {
++	status = "okay";
++};
++
++&eth {
++	status = "okay";
++
++	gmac0: mac@0 {
++		compatible = "mediatek,eth-mac";
++		reg = <0>;
++		phy-mode = "trgmii";
++
++		fixed-link {
++			speed = <1000>;
++			full-duplex;
++			pause;
++		};
++	};
++
++	mdio: mdio-bus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		phy5: ethernet-phy@5 {
++			reg = <5>;
++			phy-mode = "rgmii-rxid";
++		};
++	};
++};
++
++&mt7530 {
++	compatible = "mediatek,mt7530";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	reg = <0>;
++	pinctrl-names = "default";
++	mediatek,mcm;
++	resets = <&ethsys 2>;
++	reset-names = "mcm";
++	core-supply = <&mt6323_vpa_reg>;
++	io-supply = <&mt6323_vemc3v3_reg>;
++
++	dsa,mii-bus = <&mdio>;
++
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0>;
++
++		port@0 {
++			reg = <0>;
++			label = "lan0";
++			cpu = <&cpu_port0>;
++		};
++
++		port@1 {
++			reg = <1>;
++			label = "lan1";
++			cpu = <&cpu_port0>;
++		};
++
++		port@2 {
++			reg = <2>;
++			label = "lan2";
++			cpu = <&cpu_port0>;
++		};
++
++		port@3 {
++			reg = <3>;
++			label = "lan3";
++			cpu = <&cpu_port0>;
++		};
++
++		port@4 {
++			reg = <4>;
++			label = "wan";
++			cpu = <&cpu_port0>;
++		};
++
++		cpu_port0: port@6 {
++			reg = <6>;
++			label = "cpu";
++			ethernet = <&gmac0>;
++			phy-mode = "trgmii";
++
++			fixed-link {
++				speed = <1000>;
++				full-duplex;
++			};
++		};
++	};
++};
++
++&i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0_pins_a>;
++	status = "okay";
++};
++
++&i2c1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pins_b>;
++	status = "okay";
++};
++
++&i2c2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c2_pins_b>;
++	status = "okay";
++};
++
++&mmc0 {
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc0_pins_default>;
++	pinctrl-1 = <&mmc0_pins_uhs>;
++	status = "okay";
++	bus-width = <8>;
++	max-frequency = <50000000>;
++	cap-mmc-highspeed;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	non-removable;
++};
++
++&mmc1 {
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc1_pins_default>;
++	pinctrl-1 = <&mmc1_pins_uhs>;
++	status = "okay";
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	cap-sd-highspeed;
++	cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_3p3v>;
++};
++
++&pio {
++	cir_pins_a:cir@0 {
++		pins_cir {
++			pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
++			bias-disable;
++		};
++	};
++
++	i2c0_pins_a: i2c@0 {
++		pins_i2c0 {
++			pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
++				 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
++			bias-disable;
++		};
++	};
++
++	i2c1_pins_b: i2c@1 {
++		pin_i2c1 {
++			pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
++				 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
++			bias-disable;
++		};
++	};
++
++	i2c2_pins_b: i2c@2 {
++		pin_i2c2 {
++			pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
++				 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
++			bias-disable;
++		};
++	};
++
++	i2s0_pins_a: i2s@0 {
++		pin_i2s0 {
++			pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
++				 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
++				 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
++				 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
++				 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
++			drive-strength = <MTK_DRIVE_12mA>;
++			bias-pull-down;
++		};
++	};
++
++	i2s1_pins_a: i2s@1 {
++		pin_i2s1 {
++			pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
++				 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
++				 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
++				 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
++				 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
++			drive-strength = <MTK_DRIVE_12mA>;
++			bias-pull-down;
++		};
++	};
++
++	mmc0_pins_default: mmc0default {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
++				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
++				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
++				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
++				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
++				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
++				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
++				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
++				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
++			input-enable;
++			bias-pull-up;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
++			bias-pull-down;
++		};
++
++		pins_rst {
++			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
++			bias-pull-up;
++		};
++	};
++
++	mmc0_pins_uhs: mmc0 {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
++				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
++				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
++				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
++				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
++				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
++				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
++				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
++				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
++			input-enable;
++			drive-strength = <MTK_DRIVE_2mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
++			drive-strength = <MTK_DRIVE_2mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
++		};
++
++		pins_rst {
++			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
++			bias-pull-up;
++		};
++	};
++
++	mmc1_pins_default: mmc1default {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
++				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
++				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
++				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
++				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
++			input-enable;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
++			bias-pull-down;
++			drive-strength = <MTK_DRIVE_4mA>;
++		};
++
++		pins_wp {
++			pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
++			input-enable;
++			bias-pull-up;
++		};
++
++		pins_insert {
++			pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
++			bias-pull-up;
++		};
++	};
++
++	mmc1_pins_uhs: mmc1 {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
++				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
++				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
++				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
++				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
++			input-enable;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
++		};
++
++		pins_clk {
++			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
++			drive-strength = <MTK_DRIVE_4mA>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
++		};
++	};
++
++	pwm_pins_a: pwm@0 {
++		pins_pwm {
++			pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
++				 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
++				 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
++				 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
++				 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
++		};
++	};
++
++	spi0_pins_a: spi@0 {
++		pins_spi {
++			pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
++				<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
++				<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
++				<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
++			bias-disable;
++		};
++	};
++
++	spi1_pins_a: spi@1 {
++		pins_spi {
++			pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
++				<MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
++				<MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>,
++				<MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>;
++			bias-disable;
++		};
++	};
++
++	uart0_pins_a: uart@0 {
++		pins_dat {
++			pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
++				 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
++		};
++	};
++
++	uart1_pins_a: uart@1 {
++		pins_dat {
++			pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
++				 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
++		};
++	};
++
++	uart2_pins_b: uart@2 {
++		pins_dat {
++			pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
++				 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
++		};
++	};
++
++	pcie_default: pcie_pin_default {
++		pins_cmd_dat {
++			pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
++				 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
++			bias-disable;
++		};
++	};
++};
++
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins_a>;
++	status = "okay";
++};
++
++&pwrap {
++	mt6323 {
++		mt6323led: led {
++			compatible = "mediatek,mt6323-led";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			led@0 {
++				reg = <0>;
++				label = "led0";
++				default-state = "off";
++			};
++
++			led@1 {
++				reg = <1>;
++				label = "led1";
++				default-state = "off";
++			};
++
++			led@2 {
++				reg = <2>;
++				label = "led2";
++				default-state = "off";
++			};
++		};
++	};
++};
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins_a>;
++	status = "okay";
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins_a>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins_b>;
++	status = "okay";
++};
++
++&usb1 {
++	vusb33-supply = <&reg_3p3v>;
++	vbus-supply = <&reg_3p3v>;
++	status = "okay";
++};
++
++&u3phy1 {
++	status = "okay";
++};
++
++/*&usb2 {
++	vusb33-supply = <&reg_3p3v>;
++	vbus-supply = <&reg_3p3v>;
++	status = "okay";
++};
++
++&u3phy2 {
++	status = "okay";
++};*/
++
++&pcie {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_default>;
++	status = "okay";
++
++	pcie@1,0 {
++		status = "okay";
++	};
++
++/*	pcie@2,0 {
++		status = "okay";
++	};*/
++};
++
++&pcie1_phy {
++	status = "okay";
++};
+-- 
+2.14.1
+
-- 
2.14.1


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