From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751613AbdG0Rt3 (ORCPT ); Thu, 27 Jul 2017 13:49:29 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:38394 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751030AbdG0Rt0 (ORCPT ); Thu, 27 Jul 2017 13:49:26 -0400 MIME-Version: 1.0 In-Reply-To: <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> References: <1499955692-26556-1-git-send-email-dingtianhong@huawei.com> <1499955692-26556-3-git-send-email-dingtianhong@huawei.com> <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> <67be791f-e0cf-8284-9229-17174dc741ef@codeaurora.org> <5f9b8bfb-41a8-a17c-6fea-581aec1d5573@huawei.com> <20170724090516.2e0f0d2a@w520.home> <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> From: Alexander Duyck Date: Thu, 27 Jul 2017 10:49:25 -0700 Message-ID: Subject: Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported To: Ding Tianhong Cc: Casey Leedom , Alex Williamson , Sinan Kaya , "ashok.raj@intel.com" , "bhelgaas@google.com" , "helgaas@kernel.org" , Michael Werner , Ganesh GR , "asit.k.mallick@intel.com" , "patrick.j.cramer@intel.com" , "Suravee.Suthikulpanit@amd.com" , "Bob.Shaw@amd.com" , "l.stach@pengutronix.de" , "amira@mellanox.com" , "gabriele.paoloni@huawei.com" , "David.Laight@aculab.com" , "jeffrey.t.kirsher@intel.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "mark.rutland@arm.com" , "robin.murphy@arm.com" , "davem@davemloft.net" , "linux-arm-kernel@lists.infradead.org" , "netdev@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linuxarm@huawei.com" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 26, 2017 at 6:08 PM, Ding Tianhong wrote: > > > On 2017/7/27 2:26, Casey Leedom wrote: >> By the way Ding, two issues: >> >> 1. Did we ever get any acknowledgement from either Intel or AMD >> on this patch? I know that we can't ensure that, but it sure would >> be nice since the PCI Quirks that we're putting in affect their >> products. >> > > Still no Intel and AMD guys has ack this, this is what I am worried about, should I > ping some man again ? > > Thanks > Ding I probably wouldn't worry about it too much. If anything all this patch is doing is disabling relaxed ordering on the platforms we know have issues based on what Casey originally had. If nothing else we can follow up once the patches are in the kernel and if somebody has an issue then. You can include my acked-by, but it is mostly related to how this interacts with NICs, and not so much about the PCI chipsets themselves. Acked-by: Alexander Duyck From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Duyck Subject: Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported Date: Thu, 27 Jul 2017 10:49:25 -0700 Message-ID: References: <1499955692-26556-1-git-send-email-dingtianhong@huawei.com> <1499955692-26556-3-git-send-email-dingtianhong@huawei.com> <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> <67be791f-e0cf-8284-9229-17174dc741ef@codeaurora.org> <5f9b8bfb-41a8-a17c-6fea-581aec1d5573@huawei.com> <20170724090516.2e0f0d2a@w520.home> <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Cc: Casey Leedom , Alex Williamson , Sinan Kaya , "ashok.raj@intel.com" , "bhelgaas@google.com" , "helgaas@kernel.org" , Michael Werner , Ganesh GR , "asit.k.mallick@intel.com" , "patrick.j.cramer@intel.com" , "Suravee.Suthikulpanit@amd.com" , "Bob.Shaw@amd.com" , "l.stach@pengutronix.de" , "amira@mellanox.com" , "gabriele.paoloni@huawei.com" , "David.Laight@aculab.com" , "jeffrey.t.kirsher@int To: Ding Tianhong Return-path: In-Reply-To: <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org On Wed, Jul 26, 2017 at 6:08 PM, Ding Tianhong wrote: > > > On 2017/7/27 2:26, Casey Leedom wrote: >> By the way Ding, two issues: >> >> 1. Did we ever get any acknowledgement from either Intel or AMD >> on this patch? I know that we can't ensure that, but it sure would >> be nice since the PCI Quirks that we're putting in affect their >> products. >> > > Still no Intel and AMD guys has ack this, this is what I am worried about, should I > ping some man again ? > > Thanks > Ding I probably wouldn't worry about it too much. If anything all this patch is doing is disabling relaxed ordering on the platforms we know have issues based on what Casey originally had. If nothing else we can follow up once the patches are in the kernel and if somebody has an issue then. You can include my acked-by, but it is mostly related to how this interacts with NICs, and not so much about the PCI chipsets themselves. Acked-by: Alexander Duyck From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: MIME-Version: 1.0 In-Reply-To: <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> References: <1499955692-26556-1-git-send-email-dingtianhong@huawei.com> <1499955692-26556-3-git-send-email-dingtianhong@huawei.com> <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> <67be791f-e0cf-8284-9229-17174dc741ef@codeaurora.org> <5f9b8bfb-41a8-a17c-6fea-581aec1d5573@huawei.com> <20170724090516.2e0f0d2a@w520.home> <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> From: Alexander Duyck Date: Thu, 27 Jul 2017 10:49:25 -0700 Message-ID: Subject: Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported To: Ding Tianhong Cc: Casey Leedom , Alex Williamson , Sinan Kaya , "ashok.raj@intel.com" , "bhelgaas@google.com" , "helgaas@kernel.org" , Michael Werner , Ganesh GR , "asit.k.mallick@intel.com" , "patrick.j.cramer@intel.com" , "Suravee.Suthikulpanit@amd.com" , "Bob.Shaw@amd.com" , "l.stach@pengutronix.de" , "amira@mellanox.com" , "gabriele.paoloni@huawei.com" , "David.Laight@aculab.com" , "jeffrey.t.kirsher@intel.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "mark.rutland@arm.com" , "robin.murphy@arm.com" , "davem@davemloft.net" , "linux-arm-kernel@lists.infradead.org" , "netdev@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linuxarm@huawei.com" Content-Type: text/plain; charset="UTF-8" List-ID: On Wed, Jul 26, 2017 at 6:08 PM, Ding Tianhong wrote: > > > On 2017/7/27 2:26, Casey Leedom wrote: >> By the way Ding, two issues: >> >> 1. Did we ever get any acknowledgement from either Intel or AMD >> on this patch? I know that we can't ensure that, but it sure would >> be nice since the PCI Quirks that we're putting in affect their >> products. >> > > Still no Intel and AMD guys has ack this, this is what I am worried about, should I > ping some man again ? > > Thanks > Ding I probably wouldn't worry about it too much. If anything all this patch is doing is disabling relaxed ordering on the platforms we know have issues based on what Casey originally had. If nothing else we can follow up once the patches are in the kernel and if somebody has an issue then. You can include my acked-by, but it is mostly related to how this interacts with NICs, and not so much about the PCI chipsets themselves. Acked-by: Alexander Duyck From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexander.duyck@gmail.com (Alexander Duyck) Date: Thu, 27 Jul 2017 10:49:25 -0700 Subject: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported In-Reply-To: <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> References: <1499955692-26556-1-git-send-email-dingtianhong@huawei.com> <1499955692-26556-3-git-send-email-dingtianhong@huawei.com> <0260e398-bd8e-6615-6d5c-1f7c07b6fc09@huawei.com> <67be791f-e0cf-8284-9229-17174dc741ef@codeaurora.org> <5f9b8bfb-41a8-a17c-6fea-581aec1d5573@huawei.com> <20170724090516.2e0f0d2a@w520.home> <75213fca-4522-2297-3cb8-338e643d3552@huawei.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Jul 26, 2017 at 6:08 PM, Ding Tianhong wrote: > > > On 2017/7/27 2:26, Casey Leedom wrote: >> By the way Ding, two issues: >> >> 1. Did we ever get any acknowledgement from either Intel or AMD >> on this patch? I know that we can't ensure that, but it sure would >> be nice since the PCI Quirks that we're putting in affect their >> products. >> > > Still no Intel and AMD guys has ack this, this is what I am worried about, should I > ping some man again ? > > Thanks > Ding I probably wouldn't worry about it too much. If anything all this patch is doing is disabling relaxed ordering on the platforms we know have issues based on what Casey originally had. If nothing else we can follow up once the patches are in the kernel and if somebody has an issue then. You can include my acked-by, but it is mostly related to how this interacts with NICs, and not so much about the PCI chipsets themselves. Acked-by: Alexander Duyck