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Wed, 14 Apr 2021 20:57:32 -0700 (PDT) MIME-Version: 1.0 References: <161832726983.9430.3755052950345832110.malonedeb@chaenomeles.canonical.com> In-Reply-To: <161832726983.9430.3755052950345832110.malonedeb@chaenomeles.canonical.com> From: Alistair Francis Date: Thu, 15 Apr 2021 13:57:06 +1000 Message-ID: Subject: Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating To: Bug 1923629 <1923629@bugs.launchpad.net>, liuzhiwei , Kito Cheng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::133; envelope-from=alistair23@gmail.com; helo=mail-il1-x133.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" + LIU Zhiwei and Kito Cheng Alistair On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923629@bugs.launchpad.net> wrot= e: > > Public bug reported: > > I noticed doing a negate ( 0 =E2=80=93 0x80000000 ) using vssub.vv produc= es an > incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF). > > Here is the bit of the code: > > vmv.v.i v16, 0 > =E2=80=A6 > 8f040457 vssub.vv v8,v16,v8 > > I believe the instruction encoding is correct (vssub.vv with vd =3D v8, > vs2 =3D v16, rs1 =3D v8), but the result does not saturate in QEMU. > > I=E2=80=99ve just tested with what I think is the latest branch ( > https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb > 2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still > exists. > > ** Affects: qemu > Importance: Undecided > Status: New > > > ** Tags: riscv vector > > -- > You received this bug notification because you are a member of qemu- > devel-ml, which is subscribed to QEMU. > https://bugs.launchpad.net/bugs/1923629 > > Title: > RISC-V Vector Instruction vssub.vv not saturating > > Status in QEMU: > New > > Bug description: > I noticed doing a negate ( 0 =E2=80=93 0x80000000 ) using vssub.vv prod= uces an > incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF). > > Here is the bit of the code: > > vmv.v.i v16, 0 > =E2=80=A6 > 8f040457 vssub.vv v8,v16,v8 > > I believe the instruction encoding is correct (vssub.vv with vd =3D v8, > vs2 =3D v16, rs1 =3D v8), but the result does not saturate in QEMU. > > I=E2=80=99ve just tested with what I think is the latest branch ( > https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb > 2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still > exists. > > To manage notifications about this bug go to: > https://bugs.launchpad.net/qemu/+bug/1923629/+subscriptions >