From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6D0FC433FE for ; Tue, 8 Dec 2020 22:23:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B8A423AC8 for ; Tue, 8 Dec 2020 22:23:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730608AbgLHWXC (ORCPT ); Tue, 8 Dec 2020 17:23:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730393AbgLHWXC (ORCPT ); Tue, 8 Dec 2020 17:23:02 -0500 Received: from mail-il1-x143.google.com (mail-il1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEA1BC0613CF for ; Tue, 8 Dec 2020 14:22:21 -0800 (PST) Received: by mail-il1-x143.google.com with SMTP id c18so9592151iln.10 for ; Tue, 08 Dec 2020 14:22:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sZi46PwDTCiNBxYN28eeYZtMufiT2lSdKRPtnPp2uBA=; b=NgF2ekg1k+9cO6s6Cj4qgZNZwesh5RVJ+yitVQ53jq9S4JnMEY1fAvKafFG6f2OP63 zken1A5kvTmK+Ez35UygQMQPvHbemFUpT0ogHeO6SrlEx0oveiKGAuYzY5ief4uI0DYr l0b729ZZqdOLrpC5gNI8L9fNUIg2kRM64RAn5lVuoKy8b7qQk0bQZncY/OBhrgY+vugd GWW7TGAeH7rOxn7AnXSO+3pJhxvgGpdykrXBCI/+1xRQ1o5DF+2mlN8N30S1lPxedGJ9 JG2Ct20Jr7ZdERUodYOTo8239xhBa1+Qpi7Xe9dngL2NSXPkZp45OdAj/cdyP6dnA3gO BBDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=sZi46PwDTCiNBxYN28eeYZtMufiT2lSdKRPtnPp2uBA=; b=QRUrSUVc4h3E2LXM9Ute8hDp+eADFBkDHYLivGzXc8twaSDS75OjDza7RlvOtOj9GE MhhSpzXzXc5aMwedRjzqJywabOnj+27uXRYm+DyfLOdPix9u4vJMYY0xPUNGqddmh5fE IP6hXsF8fMVU0bu3gHLHz/zOEePHrfdW4UGfqy9m04zDQE0X0kFlDwGF1Y2tetCq7mq+ idSrmtwNDMR4ZhJLPAAuOAs7L2+DIV3YfcDECDj0x4bQKMCzqQiacabkKHQWIHL5dvTo j+BgghLS6FYPPFJE6JUIsUk+eNk4HRo5OPsprU61m/8dvbwMtwJe4JaesxPBwPtOI9Tc or+g== X-Gm-Message-State: AOAM531/ZEA5Z2Zuc6xzarnP0ceYfQJ4mX7mTTMbC1y7zeV0WSzs/H3M YTU7ET6c8+CpxPxSth5VnyVxWPo1MzkVit4cRLU= X-Google-Smtp-Source: ABdhPJzhK+ClKrZDoSlIkxZpVfST+Oc77Aa3SIyIhTTwL7rDp0p10RRz2lBvAiWVB5rWGydt52vrwgvJbbDyIX/y0cA= X-Received: by 2002:a92:490d:: with SMTP id w13mr12021ila.227.1607466141348; Tue, 08 Dec 2020 14:22:21 -0800 (PST) MIME-Version: 1.0 References: <20201203124703.168-1-jiangyifei@huawei.com> <20201203124703.168-10-jiangyifei@huawei.com> In-Reply-To: <20201203124703.168-10-jiangyifei@huawei.com> From: Alistair Francis Date: Tue, 8 Dec 2020 14:21:55 -0800 Message-ID: Subject: Re: [PATCH RFC v4 09/15] target/riscv: Add host cpu type To: Yifei Jiang Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , "Zhangxiaofeng (F)" , Sagar Karandikar , "open list:Overall" , libvir-list@redhat.com, Bastian Koppelmann , Anup Patel , yinyipeng , Alistair Francis , kvm-riscv@lists.infradead.org, Palmer Dabbelt , "dengkai (A)" , "Wubin (H)" , Zhanghailiang Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote: > > Currently, host cpu is inherited simply. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/cpu.c | 6 ++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index faee98a58c..439dc89ee7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -186,6 +186,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > #endif > > +static void riscv_host_cpu_init(Object *obj) > +{ > +} > + > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > { > ObjectClass *oc; > @@ -641,10 +645,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), Shouldn't this only be included if KVM is configured? Also it should be shared between RV32 and RV64. Alistair > #endif > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ad1c90f798..4288898019 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -43,6 +43,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) > -- > 2.19.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B545C4361B for ; Tue, 8 Dec 2020 22:52:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB1B823A79 for ; Tue, 8 Dec 2020 22:52:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB1B823A79 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kmlqF-0003GL-WD for qemu-devel@archiver.kernel.org; Tue, 08 Dec 2020 17:52:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kmlNK-0006h0-36; Tue, 08 Dec 2020 17:22:27 -0500 Received: from mail-il1-x141.google.com ([2607:f8b0:4864:20::141]:36915) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kmlNG-0000pD-Sg; Tue, 08 Dec 2020 17:22:24 -0500 Received: by mail-il1-x141.google.com with SMTP id k8so16953614ilr.4; Tue, 08 Dec 2020 14:22:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sZi46PwDTCiNBxYN28eeYZtMufiT2lSdKRPtnPp2uBA=; b=NgF2ekg1k+9cO6s6Cj4qgZNZwesh5RVJ+yitVQ53jq9S4JnMEY1fAvKafFG6f2OP63 zken1A5kvTmK+Ez35UygQMQPvHbemFUpT0ogHeO6SrlEx0oveiKGAuYzY5ief4uI0DYr l0b729ZZqdOLrpC5gNI8L9fNUIg2kRM64RAn5lVuoKy8b7qQk0bQZncY/OBhrgY+vugd GWW7TGAeH7rOxn7AnXSO+3pJhxvgGpdykrXBCI/+1xRQ1o5DF+2mlN8N30S1lPxedGJ9 JG2Ct20Jr7ZdERUodYOTo8239xhBa1+Qpi7Xe9dngL2NSXPkZp45OdAj/cdyP6dnA3gO BBDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=sZi46PwDTCiNBxYN28eeYZtMufiT2lSdKRPtnPp2uBA=; b=DKPyxLsYDq6IPilSfe3+SrZvFqj4Hp+c1SIcp3tmkWjgoP6HIUMgt7fT0OcYQjB4iS Q0vYSMtB04dlhBZ5Ut0NmLvCDb7wJtnBjANY2tReOBJ8BqSlUatg7WieylcAJEMYvDki fOUQMBYxWXzTv5RkiIK2FY7Tab1sEGSSe8TPcYfbK3qLvW/mMvlV5cyhc0PA5KrXBQP/ Z9hfDdzgaKshGTRVryeLAZ8TIxJIZ86CycieFnOdeQjyZdmVqHjyP/1Z2JvehRlzo5jq KGUEKolZezsJ2g1TgbKjduLwGJYpv21EO3+f+gEjiYKci+xst0aixlwurZ0ITFt4M5XO Q+hA== X-Gm-Message-State: AOAM532rFRoLEKBIvMiY5/iUOrb5sY7rD7oM9z6U46wu1vGGv+UjnkD/ TBYLZb0/Nix3+d0ZL2o4gPaUW5AepY8xt57fNxs= X-Google-Smtp-Source: ABdhPJzhK+ClKrZDoSlIkxZpVfST+Oc77Aa3SIyIhTTwL7rDp0p10RRz2lBvAiWVB5rWGydt52vrwgvJbbDyIX/y0cA= X-Received: by 2002:a92:490d:: with SMTP id w13mr12021ila.227.1607466141348; Tue, 08 Dec 2020 14:22:21 -0800 (PST) MIME-Version: 1.0 References: <20201203124703.168-1-jiangyifei@huawei.com> <20201203124703.168-10-jiangyifei@huawei.com> In-Reply-To: <20201203124703.168-10-jiangyifei@huawei.com> From: Alistair Francis Date: Tue, 8 Dec 2020 14:21:55 -0800 Message-ID: Subject: Re: [PATCH RFC v4 09/15] target/riscv: Add host cpu type To: Yifei Jiang Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::141; envelope-from=alistair23@gmail.com; helo=mail-il1-x141.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm-riscv@lists.infradead.org, Anup Patel , "open list:RISC-V" , "open list:Overall" , Sagar Karandikar , libvir-list@redhat.com, Bastian Koppelmann , "Zhangxiaofeng \(F\)" , "qemu-devel@nongnu.org Developers" , Zhanghailiang , Alistair Francis , yinyipeng , Palmer Dabbelt , "Wubin \(H\)" , "dengkai \(A\)" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Dec 3, 2020 at 4:55 AM Yifei Jiang wrote: > > Currently, host cpu is inherited simply. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/cpu.c | 6 ++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index faee98a58c..439dc89ee7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -186,6 +186,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > #endif > > +static void riscv_host_cpu_init(Object *obj) > +{ > +} > + > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > { > ObjectClass *oc; > @@ -641,10 +645,12 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), Shouldn't this only be included if KVM is configured? Also it should be shared between RV32 and RV64. Alistair > #endif > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ad1c90f798..4288898019 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -43,6 +43,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) > -- > 2.19.1 > >