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Tue, 11 May 2021 23:00:04 -0700 (PDT) MIME-Version: 1.0 References: <20210428041848.12982-1-space.monkey.delivers@gmail.com> <20210428041848.12982-6-space.monkey.delivers@gmail.com> In-Reply-To: <20210428041848.12982-6-space.monkey.delivers@gmail.com> From: Alistair Francis Date: Wed, 12 May 2021 15:59:37 +1000 Message-ID: Subject: Re: [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension To: Alexey Baturo Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Richard Henderson , "qemu-devel@nongnu.org Developers" , space.monkey.delivers@gmail.com, Alistair Francis , Dave Smith , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Apr 28, 2021 at 2:23 PM Alexey Baturo wrote: > > From: Anatoly Parshintsev > > Signed-off-by: Anatoly Parshintsev > Reviewed-by: Richard Henderson > --- > target/riscv/cpu.h | 20 ++++++++++++++++++++ > target/riscv/translate.c | 36 ++++++++++++++++++++++++++++++++++-- > 2 files changed, 54 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 19aa3b4769..2edfc59712 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -407,6 +407,8 @@ FIELD(TB_FLAGS, SEW, 5, 3) > FIELD(TB_FLAGS, VILL, 8, 1) > /* Is a Hypervisor instruction load/store allowed? */ > FIELD(TB_FLAGS, HLSX, 9, 1) > +/* If PointerMasking should be applied */ > +FIELD(TB_FLAGS, PM_ENABLED, 10, 1) > > bool riscv_cpu_is_32bit(CPURISCVState *env); > > @@ -464,6 +466,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); > } > } > + if (riscv_has_ext(env, RVJ)) { > + int priv = cpu_mmu_index(env, false); You will want to and this with TB_FLAGS_PRIV_MMU_MASK Otherwise: Reviewed-by: Alistair Francis Alistair > + bool pm_enabled = false; > + switch (priv) { > + case PRV_U: > + pm_enabled = env->mmte & U_PM_ENABLE; > + break; > + case PRV_S: > + pm_enabled = env->mmte & S_PM_ENABLE; > + break; > + case PRV_M: > + pm_enabled = env->mmte & M_PM_ENABLE; > + break; > + default: > + g_assert_not_reached(); > + } > + flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled); > + } > #endif > > *pflags = flags; > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 2e815a5912..37706d56d5 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; > static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ > static TCGv load_res; > static TCGv load_val; > +/* globals for PM CSRs */ > +static TCGv pm_mask[4]; > +static TCGv pm_base[4]; > > #include "exec/gen-icount.h" > > @@ -64,6 +67,10 @@ typedef struct DisasContext { > uint16_t vlen; > uint16_t mlen; > bool vl_eq_vlmax; > + /* PointerMasking extension */ > + bool pm_enabled; > + TCGv pm_mask; > + TCGv pm_base; > CPUState *cs; > } DisasContext; > > @@ -90,13 +97,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) > } > > /* > - * Temp stub: generates address adjustment for PointerMasking > + * Generates address adjustment for PointerMasking > */ > static void gen_pm_adjust_address(DisasContext *s, > TCGv_i64 dst, > TCGv_i64 src) > { > - tcg_gen_mov_i64(dst, src); > + if (!s->pm_enabled) { > + /* Load unmodified address */ > + tcg_gen_mov_i64(dst, src); > + } else { > + tcg_gen_andc_i64(dst, src, s->pm_mask); > + tcg_gen_or_i64(dst, dst, s->pm_base); > + } > } > > /* > @@ -657,6 +670,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); > ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); > ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); > + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); > + int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK; > + ctx->pm_mask = pm_mask[priv]; > + ctx->pm_base = pm_base[priv]; > ctx->cs = cs; > } > > @@ -777,4 +794,19 @@ void riscv_translate_init(void) > "load_res"); > load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), > "load_val"); > +#ifndef CONFIG_USER_ONLY > + /* Assign PM CSRs to tcg globals */ > + pm_mask[PRV_U] = > + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); > + pm_base[PRV_U] = > + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); > + pm_mask[PRV_S] = > + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); > + pm_base[PRV_S] = > + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); > + pm_mask[PRV_M] = > + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); > + pm_base[PRV_M] = > + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); > +#endif > } > -- > 2.20.1 > >