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Thu, 17 Jun 2021 18:33:05 -0700 (PDT) MIME-Version: 1.0 References: <20210617165647.2575955-1-erdnaxe@crans.org> <20210617165647.2575955-5-erdnaxe@crans.org> In-Reply-To: <20210617165647.2575955-5-erdnaxe@crans.org> From: Alistair Francis Date: Fri, 18 Jun 2021 11:32:38 +1000 Message-ID: Subject: Re: [PATCH v3 4/4] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase To: Alexandre Iooss Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d36; envelope-from=alistair23@gmail.com; helo=mail-io1-xd36.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list : STM32VLDISCOVERY" , "open list : All patches CC here" , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss wrote: > > New mini-kernel test for STM32VLDISCOVERY USART1. > > Signed-off-by: Alexandre Iooss Acked-by: Alistair Francis Alistair > --- > tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c > index d40adddafa..96849cec91 100644 > --- a/tests/qtest/boot-serial-test.c > +++ b/tests/qtest/boot-serial-test.c > @@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] = { > 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */ > }; > > +static const uint8_t kernel_stm32vldiscovery[] = { > + 0x00, 0x00, 0x00, 0x00, /* Stack top address */ > + 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */ > + 0x00, 0x00, 0x00, 0x00, /* NMI */ > + 0x00, 0x00, 0x00, 0x00, /* Hard fault */ > + 0x00, 0x00, 0x00, 0x00, /* Memory management fault */ > + 0x00, 0x00, 0x00, 0x00, /* Bus fault */ > + 0x00, 0x00, 0x00, 0x00, /* Usage fault */ > + 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */ > + 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */ > + 0x1a, 0x68, /* ldr r2, [r3] */ > + 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x1a, 0x68, /* ldr r2, [r3] */ > + 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */ > + 0x45, 0x22, /* movs r2, #69 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */ > + 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */ > + 0x54, 0x22, /* movs r2, 'T' */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0xfe, 0xe7, /* b . */ > + 0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */ > + 0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */ > + 0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */ > + 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */ > + 0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */ > +}; > + > typedef struct testdef { > const char *arch; /* Target architecture */ > const char *machine; /* Name of the machine */ > @@ -144,6 +179,8 @@ static testdef_t tests[] = { > { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64), > kernel_aarch64 }, > { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, > + { "arm", "stm32vldiscovery", "", "T", > + sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery }, > > { NULL } > }; > -- > 2.25.1 >