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MORIN" Subject: Re: [Buildroot] [PATCH 1/1] package/guile: fix build on riscv32 X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabrice Fontaine , buildroot Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" On Sat, Aug 7, 2021 at 6:53 PM Yann E. MORIN wrote: > > Fabrice, All, > > On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly: > > Fix the following build failure on riscv32: > > > > system/base/target.scm:132:16: In procedure triplet-pointer-size: > > unknown CPU word size "riscv32" > > > > Fixes: > > - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8 > > > > Signed-off-by: Fabrice Fontaine > > --- > > ...stem-base-target.scm-support-riscv32.patch | 33 +++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > create mode 100644 package/guile/0004-module-system-base-target.scm-support-riscv32.patch > > > > diff --git a/package/guile/0004-module-system-base-target.scm-support-riscv32.patch b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch > > new file mode 100644 > > index 0000000000..cadd040f12 > > --- /dev/null > > +++ b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch > > @@ -0,0 +1,33 @@ > > +From 995a5e1da735b75733f059615c593c330b534d80 Mon Sep 17 00:00:00 2001 > > +From: Fabrice Fontaine > > +Date: Fri, 6 Aug 2021 19:49:37 +0200 > > +Subject: [PATCH] module/system/base/target.scm: support riscv32 > > + > > +Fix the following build failure on riscv32: > > + > > +system/base/target.scm:132:16: In procedure triplet-pointer-size: > > +unknown CPU word size "riscv32" > > + > > +Fixes: > > + - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8 > > + > > +Signed-off-by: Fabrice Fontaine > > +--- > > + module/system/base/target.scm | 1 + > > + 1 file changed, 1 insertion(+) > > + > > +diff --git a/module/system/base/target.scm b/module/system/base/target.scm > > +index 2088cd866..5544e234f 100644 > > +--- a/module/system/base/target.scm > > ++++ b/module/system/base/target.scm > > +@@ -121,6 +121,7 @@ > > + ((member cpu '("sparc" "powerpc" "mips" "mipsel" "nios2" "m68k" "sh3" "sh4")) 4) > > + ((member cpu '("s390x" "alpha")) 8) > > + ((string-match "^arm.*" cpu) 4) > > ++ ((string-match "^riscv.*" cpu) 8) > > Are you sure that a 32-bit CPU will have 8-byte wide words? I would > have naturrally expected them to be just 4-byte wide... > > If htis is indeed the case, then please explain that in the patch commit > log... It should be 4-byte words for riscv32. Basically the same as 32-bit arm except when it comes to time_t types (which are always 64-bits). Alistair _______________________________________________ buildroot mailing list buildroot@busybox.net http://lists.busybox.net/mailman/listinfo/buildroot