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Mon, 08 Mar 2021 05:38:03 -0800 (PST) MIME-Version: 1.0 References: <20210305135451.15427-1-alex.bennee@linaro.org> <20210305135451.15427-4-alex.bennee@linaro.org> <87im65gxla.fsf@keithp.com> <877dmlgnrf.fsf@keithp.com> <87o8fwfcjd.fsf@keithp.com> In-Reply-To: From: Alistair Francis Date: Mon, 8 Mar 2021 08:36:44 -0500 Message-ID: Subject: Re: [PATCH v1 3/3] semihosting/arg-compat: fix up handling of SYS_HEAPINFO To: Peter Maydell Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=alistair23@gmail.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bug 1915925 <1915925@bugs.launchpad.net>, Keith Packard , "open list:ARM TCG CPUs" , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Mar 8, 2021 at 5:10 AM Peter Maydell wrote: > > On Sat, 6 Mar 2021 at 16:54, Keith Packard wrote: > > > > Peter Maydell writes: > > > Part of why I asked is that the current RISCV implementation > > > is just looking at sizeof(target_ulong); but the qemu-system-riscv64 > > > executable AIUI now supports emulating both "this is a 64 bit > > > guest CPU" and "this is a 32 bit host CPU", and so looking at > > > a QEMU-compile-time value like "sizeof(target_ulong)" will > > > produce the wrong answer for 32-bit CPUs emulated in > > > the qemu-system-riscv64 binary. My guess is maybe > > > it should be looking at the result of riscv_cpu_is_32bit() instead. > > > > Wow. I read through the code and couldn't find anything that looked like > > it supported that, sounds like I must have missed something? riscv_cpu_is_32bit() is somewhat new, so it might not have been there when you wrote the patches. > > I thought Alistair had done that work (which brings riscv into > line with the other 32/64 bit QEMU targets, which all support > the 32-bit CPU types in the 64-bit-capable executable). But maybe > it hasn't landed in master yet? I have started on the effort, but I have not finished yet. Adding riscv_cpu_is_32bit() was the first step there and I have some more patches locally but I don't have anything working yet. Alistair > > thanks > -- PMM