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* Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
@ 2021-04-19 21:26 ` Alexander Wagner
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Wagner @ 2021-04-19 21:26 UTC (permalink / raw)
  To: qemu-devel@nongnu.org Developers
  Cc: Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, qemu-riscv,
	Sagar Karandikar

Hi,

I just wanted to check if the patch [1] is missing anything to be 
merged? If so, please let me know.

Regards

Alex


[1] 
https://patchew.org/QEMU/20210310221208.167990-1-alexander.wagner@ulal.de/




^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
@ 2021-04-19 21:26 ` Alexander Wagner
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Wagner @ 2021-04-19 21:26 UTC (permalink / raw)
  To: qemu-devel@nongnu.org Developers
  Cc: Bastian Koppelmann, Palmer Dabbelt, Alistair Francis,
	Sagar Karandikar, qemu-riscv

Hi,

I just wanted to check if the patch [1] is missing anything to be 
merged? If so, please let me know.

Regards

Alex


[1] 
https://patchew.org/QEMU/20210310221208.167990-1-alexander.wagner@ulal.de/




^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
  2021-04-19 21:26 ` Alexander Wagner
@ 2021-04-19 21:36   ` Alistair Francis
  -1 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2021-04-19 21:36 UTC (permalink / raw)
  To: Alexander Wagner
  Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
	qemu-devel@nongnu.org Developers, Palmer Dabbelt,
	Alistair Francis

On Tue, Apr 20, 2021 at 7:26 AM Alexander Wagner
<alexander.wagner@ulal.de> wrote:
>
> Hi,
>
> I just wanted to check if the patch [1] is missing anything to be
> merged? If so, please let me know.

Thanks for the ping!

You have done everything correctly, I just forgot to apply the patch.

Do you mind re-sending the patch though? When re-sending the patch can
you include all of the reviewed by tags?

Alistair

>
> Regards
>
> Alex
>
>
> [1]
> https://patchew.org/QEMU/20210310221208.167990-1-alexander.wagner@ulal.de/
>
>
>


^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
@ 2021-04-19 21:36   ` Alistair Francis
  0 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2021-04-19 21:36 UTC (permalink / raw)
  To: Alexander Wagner
  Cc: qemu-devel@nongnu.org Developers, Bastian Koppelmann,
	Alistair Francis, Palmer Dabbelt, open list:RISC-V,
	Sagar Karandikar

On Tue, Apr 20, 2021 at 7:26 AM Alexander Wagner
<alexander.wagner@ulal.de> wrote:
>
> Hi,
>
> I just wanted to check if the patch [1] is missing anything to be
> merged? If so, please let me know.

Thanks for the ping!

You have done everything correctly, I just forgot to apply the patch.

Do you mind re-sending the patch though? When re-sending the patch can
you include all of the reviewed by tags?

Alistair

>
> Regards
>
> Alex
>
>
> [1]
> https://patchew.org/QEMU/20210310221208.167990-1-alexander.wagner@ulal.de/
>
>
>


^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
  2021-03-10 22:12 ` Alexander Wagner
@ 2021-03-11 21:41   ` Alistair Francis
  -1 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2021-03-11 21:41 UTC (permalink / raw)
  To: Alexander Wagner
  Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
	qemu-devel@nongnu.org Developers, Alistair Francis,
	Palmer Dabbelt

On Wed, Mar 10, 2021 at 5:23 PM Alexander Wagner
<alexander.wagner@ulal.de> wrote:
>
> The IBEX documentation [1] specifies the reset vector to be "the most
> significant 3 bytes of the boot address and the reset value (0x80) as
> the least significant byte".
>
> [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
>
> Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/opentitan.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index e168bffe69..ca4c1be6f6 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
> -    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
> +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
>      sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
>
>      /* Boot ROM */
> --
> 2.25.1
>
>


^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv: Fix OT IBEX reset vector
@ 2021-03-11 21:41   ` Alistair Francis
  0 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2021-03-11 21:41 UTC (permalink / raw)
  To: Alexander Wagner
  Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
	Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt,
	Alistair Francis

On Wed, Mar 10, 2021 at 5:23 PM Alexander Wagner
<alexander.wagner@ulal.de> wrote:
>
> The IBEX documentation [1] specifies the reset vector to be "the most
> significant 3 bytes of the boot address and the reset value (0x80) as
> the least significant byte".
>
> [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
>
> Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/opentitan.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index e168bffe69..ca4c1be6f6 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
> -    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
> +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
>      sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
>
>      /* Boot ROM */
> --
> 2.25.1
>
>


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] hw/riscv: Fix OT IBEX reset vector
@ 2021-03-10 22:12 ` Alexander Wagner
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Wagner @ 2021-03-10 22:12 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, sagark, kbastian, palmer, Alistair.Francis, Alexander Wagner

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index e168bffe69..ca4c1be6f6 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 
     /* Boot ROM */
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] hw/riscv: Fix OT IBEX reset vector
@ 2021-03-10 22:12 ` Alexander Wagner
  0 siblings, 0 replies; 8+ messages in thread
From: Alexander Wagner @ 2021-03-10 22:12 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alexander Wagner, Alistair.Francis, qemu-riscv, palmer, sagark, kbastian

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index e168bffe69..ca4c1be6f6 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -120,7 +120,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 
     /* Boot ROM */
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-04-19 21:38 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-19 21:26 [PATCH] hw/riscv: Fix OT IBEX reset vector Alexander Wagner
2021-04-19 21:26 ` Alexander Wagner
2021-04-19 21:36 ` Alistair Francis
2021-04-19 21:36   ` Alistair Francis
  -- strict thread matches above, loose matches on Subject: below --
2021-03-10 22:12 Alexander Wagner
2021-03-10 22:12 ` Alexander Wagner
2021-03-11 21:41 ` Alistair Francis
2021-03-11 21:41   ` Alistair Francis

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