From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9AD9CC433EF for ; Thu, 2 Jun 2022 00:42:33 +0000 (UTC) Received: from localhost ([::1]:53264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwYv1-0006xN-P9 for qemu-devel@archiver.kernel.org; Wed, 01 Jun 2022 20:42:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwYpH-0003vZ-0h; Wed, 01 Jun 2022 20:36:35 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]:39921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwYpF-00047y-J0; Wed, 01 Jun 2022 20:36:34 -0400 Received: by mail-oi1-x22b.google.com with SMTP id y131so4759328oia.6; Wed, 01 Jun 2022 17:36:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XdrfdHxaWmx9gsIN6gbPRflPZPVQ08Xrb0jXEispltE=; b=AE+nOJlblaJS8PgPgYZlqDaDVpdncUptCJEXs5IPqGzVkOdN0BbDvv+8HBIwUOE1O3 X/Ma6i64ZOJBHom0r+jZIEQn1s6WeXc70odQFp9JHXT4+2ObBTc6lo457u4/xO8YiziE cjvvZPJkHrU5Unb7LDcayAvAw9XhAWJk0GWlh1cTCiJmlZkLSGH2+faP6DXQugiDgvVO 2mg7kfC+ejn804tBUKHI1TgL7iDQ15S/5lTuq3x2DjtYkJA9WcHqq0wgCBsiVuQ73CfA iTAQ863J4yie9h0Io+69YKx867/TFPpnIQIKqML5e7RqvUhe6uA0zb6xQdi/eaMBUDEH J8nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=XdrfdHxaWmx9gsIN6gbPRflPZPVQ08Xrb0jXEispltE=; b=S5wZHBbnT/76s5xDUdaxBttTsFHfLIS+dG8c8ApmyktoTUCI7xz5M223rznpLYYUDA KJD1fYHch1RezcqbWKC+Bq7jy0DbJJgWLmlP3PYN151wOfUVbo3t/vLuaIgJlfucXzlN RpsnqcxIJjdyp8u0V9yyI7aIwYcK6IubYapyGIL7xzPMls/iFRPVW4+l6D6PQr2Kx0qL k31393/XEuoGRSBYG4EfT8b/pLzV6FDFCPPg1maPdBU0+pyJoxPRzumXBgz6gh5nhZDI CTU99Ue6cPIB/mSxr7ZLJZSOE1MWx1elvXDUMZONA5KLFbTaWnaEiGr+delOFwt1hovY obkg== X-Gm-Message-State: AOAM532e58Uc+Eddnp0EM6MUmjvcnCDsWHMZ5ri5WNGpVGH8SRQCXQvZ EGzNvT42uaASnqzC8TND5eqZ4lZww55VzoPDvNs= X-Google-Smtp-Source: ABdhPJwBX97R7qN6NdItfHswSe9TPIqKKAPJqx9eTibw/Ll6YW2cuL+A6/07OhpOJLDJ624EeHWY7cZrfyWInvvySuY= X-Received: by 2002:a05:6808:19a6:b0:32b:90c4:d1af with SMTP id bj38-20020a05680819a600b0032b90c4d1afmr17086632oib.64.1654130189184; Wed, 01 Jun 2022 17:36:29 -0700 (PDT) MIME-Version: 1.0 References: <20220601172353.3220232-1-fkonrad@xilinx.com> <20220601172353.3220232-4-fkonrad@xilinx.com> In-Reply-To: <20220601172353.3220232-4-fkonrad@xilinx.com> From: Alistair Francis Date: Thu, 2 Jun 2022 10:36:03 +1000 Message-ID: Subject: Re: [PATCH v3 3/4] xlnx_dp: Fix the interrupt disable logic To: frederic.konrad@xilinx.com Cc: "qemu-devel@nongnu.org Developers" , qemu-arm , Peter Maydell , Edgar Iglesias , Alistair Francis , Sai Pavan Boddu , Edgar Iglesias , fkonrad@amd.com, Sai Pavan Boddu , "Edgar E . Iglesias" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 2, 2022 at 3:32 AM wrote: > > From: Sai Pavan Boddu > > Fix interrupt disable logic. Mask value 1 indicates that interrupts are > disabled. > > Signed-off-by: Sai Pavan Boddu > Reviewed-by: Edgar E. Iglesias > Signed-off-by: Frederic Konrad Acked-by: Alistair Francis Alistair > --- > hw/display/xlnx_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c > index d0bea512bd..eed705219e 100644 > --- a/hw/display/xlnx_dp.c > +++ b/hw/display/xlnx_dp.c > @@ -889,7 +889,7 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, > xlnx_dp_update_irq(s); > break; > case DP_INT_DS: > - s->core_registers[DP_INT_MASK] |= ~value; > + s->core_registers[DP_INT_MASK] |= value; > xlnx_dp_update_irq(s); > break; > default: > -- > 2.25.1 > >