Re: [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging

From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Michael Clark <mjc@sifive.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging
Date: Thu, 24 May 2018 15:47:22 -0700	[thread overview]
Message-ID: <CAKmqyKNGpOf1Sxrv9f2e9A_XP=JC0REgpwjzZfnsF7kePey0Gg@mail.gmail.com> (raw)
In-Reply-To: <625fe1a3-fe18-6216-eeb2-393f90817bff@amsat.org>

On Wed, May 23, 2018 at 5:33 AM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Hi Michael,
>
> On 05/22/2018 09:15 PM, Michael Clark wrote:
>> Add carriage return that was erroneously removed
>> when converting to qemu_log. Change hard coded
>> core number to the actual hartid.
>
> I think it makes more sens to move this patch before your 6/30 "Move
> non-ops from op_helper to cpu_helper".
>
>>
>> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
>> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>> Cc: Palmer Dabbelt <palmer@sifive.com>
>> Cc: Alistair Francis <Alistair.Francis@wdc.com>
>> Signed-off-by: Michael Clark <mjc@sifive.com>
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
>> ---
>>  target/riscv/cpu_helper.c | 18 ++++++++++--------
>>  1 file changed, 10 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index bc15e19022cc..69592c037042 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -446,11 +446,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>      if (RISCV_DEBUG_INTERRUPT) {
>>          int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
>>          if (cs->exception_index & RISCV_EXCP_INT_FLAG) {
>> -            qemu_log_mask(LOG_TRACE, "core   0: trap %s, epc 0x" TARGET_FMT_lx,
>> -                riscv_intr_names[log_cause], env->pc);
>> +            qemu_log_mask(LOG_TRACE, "core "
>> +                TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n",
>> +                env->mhartid, riscv_intr_names[log_cause], env->pc);
>>          } else {
>> -            qemu_log_mask(LOG_TRACE, "core   0: intr %s, epc 0x" TARGET_FMT_lx,
>> -                riscv_excp_names[log_cause], env->pc);
>> +            qemu_log_mask(LOG_TRACE, "core "
>> +                TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n",
>> +                env->mhartid, riscv_excp_names[log_cause], env->pc);
>>          }
>>      }
>>
>> @@ -512,8 +514,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>
>>          if (hasbadaddr) {
>>              if (RISCV_DEBUG_INTERRUPT) {
>> -                qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld
>> -                    ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
>> +                qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x"
>> +                    TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
>>              }
>>              env->sbadaddr = env->badaddr;
>>          } else {
>> @@ -537,8 +539,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>
>>          if (hasbadaddr) {
>>              if (RISCV_DEBUG_INTERRUPT) {
>> -                qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld
>> -                    ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
>> +                qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x"
>> +                    TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
>>              }
>>              env->mbadaddr = env->badaddr;
>>          } else {
>>
>