From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:40720) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gm668-0005eU-G4 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 19:08:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gm667-0001CT-J2 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 19:08:52 -0500 MIME-Version: 1.0 References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> <20190122092909.5341-14-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190122092909.5341-14-kbastian@mail.uni-paderborn.de> From: Alistair Francis Date: Tue, 22 Jan 2019 16:08:13 -0800 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann Cc: Sagar Karandikar , Palmer Dabbelt , qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, Richard Henderson , "qemu-devel@nongnu.org Developers" On Tue, Jan 22, 2019 at 1:49 AM Bastian Koppelmann wrote: > > Reviewed-by: Richard Henderson > Signed-off-by: Bastian Koppelmann > Signed-off-by: Peer Adelt Acked-by: Alistair Francis Alistair > --- > target/riscv/insn32-64.decode | 6 +++ > target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode > index 0bee95c984..6319f872ac 100644 > --- a/target/riscv/insn32-64.decode > +++ b/target/riscv/insn32-64.decode > @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st > amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st > amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st > amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st > + > +# *** RV64F Standard Extension (in addition to RV32F) *** > +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm > +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm > +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm > +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c > index b101593ac4..b667c576d4 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) > > return true; > } > + > +#ifdef TARGET_RISCV64 > +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, t0); > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, t0); > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); > + > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); > + > + tcg_temp_free(t0); > + return true; > +} > +#endif > -- > 2.20.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1gm669-0005ef-2L for mharc-qemu-riscv@gnu.org; Tue, 22 Jan 2019 19:08:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40687) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gm666-0005eL-Dg for qemu-riscv@nongnu.org; Tue, 22 Jan 2019 19:08:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gm664-00019I-C6 for qemu-riscv@nongnu.org; Tue, 22 Jan 2019 19:08:49 -0500 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]:38911) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gm664-0000xR-0B; Tue, 22 Jan 2019 19:08:48 -0500 Received: by mail-lj1-x244.google.com with SMTP id c19-v6so320662lja.5; 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Tue, 22 Jan 2019 16:08:40 -0800 (PST) MIME-Version: 1.0 References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> <20190122092909.5341-14-kbastian@mail.uni-paderborn.de> In-Reply-To: <20190122092909.5341-14-kbastian@mail.uni-paderborn.de> From: Alistair Francis Date: Tue, 22 Jan 2019 16:08:13 -0800 Message-ID: To: Bastian Koppelmann Cc: Sagar Karandikar , Palmer Dabbelt , qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, Richard Henderson , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::244 Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Jan 2019 00:08:51 -0000 On Tue, Jan 22, 2019 at 1:49 AM Bastian Koppelmann wrote: > > Reviewed-by: Richard Henderson > Signed-off-by: Bastian Koppelmann > Signed-off-by: Peer Adelt Acked-by: Alistair Francis Alistair > --- > target/riscv/insn32-64.decode | 6 +++ > target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode > index 0bee95c984..6319f872ac 100644 > --- a/target/riscv/insn32-64.decode > +++ b/target/riscv/insn32-64.decode > @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st > amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st > amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st > amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st > + > +# *** RV64F Standard Extension (in addition to RV32F) *** > +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm > +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm > +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm > +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c > index b101593ac4..b667c576d4 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) > > return true; > } > + > +#ifdef TARGET_RISCV64 > +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, t0); > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, t0); > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); > + > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); > + > + tcg_temp_free(t0); > + return true; > +} > +#endif > -- > 2.20.1 > >