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Mon, 30 Jan 2023 05:27:13 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Alistair Francis Date: Mon, 30 Jan 2023 23:26:47 +1000 Message-ID: Subject: Re: [PATCH v2 04/14] xen/riscv: add header To: Oleksii Kurochko Cc: xen-devel@lists.xenproject.org, Jan Beulich , Julien Grall , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Bob Eshleman , Alistair Francis , Connor Davis Content-Type: text/plain; charset="UTF-8" On Sat, Jan 28, 2023 at 12:00 AM Oleksii Kurochko wrote: > > The following changes were made in comparison with from > Linux: > * remove all defines as they are defined in riscv_encoding.h > * leave only csr_* macros > > Origin: https://github.com/torvalds/linux.git 2475bf0250de > Signed-off-by: Oleksii Kurochko Reviewed-by: Alistair Francis Alistair > --- > Changes in V2: > - Minor refactoring mentioned in the commit message, switch tabs to > spaces and refactor things around __asm__ __volatile__. > - Update the commit message and add "Origin:" tag. > --- > xen/arch/riscv/include/asm/csr.h | 84 ++++++++++++++++++++++++++++++++ > 1 file changed, 84 insertions(+) > create mode 100644 xen/arch/riscv/include/asm/csr.h > > diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h > new file mode 100644 > index 0000000000..4275cf6515 > --- /dev/null > +++ b/xen/arch/riscv/include/asm/csr.h > @@ -0,0 +1,84 @@ > +/* > + * SPDX-License-Identifier: GPL-2.0-only > + * > + * Copyright (C) 2015 Regents of the University of California > + */ > + > +#ifndef _ASM_RISCV_CSR_H > +#define _ASM_RISCV_CSR_H > + > +#include > +#include > +#include > + > +#ifndef __ASSEMBLY__ > + > +#define csr_read(csr) \ > +({ \ > + register unsigned long __v; \ > + __asm__ __volatile__ ( "csrr %0, " __ASM_STR(csr) \ > + : "=r" (__v) \ > + : : "memory" ); \ > + __v; \ > +}) > + > +#define csr_write(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrw " __ASM_STR(csr) ", %0" \ > + : /* no outputs */ \ > + : "rK" (__v) \ > + : "memory" ); \ > +}) > + > +#define csr_swap(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrrw %0, " __ASM_STR(csr) ", %1" \ > + : "=r" (__v) \ > + : "rK" (__v) \ > + : "memory" ); \ > + __v; \ > +}) > + > +#define csr_read_set(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrrs %0, " __ASM_STR(csr) ", %1" \ > + : "=r" (__v) \ > + : "rK" (__v) \ > + : "memory" ); \ > + __v; \ > +}) > + > +#define csr_set(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrs " __ASM_STR(csr) ", %0" \ > + : /* no outputs */ \ > + : "rK" (__v) \ > + : "memory" ); \ > +}) > + > +#define csr_read_clear(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrrc %0, " __ASM_STR(csr) ", %1" \ > + : "=r" (__v) \ > + : "rK" (__v) \ > + : "memory" ); \ > + __v; \ > +}) > + > +#define csr_clear(csr, val) \ > +({ \ > + unsigned long __v = (unsigned long)(val); \ > + __asm__ __volatile__ ( "csrc " __ASM_STR(csr) ", %0" \ > + : /*no outputs */ \ > + : "rK" (__v) \ > + : "memory" ); \ > +}) > + > +#endif /* __ASSEMBLY__ */ > + > +#endif /* _ASM_RISCV_CSR_H */ > -- > 2.39.0 > >