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Tue, 15 Jun 2021 03:41:03 -0700 (PDT) MIME-Version: 1.0 References: <20210608161028.4159582-1-erdnaxe@crans.org> <20210608161028.4159582-2-erdnaxe@crans.org> <6bcf8d1b-7caf-ded5-937a-4c1bf96e2d85@crans.org> <7e8a01c5-0130-1003-8396-af8d4b45d2c0@crans.org> In-Reply-To: <7e8a01c5-0130-1003-8396-af8d4b45d2c0@crans.org> From: Alistair Francis Date: Tue, 15 Jun 2021 20:40:37 +1000 Message-ID: Subject: Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC To: Alexandre IOOSS Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d34; envelope-from=alistair23@gmail.com; helo=mail-io1-xd34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:STM32F100" , "open list:All patches CC here" , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Jun 15, 2021 at 7:15 PM Alexandre IOOSS wrote: > > > > On 6/15/21 10:04 AM, Alistair Francis wrote: > > On Tue, Jun 15, 2021 at 5:50 PM Alexandre IOOSS wrote: > >> > >> On 6/15/21 9:41 AM, Alistair Francis wrote: > >>> Aren't you missing some timers, like timer[5] 0x4000_0C00? > >>> > >>> Alistair > >> > >> I double-checked using the reference manual and the datasheet and there > >> is not timer[5]: > >> - page 36 of > >> https://www.st.com/resource/en/reference_manual/cd00246267-stm32f100xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf > > > > Strange, https://www.st.com/resource/en/datasheet/stm32f100rc.pdf > > describes Timer 5 and page 282 of the document you linked talks about > > timer 5 as well. > > > > Alistair > > > >> - page 30 of https://www.st.com/resource/en/datasheet/stm32f100cb.pdf > >> > >> I believe ST is skipping numbers to guarantee that timer[n] will have a > >> consistent address on different STM32 SoC. > >> > >> Thanks, > >> -- Alexandre > >> > > From what I understand from other STM32F100xx reference manuals: > I am implementing all peripherals in the STM32F100xx reference manual > which match with what is actually in the STM32F100RB SoC (used in the > STM32VLDISCOVERY). Ah, my mistake. The STM numbering always confuses me. > > STM32F100RC SoC implements more peripherals (more USART, more > timers...). Adding these peripherals in stm32f100.c means that the > STM32VLDISCOVERY machine would have peripherals that does not exist on > the real target. Do we want to avoid that? Yep, this is fine as is. > > Should we keep stm32f100.c with the common subset of peripherals and > extend it when a machine is using a variant with more peripherals? > > I believe this issue is also linked with what Philippe proposed: we > could abstract STM32 SoC in the same way ATMEGA is abstracted. This > would make a lot of sense since the STM32 family has a lot of > similarities and we don't want to bloat QEMU with N times the same code. I agree. That's the best way forward and I think it's a good goal. We don't have to block this series on that though. If you would like to work on a shared abstraction that would be great :) Once the IRQs are fixed: Reviewed-by: Alistair Francis Alistair > > Thanks, > -- Alexandre >