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X-Received-From: 2a00:1450:4864:20::142 Subject: Re: [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, May 30, 2019 at 6:52 AM Hesham Almatary wrote: > > The PMP should be checked when doing a page table walk, and report access > fault exception if the to-be-read PTE failed the PMP check. > > Suggested-by: Jonathan Behrens > Signed-off-by: Hesham Almatary > --- > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 10 +++++++++- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c17184f4e4..ab3ba3f15a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -94,6 +94,7 @@ enum { > #define PRIV_VERSION_1_09_1 0x00010901 > #define PRIV_VERSION_1_10_0 0x00011000 > > +#define TRANSLATE_PMP_FAIL 2 > #define TRANSLATE_FAIL 1 > #define TRANSLATE_SUCCESS 0 > #define NB_MMU_MODES 4 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 5a1cd7cf96..00bc4f1712 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -211,6 +211,12 @@ restart: > > /* check that physical address of PTE is legal */ > target_ulong pte_addr = base + idx * ptesize; > + > + if (riscv_feature(env, RISCV_FEATURE_PMP) && > + !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), > + 1 << MMU_DATA_LOAD, PRV_S)) { Shouldn't we be passing mode in here? Alistair > + return TRANSLATE_PMP_FAIL; > + } > #if defined(TARGET_RISCV32) > target_ulong pte = ldl_phys(cs->as, pte_addr); > #elif defined(TARGET_RISCV64) > @@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > (ret == TRANSLATE_SUCCESS) && > !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, > mode)) { > + ret = TRANSLATE_PMP_FAIL; > + } > + if (ret == TRANSLATE_PMP_FAIL) { > pmp_violation = true; > - ret = TRANSLATE_FAIL; > } > if (ret == TRANSLATE_SUCCESS) { > tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, > -- > 2.17.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1hYd8K-00067O-M8 for mharc-qemu-riscv@gnu.org; Wed, 05 Jun 2019 17:07:44 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51075) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYd8I-00065Y-TA for qemu-riscv@nongnu.org; Wed, 05 Jun 2019 17:07:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYd8H-0007RK-1T for qemu-riscv@nongnu.org; Wed, 05 Jun 2019 17:07:42 -0400 Received: from mail-lf1-x142.google.com ([2a00:1450:4864:20::142]:34192) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYd8F-0006hd-3d; Wed, 05 Jun 2019 17:07:39 -0400 Received: by mail-lf1-x142.google.com with SMTP id y198so9674907lfa.1; Wed, 05 Jun 2019 14:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Ir0aWXK1HA8gcf6jmWHtEGBp8js2Rqbgng0/bt00rrs=; b=SH14dOYnPi0pfbMUatsB0A5d8hVtipS6wJ3jVI0m59/9vCU6jmMe+O0Sg7jEpNWzai 2r6/2qPhz42PRcZNaf1VtD+kHyWRAznX3nlLkRYmFIGDVwR2v/viVQAOhiReWUDAEgaV ZXrqFladVAhDjY/hfXG3mJ0EUoNx9Wa5QEYlP0tA/2tMJeFRHk+kAp2hfLgby41C1eYG B8/AJIP+qY6YhpnKbm0TK6Y3AHOD4voz2tTLfIQJuwBwnIqhemrX8IwOh/0WYkBKb9nW VczZKiFfxPZ0ldgqmNMFz2PuEjIPwzh5gImZmz+awDNWEaTyI1z7kBbm0wlTrmKL6BCD O7AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ir0aWXK1HA8gcf6jmWHtEGBp8js2Rqbgng0/bt00rrs=; b=cif6IOtwJxo6r1uAoTZoIRmKtts0q/8wPgRlbYKU6abrnzV2EChqEfAo3WTk3u4KGq ldmA2lh/nCyOA/mbKmZPfG/adxoxG2c7fQzkLeq1Z2Esi55hIZd4jzdBHw1jVsrDibPw kb94Blh79iF68k9ScYRCGD7bB+3XREYHb7c0wL0roJjqIg746Wl91tQXJKpPrWjciK0e 8+1XnE/ZUx7Eu0ERZVeBFLBN631pw/MIogE5IA1KkQx4V+GxR+VfcfaPkRPIwZ94wc9/ AIXhuWGM6zl2y7rAScUhyvDH3uLh2IdkYqZL6SLoKkYAG2IocQ/ynHxXzk+l8d4afvFb Z+Ng== X-Gm-Message-State: APjAAAVP2blNMZR7K6zXx8fuVMXfYihW6QMVwBYGp3d9Urxw/CJnlvMk wvqhgXEbsWd37XESXD3tEC1pukxeKC7iquLiKY4= X-Google-Smtp-Source: APXvYqzBLswPnrZOv9FXdT+Ka89QvSuyWfwL5jUYZwp/6jJiOx6fmqpnezYzVn5ckU7I3RT+BR1RWX6RUoZcaJu2P+M= X-Received: by 2002:ac2:4990:: with SMTP id f16mr20714968lfl.93.1559768839418; Wed, 05 Jun 2019 14:07:19 -0700 (PDT) MIME-Version: 1.0 References: <20190530135135.19715-1-Hesham.Almatary@cl.cam.ac.uk> <20190530135135.19715-4-Hesham.Almatary@cl.cam.ac.uk> In-Reply-To: <20190530135135.19715-4-Hesham.Almatary@cl.cam.ac.uk> From: Alistair Francis Date: Wed, 5 Jun 2019 14:04:46 -0700 Message-ID: To: Hesham Almatary Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::142 Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Jun 2019 21:07:44 -0000 On Thu, May 30, 2019 at 6:52 AM Hesham Almatary wrote: > > The PMP should be checked when doing a page table walk, and report access > fault exception if the to-be-read PTE failed the PMP check. > > Suggested-by: Jonathan Behrens > Signed-off-by: Hesham Almatary > --- > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 10 +++++++++- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c17184f4e4..ab3ba3f15a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -94,6 +94,7 @@ enum { > #define PRIV_VERSION_1_09_1 0x00010901 > #define PRIV_VERSION_1_10_0 0x00011000 > > +#define TRANSLATE_PMP_FAIL 2 > #define TRANSLATE_FAIL 1 > #define TRANSLATE_SUCCESS 0 > #define NB_MMU_MODES 4 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 5a1cd7cf96..00bc4f1712 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -211,6 +211,12 @@ restart: > > /* check that physical address of PTE is legal */ > target_ulong pte_addr = base + idx * ptesize; > + > + if (riscv_feature(env, RISCV_FEATURE_PMP) && > + !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), > + 1 << MMU_DATA_LOAD, PRV_S)) { Shouldn't we be passing mode in here? Alistair > + return TRANSLATE_PMP_FAIL; > + } > #if defined(TARGET_RISCV32) > target_ulong pte = ldl_phys(cs->as, pte_addr); > #elif defined(TARGET_RISCV64) > @@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > (ret == TRANSLATE_SUCCESS) && > !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type, > mode)) { > + ret = TRANSLATE_PMP_FAIL; > + } > + if (ret == TRANSLATE_PMP_FAIL) { > pmp_violation = true; > - ret = TRANSLATE_FAIL; > } > if (ret == TRANSLATE_SUCCESS) { > tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, > -- > 2.17.1 > >