* [PATCH] target/riscv: Fix VS mode hypervisor CSR access
@ 2022-05-06 16:54 Dylan Reid
2022-05-09 8:14 ` Alistair Francis
2022-05-09 9:21 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Dylan Reid @ 2022-05-06 16:54 UTC (permalink / raw)
To: qemu-devel; +Cc: palmer, alistair.francis, bin.meng, Dylan Reid
VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.
Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.
Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
---
target/riscv/csr.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92..4ea7df02c9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3141,13 +3141,13 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
- if (riscv_has_ext(env, RVH) &&
- env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env)) {
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
/*
- * We are in S mode without virtualisation, therefore we are in HS Mode.
+ * We are in either HS or VS mode.
* Add 1 to the effective privledge level to allow us to access the
- * Hypervisor CSRs.
+ * Hypervisor CSRs. The `hmode` predicate will determine if access
+ * should be allowed(HS) or if a virtual instruction exception should be
+ * raised(VS).
*/
effective_priv++;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Fix VS mode hypervisor CSR access
2022-05-06 16:54 [PATCH] target/riscv: Fix VS mode hypervisor CSR access Dylan Reid
@ 2022-05-09 8:14 ` Alistair Francis
2022-05-09 9:21 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-05-09 8:14 UTC (permalink / raw)
To: Dylan Reid
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, Dylan Reid
On Fri, May 6, 2022 at 11:16 PM Dylan Reid <dylan@rivosinc.com> wrote:
>
> VS mode access to hypervisor CSRs should generate virtual, not illegal,
> instruction exceptions.
>
> Don't return early and indicate an illegal instruction exception when
> accessing a hypervisor CSR from VS mode. Instead, fall through to the
> `hmode` predicate to return the correct virtual instruction exception.
>
> Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 3500e07f92..4ea7df02c9 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3141,13 +3141,13 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> #if !defined(CONFIG_USER_ONLY)
> int effective_priv = env->priv;
>
> - if (riscv_has_ext(env, RVH) &&
> - env->priv == PRV_S &&
> - !riscv_cpu_virt_enabled(env)) {
> + if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
> /*
> - * We are in S mode without virtualisation, therefore we are in HS Mode.
> + * We are in either HS or VS mode.
> * Add 1 to the effective privledge level to allow us to access the
> - * Hypervisor CSRs.
> + * Hypervisor CSRs. The `hmode` predicate will determine if access
> + * should be allowed(HS) or if a virtual instruction exception should be
> + * raised(VS).
> */
> effective_priv++;
> }
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Fix VS mode hypervisor CSR access
2022-05-06 16:54 [PATCH] target/riscv: Fix VS mode hypervisor CSR access Dylan Reid
2022-05-09 8:14 ` Alistair Francis
@ 2022-05-09 9:21 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-05-09 9:21 UTC (permalink / raw)
To: Dylan Reid
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, Dylan Reid
On Fri, May 6, 2022 at 11:16 PM Dylan Reid <dylan@rivosinc.com> wrote:
>
> VS mode access to hypervisor CSRs should generate virtual, not illegal,
> instruction exceptions.
>
> Don't return early and indicate an illegal instruction exception when
> accessing a hypervisor CSR from VS mode. Instead, fall through to the
> `hmode` predicate to return the correct virtual instruction exception.
>
> Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/csr.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 3500e07f92..4ea7df02c9 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3141,13 +3141,13 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> #if !defined(CONFIG_USER_ONLY)
> int effective_priv = env->priv;
>
> - if (riscv_has_ext(env, RVH) &&
> - env->priv == PRV_S &&
> - !riscv_cpu_virt_enabled(env)) {
> + if (riscv_has_ext(env, RVH) && env->priv == PRV_S) {
> /*
> - * We are in S mode without virtualisation, therefore we are in HS Mode.
> + * We are in either HS or VS mode.
> * Add 1 to the effective privledge level to allow us to access the
> - * Hypervisor CSRs.
> + * Hypervisor CSRs. The `hmode` predicate will determine if access
> + * should be allowed(HS) or if a virtual instruction exception should be
> + * raised(VS).
> */
> effective_priv++;
> }
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-05-06 16:54 [PATCH] target/riscv: Fix VS mode hypervisor CSR access Dylan Reid
2022-05-09 8:14 ` Alistair Francis
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