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From: Alistair Francis <alistair23@gmail.com>
To: Jim Shu <cwshu@andestech.com>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 2/3] target/riscv: add log of PMP permission checking
Date: Tue, 16 Mar 2021 16:02:25 -0400	[thread overview]
Message-ID: <CAKmqyKODi+WrX_P_Ca-_jHrtxARYTqat4jmNW+9Dc=UX2S-UOg@mail.gmail.com> (raw)
In-Reply-To: <1613914370-17285-3-git-send-email-cwshu@andestech.com>

On Sun, Feb 21, 2021 at 10:31 AM Jim Shu <cwshu@andestech.com> wrote:
>
> Like MMU translation, add qemu log of PMP permission checking for
> debugging.
>
> Signed-off-by: Jim Shu <cwshu@andestech.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f6ac63bf0e..c1ecb8a710 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -794,6 +794,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>              if (ret == TRANSLATE_SUCCESS) {
>                  ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
>                                                 size, access_type, mode);
> +
> +                qemu_log_mask(CPU_LOG_MMU,
> +                              "%s PMP address=" TARGET_FMT_plx " ret %d prot"
> +                              " %d tlb_size " TARGET_FMT_lu "\n",
> +                              __func__, pa, ret, prot_pmp, tlb_size);
> +
>                  prot &= prot_pmp;
>              }
>
> @@ -821,6 +827,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>          if (ret == TRANSLATE_SUCCESS) {
>              ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
>                                             size, access_type, mode);
> +
> +            qemu_log_mask(CPU_LOG_MMU,
> +                          "%s PMP address=" TARGET_FMT_plx " ret %d prot"
> +                          " %d tlb_size " TARGET_FMT_lu "\n",
> +                          __func__, pa, ret, prot_pmp, tlb_size);
> +
>              prot &= prot_pmp;
>          }
>      }
> --
> 2.30.1
>
>


  reply	other threads:[~2021-03-16 20:07 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1613914370-17285-1-git-send-email-cwshu@andestech.com>
2021-02-21 13:32 ` [PATCH 1/3] target/riscv: propagate PMP permission to TLB page Jim Shu
2021-02-21 13:32   ` Jim Shu
2021-02-21 13:32 ` [PATCH 2/3] target/riscv: add log of PMP permission checking Jim Shu
2021-02-21 13:32   ` Jim Shu
2021-03-16 20:02   ` Alistair Francis [this message]
2021-02-21 13:32 ` [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed Jim Shu
2021-02-21 13:32   ` Jim Shu
2021-02-21 14:01 [PATCH 0/3] target/riscv: fix PMP permission checking when softmmu's TLB hits Jim Shu
2021-02-21 14:01 ` [PATCH 2/3] target/riscv: add log of PMP permission checking Jim Shu
2021-02-21 14:01   ` Jim Shu

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