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Tue, 01 Feb 2022 22:36:29 -0800 (PST) MIME-Version: 1.0 References: <20220202005249.3566542-1-philipp.tomsich@vrull.eu> In-Reply-To: <20220202005249.3566542-1-philipp.tomsich@vrull.eu> From: Alistair Francis Date: Wed, 2 Feb 2022 16:36:03 +1000 Message-ID: Subject: Re: [PATCH v6 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes To: Philipp Tomsich Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d36 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::d36; envelope-from=alistair23@gmail.com; helo=mail-io1-xd36.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Kito Cheng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Greg Favor Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Feb 2, 2022 at 2:03 PM Philipp Tomsich wrote: > > > In adding our first X-extension (i.e., vendor-defined) on RISC-V with > XVentanaCondOps, we need to add a few instructure improvements to make > it easier to add similar vendor-defined extensions in the future: > - refactor access to the cfg->ext_* fields by making a pointer to the > cfg structure (as cfg_ptr) available via DisasContext > - add a table-based list of decoders to invoke, each being guarded by > a guard/predicate-function, that can be used to either add vendor > extensions, large extensions or override (by listing the decoder > before the one for standard extensions) patterns to handle errata > > > Changes in v6: > - add the 'vt' prefix to gen_condmask, renaming it to gen_vt_condmask > > Changes in v5: > - use the typedef in DisasContext instead of the nakes struct > for RISCVCPUConfig > - manually picked up those Reviewed-by tags from Richard that patman > missed > > Changes in v4: > - use a typedef into 'RISCVCPUConfig' (instead of the explicit > 'struct RISCVCPUConfig') to comply with the coding standard > (as suggested in Richard's review of v3) > - add braces to comply with coding standard (as suggested by Richard) > - merge the two if-statements to reduce clutter after (now that the > braces have been added) > > Changes in v3: > - (new patch) refactor 'struct RISCVCPUConfig' > - (new patch) copy pointer to element cfg into DisasContext > - (new patch) test extension-availability through cfg_ptr in > DisasContext, removing the fields that have been copied into > DisasContext directly > - (new patch) change Zb[abcs] implementation to use cfg_ptr (copied > into DisasContext) instead of going throuhg RISCV_CPU > - expose only the DisasContext* to predicate functions > - mark the table of decoder functions as static > - drop the inline from always_true_p, until the need arises (i.e., > someone finds a use for it and calls it directly) > - rewrite to drop the 'handled' temporary in iterating over the > decoder table, removing the assignment in the condition of the if > - rename to trans_xventanacondops.c.inc (i.e. with the '.c') > - (in MATERIALISE_EXT_PREDICATE) don't annotate the predicate function > for testing the availability of individual extensions as 'inline' > and don't make CPURISCVState* visible to these predicate functions > - add a MAINTAINERS entry for XVentanaCondOps > > Changes in v2: > - (new patch) iterate over a table of guarded decoder functions > - Split off decode table into XVentanaCondOps.decode > - Wire up XVentanaCondOps in the decoder-table > > Philipp Tomsich (7): > target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct > RISCVCPUConfig' > target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into > cfg_ptr > target/riscv: access configuration through cfg_ptr in DisasContext > target/riscv: access cfg structure through DisasContext > target/riscv: iterate over a table of decoders > target/riscv: Add XVentanaCondOps custom extension > target/riscv: add a MAINTAINERS entry for XVentanaCondOps Thanks! Applied to riscv-to-apply.next Alistair > > MAINTAINERS | 7 ++ > target/riscv/XVentanaCondOps.decode | 25 +++++ > target/riscv/cpu.c | 3 + > target/riscv/cpu.h | 81 +++++++------- > target/riscv/insn_trans/trans_rvb.c.inc | 8 +- > target/riscv/insn_trans/trans_rvi.c.inc | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++--------- > target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- > .../insn_trans/trans_xventanacondops.c.inc | 39 +++++++ > target/riscv/meson.build | 1 + > target/riscv/translate.c | 60 ++++++---- > 11 files changed, 219 insertions(+), 115 deletions(-) > create mode 100644 target/riscv/XVentanaCondOps.decode > create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc > > -- > 2.33.1 > >