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X-Received-From: 2a00:1450:4864:20::243 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Richard Henderson , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com, Chih-Min Chao , wenmeng_zhang@c-sky.com, Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Feb 18, 2020 at 4:46 PM LIU Zhiwei wrote: > > Hi, Alistair > > On 2020/2/19 6:34, Alistair Francis wrote: > > On Mon, Feb 10, 2020 at 12:12 AM LIU Zhiwei wrot= e: > >> Vector extension is default on only for "any" cpu. It can be turned > >> on by command line "-cpu rv64,v=3Dtrue,vlen=3D128,elen=3D64,vext_spec= =3Dv0.7.1". > >> > >> vlen is the vector register length, default value is 128 bit. > >> elen is the max operator size in bits, default value is 64 bit. > >> vext_spec is the vector specification version, default value is v0.7.1= . > >> Thest properties and cpu can be specified with other values. > >> > >> Signed-off-by: LIU Zhiwei > > This looks fine to me. Shouldn't this be the last patch though? > Yes=EF=BC=8C it should be the last patch. > > As in > > once the vector extension has been added to QEMU you can turn it on > > from the command line. Right now this turns it on but it isn't > > implemented. > Maybe I should just add fields in RISCVCPU structure. And never open the > vector extension on or add configure properties until the implementation > is ready. Yes, I think that is a good idea. > > It's still a little awkward as the reviewers will not be able to test > the patch until the > last patch. I understand, but I don't think anyone is going to want to test the extension half way through it being added to QEMU. This way we can start to merge patches even without full support as users can't turn it on. Alistair > > > Alistair > > > >> --- > >> target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++= -- > >> target/riscv/cpu.h | 8 ++++++++ > >> 2 files changed, 54 insertions(+), 2 deletions(-) > >> > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index 8c86ebc109..95fdb6261e 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, in= t priv_ver) > >> env->priv_ver =3D priv_ver; > >> } > >> > >> +static void set_vext_version(CPURISCVState *env, int vext_ver) > >> +{ > >> + env->vext_ver =3D vext_ver; > >> +} > >> + > >> static void set_feature(CPURISCVState *env, int feature) > >> { > >> env->features |=3D (1ULL << feature); > >> @@ -113,7 +118,7 @@ static void set_resetvec(CPURISCVState *env, int r= esetvec) > >> static void riscv_any_cpu_init(Object *obj) > >> { > >> CPURISCVState *env =3D &RISCV_CPU(obj)->env; > >> - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); > >> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | = RVV); > >> set_priv_version(env, PRIV_VERSION_1_11_0); > >> set_resetvec(env, DEFAULT_RSTVEC); > >> } > >> @@ -320,6 +325,7 @@ static void riscv_cpu_realize(DeviceState *dev, Er= ror **errp) > >> CPURISCVState *env =3D &cpu->env; > >> RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); > >> int priv_version =3D PRIV_VERSION_1_11_0; > >> + int vext_version =3D VEXT_VERSION_0_07_1; > >> target_ulong target_misa =3D 0; > >> Error *local_err =3D NULL; > >> > >> @@ -343,8 +349,18 @@ static void riscv_cpu_realize(DeviceState *dev, E= rror **errp) > >> return; > >> } > >> } > >> - > >> + if (cpu->cfg.vext_spec) { > >> + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { > >> + vext_version =3D VEXT_VERSION_0_07_1; > >> + } else { > >> + error_setg(errp, > >> + "Unsupported vector spec version '%s'", > >> + cpu->cfg.vext_spec); > >> + return; > >> + } > >> + } > >> set_priv_version(env, priv_version); > >> + set_vext_version(env, vext_version); > >> set_resetvec(env, DEFAULT_RSTVEC); > >> > >> if (cpu->cfg.mmu) { > >> @@ -409,6 +425,30 @@ static void riscv_cpu_realize(DeviceState *dev, E= rror **errp) > >> if (cpu->cfg.ext_u) { > >> target_misa |=3D RVU; > >> } > >> + if (cpu->cfg.ext_v) { > >> + target_misa |=3D RVV; > >> + if (!is_power_of_2(cpu->cfg.vlen)) { > >> + error_setg(errp, > >> + "Vector extension VLEN must be power of 2"); > >> + return; > >> + } > >> + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { > >> + error_setg(errp, > >> + "Vector extension implementation only supports= VLEN " > >> + "in the range [128, %d]", RV_VLEN_MAX); > >> + return; > >> + } > >> + if (!is_power_of_2(cpu->cfg.elen)) { > >> + error_setg(errp, > >> + "Vector extension ELEN must be power of 2"); > >> + return; > >> + } > >> + if (cpu->cfg.elen > 64) { > >> + error_setg(errp, > >> + "Vector extension ELEN must <=3D 64"); > >> + return; > >> + } > >> + } > >> > >> set_misa(env, RVXLEN | target_misa); > >> } > >> @@ -444,10 +484,14 @@ static Property riscv_cpu_properties[] =3D { > >> DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > >> DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > >> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > >> + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > >> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > >> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > >> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > >> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > >> + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > >> + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > >> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > >> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > >> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > >> DEFINE_PROP_END_OF_LIST(), > >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >> index 07e63016a7..bf2b4b55af 100644 > >> --- a/target/riscv/cpu.h > >> +++ b/target/riscv/cpu.h > >> @@ -64,6 +64,7 @@ > >> #define RVA RV('A') > >> #define RVF RV('F') > >> #define RVD RV('D') > >> +#define RVV RV('V') > >> #define RVC RV('C') > >> #define RVS RV('S') > >> #define RVU RV('U') > >> @@ -82,6 +83,8 @@ enum { > >> #define PRIV_VERSION_1_10_0 0x00011000 > >> #define PRIV_VERSION_1_11_0 0x00011100 > >> > >> +#define VEXT_VERSION_0_07_1 0x00000701 > >> + > >> #define TRANSLATE_PMP_FAIL 2 > >> #define TRANSLATE_FAIL 1 > >> #define TRANSLATE_SUCCESS 0 > >> @@ -118,6 +121,7 @@ struct CPURISCVState { > >> target_ulong badaddr; > >> > >> target_ulong priv_ver; > >> + target_ulong vext_ver; > >> target_ulong misa; > >> target_ulong misa_mask; > >> > >> @@ -226,12 +230,16 @@ typedef struct RISCVCPU { > >> bool ext_c; > >> bool ext_s; > >> bool ext_u; > >> + bool ext_v; > >> bool ext_counters; > >> bool ext_ifencei; > >> bool ext_icsr; > >> > >> char *priv_spec; > >> char *user_spec; > >> + char *vext_spec; > >> + uint16_t vlen; > >> + uint16_t elen; > >> bool mmu; > >> bool pmp; > >> } cfg; > >> -- > >> 2.23.0 > >> > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1j4Dup-0004Co-Pt for mharc-qemu-riscv@gnu.org; Tue, 18 Feb 2020 20:12:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45246) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4Dum-00047d-Ix for qemu-riscv@nongnu.org; Tue, 18 Feb 2020 20:12:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4Dul-0001jz-4Y for qemu-riscv@nongnu.org; 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d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Uc1rnFArpCrnrzRHRbrRKPXAtcLPWZhS6Dh9jV3fr98=; b=uTxrLtOUsO/WOl4TNMKLuC0koEO4T5m1H5MBAzsurS5HLugoIWWuzTOCIizElax9u2 Sbjg4iR3cUIc1tTeLJR97CvnM9MOgZof0LaRd5qPh/xKfA5zdX4Up29M1EqjB2v32Bu7 9TJH6owC/NFGMq3G4GXDJc2qijNLXT04Cm4S2Gh5e8nOGRgWo/gPxi/4MAx6knWqEhqb PIJFRJT4IkPR5IcGHMPnUTj6judrOCj5YYmv0zRzuMrNkwNsAtTctIu4cfMFHyTKvWzQ PY4vmirPCaOV75SnHDQde5S+88bmaxpf8C8A099mcRgsrnl1XaDsbjmsX6BEd5OpiLJI A72g== X-Gm-Message-State: APjAAAU+qncRYLiAR5hUXXlFsaoyPGFI/+Ak/MEMw2MaL91fvgoDP26o 8MmOn0IVMFYVn4ocDF/fwvgC4+k1Gk1xVVot86c= X-Google-Smtp-Source: APXvYqynZMmaKkJBsEo6H45GxcOmQ4R8MCmjGLXLeVo+g7XsmWvOxMB0bH9lxjQUj+AdBxYN8qXOgmE4UPBNfxbS/PQ= X-Received: by 2002:a2e:a36a:: with SMTP id i10mr13978247ljn.107.1582074749973; Tue, 18 Feb 2020 17:12:29 -0800 (PST) MIME-Version: 1.0 References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> <20200210081240.11481-3-zhiwei_liu@c-sky.com> <0eb6836a-b133-b3b1-6ef6-74dd341b1dd5@c-sky.com> In-Reply-To: <0eb6836a-b133-b3b1-6ef6-74dd341b1dd5@c-sky.com> From: Alistair Francis Date: Tue, 18 Feb 2020 17:05:04 -0800 Message-ID: Subject: Re: [PATCH v4 2/4] target/riscv: configure and turn on vector extension from command line To: LIU Zhiwei Cc: Richard Henderson , Chih-Min Chao , Palmer Dabbelt , wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, "qemu-devel@nongnu.org Developers" , "open list:RISC-V" Content-Type: text/plain; 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X-Received-From: 2a00:1450:4864:20::243 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Feb 2020 01:12:38 -0000 On Tue, Feb 18, 2020 at 4:46 PM LIU Zhiwei wrote: > > Hi, Alistair > > On 2020/2/19 6:34, Alistair Francis wrote: > > On Mon, Feb 10, 2020 at 12:12 AM LIU Zhiwei wrot= e: > >> Vector extension is default on only for "any" cpu. It can be turned > >> on by command line "-cpu rv64,v=3Dtrue,vlen=3D128,elen=3D64,vext_spec= =3Dv0.7.1". > >> > >> vlen is the vector register length, default value is 128 bit. > >> elen is the max operator size in bits, default value is 64 bit. > >> vext_spec is the vector specification version, default value is v0.7.1= . > >> Thest properties and cpu can be specified with other values. > >> > >> Signed-off-by: LIU Zhiwei > > This looks fine to me. Shouldn't this be the last patch though? > Yes=EF=BC=8C it should be the last patch. > > As in > > once the vector extension has been added to QEMU you can turn it on > > from the command line. Right now this turns it on but it isn't > > implemented. > Maybe I should just add fields in RISCVCPU structure. And never open the > vector extension on or add configure properties until the implementation > is ready. Yes, I think that is a good idea. > > It's still a little awkward as the reviewers will not be able to test > the patch until the > last patch. I understand, but I don't think anyone is going to want to test the extension half way through it being added to QEMU. This way we can start to merge patches even without full support as users can't turn it on. Alistair > > > Alistair > > > >> --- > >> target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++++= -- > >> target/riscv/cpu.h | 8 ++++++++ > >> 2 files changed, 54 insertions(+), 2 deletions(-) > >> > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index 8c86ebc109..95fdb6261e 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, in= t priv_ver) > >> env->priv_ver =3D priv_ver; > >> } > >> > >> +static void set_vext_version(CPURISCVState *env, int vext_ver) > >> +{ > >> + env->vext_ver =3D vext_ver; > >> +} > >> + > >> static void set_feature(CPURISCVState *env, int feature) > >> { > >> env->features |=3D (1ULL << feature); > >> @@ -113,7 +118,7 @@ static void set_resetvec(CPURISCVState *env, int r= esetvec) > >> static void riscv_any_cpu_init(Object *obj) > >> { > >> CPURISCVState *env =3D &RISCV_CPU(obj)->env; > >> - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); > >> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU | = RVV); > >> set_priv_version(env, PRIV_VERSION_1_11_0); > >> set_resetvec(env, DEFAULT_RSTVEC); > >> } > >> @@ -320,6 +325,7 @@ static void riscv_cpu_realize(DeviceState *dev, Er= ror **errp) > >> CPURISCVState *env =3D &cpu->env; > >> RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); > >> int priv_version =3D PRIV_VERSION_1_11_0; > >> + int vext_version =3D VEXT_VERSION_0_07_1; > >> target_ulong target_misa =3D 0; > >> Error *local_err =3D NULL; > >> > >> @@ -343,8 +349,18 @@ static void riscv_cpu_realize(DeviceState *dev, E= rror **errp) > >> return; > >> } > >> } > >> - > >> + if (cpu->cfg.vext_spec) { > >> + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { > >> + vext_version =3D VEXT_VERSION_0_07_1; > >> + } else { > >> + error_setg(errp, > >> + "Unsupported vector spec version '%s'", > >> + cpu->cfg.vext_spec); > >> + return; > >> + } > >> + } > >> set_priv_version(env, priv_version); > >> + set_vext_version(env, vext_version); > >> set_resetvec(env, DEFAULT_RSTVEC); > >> > >> if (cpu->cfg.mmu) { > >> @@ -409,6 +425,30 @@ static void riscv_cpu_realize(DeviceState *dev, E= rror **errp) > >> if (cpu->cfg.ext_u) { > >> target_misa |=3D RVU; > >> } > >> + if (cpu->cfg.ext_v) { > >> + target_misa |=3D RVV; > >> + if (!is_power_of_2(cpu->cfg.vlen)) { > >> + error_setg(errp, > >> + "Vector extension VLEN must be power of 2"); > >> + return; > >> + } > >> + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { > >> + error_setg(errp, > >> + "Vector extension implementation only supports= VLEN " > >> + "in the range [128, %d]", RV_VLEN_MAX); > >> + return; > >> + } > >> + if (!is_power_of_2(cpu->cfg.elen)) { > >> + error_setg(errp, > >> + "Vector extension ELEN must be power of 2"); > >> + return; > >> + } > >> + if (cpu->cfg.elen > 64) { > >> + error_setg(errp, > >> + "Vector extension ELEN must <=3D 64"); > >> + return; > >> + } > >> + } > >> > >> set_misa(env, RVXLEN | target_misa); > >> } > >> @@ -444,10 +484,14 @@ static Property riscv_cpu_properties[] =3D { > >> DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > >> DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > >> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > >> + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), > >> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > >> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > >> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > >> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > >> + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > >> + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > >> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > >> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > >> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > >> DEFINE_PROP_END_OF_LIST(), > >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >> index 07e63016a7..bf2b4b55af 100644 > >> --- a/target/riscv/cpu.h > >> +++ b/target/riscv/cpu.h > >> @@ -64,6 +64,7 @@ > >> #define RVA RV('A') > >> #define RVF RV('F') > >> #define RVD RV('D') > >> +#define RVV RV('V') > >> #define RVC RV('C') > >> #define RVS RV('S') > >> #define RVU RV('U') > >> @@ -82,6 +83,8 @@ enum { > >> #define PRIV_VERSION_1_10_0 0x00011000 > >> #define PRIV_VERSION_1_11_0 0x00011100 > >> > >> +#define VEXT_VERSION_0_07_1 0x00000701 > >> + > >> #define TRANSLATE_PMP_FAIL 2 > >> #define TRANSLATE_FAIL 1 > >> #define TRANSLATE_SUCCESS 0 > >> @@ -118,6 +121,7 @@ struct CPURISCVState { > >> target_ulong badaddr; > >> > >> target_ulong priv_ver; > >> + target_ulong vext_ver; > >> target_ulong misa; > >> target_ulong misa_mask; > >> > >> @@ -226,12 +230,16 @@ typedef struct RISCVCPU { > >> bool ext_c; > >> bool ext_s; > >> bool ext_u; > >> + bool ext_v; > >> bool ext_counters; > >> bool ext_ifencei; > >> bool ext_icsr; > >> > >> char *priv_spec; > >> char *user_spec; > >> + char *vext_spec; > >> + uint16_t vlen; > >> + uint16_t elen; > >> bool mmu; > >> bool pmp; > >> } cfg; > >> -- > >> 2.23.0 > >> >