From: Alistair Francis <alistair23@gmail.com>
To: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Cc: xen-devel@lists.xenproject.org,
Andrew Cooper <andrew.cooper3@citrix.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Gianluca Guida <gianluca@rivosinc.com>,
Bob Eshleman <bobbyeshleman@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
Connor Davis <connojdavis@gmail.com>
Subject: Re: [PATCH v1 04/14] xen/riscv: add <asm/csr.h> header
Date: Mon, 23 Jan 2023 09:25:14 +1000 [thread overview]
Message-ID: <CAKmqyKOmAg9D0r-k6Z3VoVSTynY58z0GUb+oCrkzi_Q9HZju_w@mail.gmail.com> (raw)
In-Reply-To: <afc53b9bee58b5d386f105ee8f23a411d5a15bed.1674226563.git.oleksii.kurochko@gmail.com>
On Sat, Jan 21, 2023 at 1:00 AM Oleksii Kurochko
<oleksii.kurochko@gmail.com> wrote:
>
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> xen/arch/riscv/include/asm/csr.h | 82 ++++++++++++++++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 xen/arch/riscv/include/asm/csr.h
>
> diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h
> new file mode 100644
> index 0000000000..1a879c6c4d
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/csr.h
> @@ -0,0 +1,82 @@
> +/*
> + * Take from Linux.
> + *
> + * SPDX-License-Identifier: GPL-2.0-only
> + *
> + * Copyright (C) 2015 Regents of the University of California
> + */
> +
> +#ifndef _ASM_RISCV_CSR_H
> +#define _ASM_RISCV_CSR_H
> +
> +#include <asm/asm.h>
> +#include <xen/const.h>
> +#include <asm/riscv_encoding.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#define csr_read(csr) \
> +({ \
> + register unsigned long __v; \
> + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
> + : "=r" (__v) : \
> + : "memory"); \
> + __v; \
> +})
> +
> +#define csr_write(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long)(val); \
> + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
> + : : "rK" (__v) \
> + : "memory"); \
> +})
> +
> +/*
> +#define csr_swap(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long)(val); \
> + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
> + : "=r" (__v) : "rK" (__v) \
> + : "memory"); \
> + __v; \
> +})
> +
> +#define csr_read_set(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long)(val); \
> + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
> + : "=r" (__v) : "rK" (__v) \
> + : "memory"); \
> + __v; \
> +})
> +
> +#define csr_set(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long)(val); \
> + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
> + : : "rK" (__v) \
> + : "memory"); \
> +})
> +
> +#define csr_read_clear(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long)(val); \
> + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
> + : "=r" (__v) : "rK" (__v) \
> + : "memory"); \
> + __v; \
> +})
> +
> +#define csr_clear(csr, val) \
> +({ \
> + unsigned long __v = (unsigned long)(val); \
> + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
> + : : "rK" (__v) \
> + : "memory"); \
> +})
> +*/
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _ASM_RISCV_CSR_H */
> --
> 2.39.0
>
>
next prev parent reply other threads:[~2023-01-22 23:26 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 14:59 [PATCH v1 00/14] RISCV basic exception handling implementation Oleksii Kurochko
2023-01-20 14:59 ` [PATCH v1 01/14] xen/riscv: add _zicsr to CFLAGS Oleksii Kurochko
2023-01-20 15:29 ` Andrew Cooper
2023-01-23 10:43 ` Oleksii
2023-01-31 11:49 ` Alistair Francis
2023-01-31 12:30 ` Oleksii
2023-01-20 14:59 ` [PATCH v1 02/14] xen/riscv: add <asm/asm.h> header Oleksii Kurochko
2023-01-20 15:31 ` Andrew Cooper
2023-01-23 11:00 ` Jan Beulich
2023-01-23 11:10 ` Andrew Cooper
2023-01-22 22:58 ` Alistair Francis
2023-01-20 14:59 ` [PATCH v1 03/14] xen/riscv: add <asm/riscv_encoding.h header Oleksii Kurochko
2023-01-22 23:24 ` Alistair Francis
2023-01-23 13:52 ` Jan Beulich
2023-01-23 14:04 ` Oleksii
2023-01-23 14:06 ` Jan Beulich
2023-01-20 14:59 ` [PATCH v1 04/14] xen/riscv: add <asm/csr.h> header Oleksii Kurochko
2023-01-22 23:25 ` Alistair Francis [this message]
2023-01-23 13:57 ` Jan Beulich
2023-01-23 14:23 ` Oleksii
2023-01-23 14:31 ` Jan Beulich
2023-01-20 14:59 ` [PATCH v1 05/14] xen/riscv: add early_printk_hnum() function Oleksii Kurochko
2023-01-20 15:39 ` Andrew Cooper
2023-01-23 12:05 ` Oleksii
2023-01-23 11:10 ` Jan Beulich
2023-01-20 14:59 ` [PATCH v1 06/14] xen/riscv: introduce exception context Oleksii Kurochko
2023-01-20 15:54 ` Andrew Cooper
2023-01-23 12:03 ` Oleksii
2023-01-23 12:25 ` Andrew Cooper
2023-01-23 11:13 ` Jan Beulich
2023-01-20 14:59 ` [PATCH v1 07/14] xen/riscv: introduce exception handlers implementation Oleksii Kurochko
2023-01-22 23:29 ` Alistair Francis
2023-01-23 11:17 ` Jan Beulich
2023-01-23 15:04 ` Oleksii
2023-01-23 11:50 ` Andrew Cooper
2023-01-23 12:41 ` Jan Beulich
2023-01-23 15:17 ` Oleksii
2023-01-23 20:09 ` Andrew Cooper
2023-01-25 14:44 ` Oleksii
2023-01-20 14:59 ` [PATCH v1 08/14] xen/riscv: introduce decode_cause() stuff Oleksii Kurochko
2023-01-22 23:38 ` Alistair Francis
2023-01-23 12:09 ` Andrew Cooper
2023-01-20 14:59 ` [PATCH v1 09/14] xen/riscv: introduce do_unexpected_trap() Oleksii Kurochko
2023-01-22 23:39 ` Alistair Francis
2023-01-25 17:01 ` Oleksii
2023-01-25 17:11 ` Julien Grall
2023-01-25 17:15 ` Andrew Cooper
2023-01-26 8:40 ` Oleksii
2023-01-20 14:59 ` [PATCH v1 10/14] xen/riscv: mask all interrupts Oleksii Kurochko
2023-01-22 23:40 ` Alistair Francis
2023-01-20 14:59 ` [PATCH v1 11/14] xen/riscv: introduce setup_trap_handler() Oleksii Kurochko
2023-01-22 23:41 ` Alistair Francis
2023-01-23 23:21 ` Andrew Cooper
2023-01-20 14:59 ` [PATCH v1 12/14] xen/riscv: introduce an implementation of macros from <asm/bug.h> Oleksii Kurochko
2023-01-23 11:37 ` Jan Beulich
2023-01-20 14:59 ` [PATCH v1 13/14] xen/riscv: test basic handling stuff Oleksii Kurochko
2023-01-20 14:59 ` [PATCH v1 14/14] automation: add smoke test to verify macros from bug.h Oleksii Kurochko
2023-01-24 23:53 ` Stefano Stabellini
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