This patch series adds the STM32VLDISCOVERY Machine to QEMU Information on the board is available at: https://www.st.com/en/evaluation-tools/stm32vldiscovery.html v3: - Add test for STM32VLDISCOVERY USART1 v2: - Add documentation of STM32 boards - Fixed number of interrupts - Fixed Cortex-M3 name Alexandre Iooss (4): stm32f100: Add the stm32f100 SoC stm32vldiscovery: Add the STM32VLDISCOVERY Machine docs/system: arm: Add stm32 boards description tests/boot-serial-test: Add STM32VLDISCOVERY board testcase MAINTAINERS | 13 ++ default-configs/devices/arm-softmmu.mak | 1 + docs/system/arm/stm32.rst | 66 +++++++++ docs/system/target-arm.rst | 1 + hw/arm/Kconfig | 10 ++ hw/arm/meson.build | 2 + hw/arm/stm32f100_soc.c | 182 ++++++++++++++++++++++++ hw/arm/stm32vldiscovery.c | 66 +++++++++ include/hw/arm/stm32f100_soc.h | 57 ++++++++ tests/qtest/boot-serial-test.c | 37 +++++ 10 files changed, 435 insertions(+) create mode 100644 docs/system/arm/stm32.rst create mode 100644 hw/arm/stm32f100_soc.c create mode 100644 hw/arm/stm32vldiscovery.c create mode 100644 include/hw/arm/stm32f100_soc.h -- 2.25.1
This SoC is similar to stm32f205 SoC. This will be used by the STM32VLDISCOVERY to create a machine. Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> --- MAINTAINERS | 6 ++ hw/arm/Kconfig | 6 ++ hw/arm/meson.build | 1 + hw/arm/stm32f100_soc.c | 182 +++++++++++++++++++++++++++++++++ include/hw/arm/stm32f100_soc.h | 57 +++++++++++ 5 files changed, 252 insertions(+) create mode 100644 hw/arm/stm32f100_soc.c create mode 100644 include/hw/arm/stm32f100_soc.h diff --git a/MAINTAINERS b/MAINTAINERS index 7d9cd29042..62dfa31800 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -946,6 +946,12 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/virt-acpi-build.c +STM32F100 +M: Alexandre Iooss <erdnaxe@crans.org> +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/stm32f100_soc.c + STM32F205 M: Alistair Francis <alistair@alistair23.me> M: Peter Maydell <peter.maydell@linaro.org> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 67723d9ea6..0bc3ee3e91 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -326,6 +326,12 @@ config RASPI select SDHCI select USB_DWC2 +config STM32F100_SOC + bool + select ARM_V7M + select STM32F2XX_USART + select STM32F2XX_SPI + config STM32F205_SOC bool select ARM_V7M diff --git a/hw/arm/meson.build b/hw/arm/meson.build index be39117b9b..0e637e6a9e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c new file mode 100644 index 0000000000..0c4a5c6645 --- /dev/null +++ b/hw/arm/stm32f100_soc.c @@ -0,0 +1,182 @@ +/* + * STM32F100 SoC + * + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/arm/boot.h" +#include "exec/address-spaces.h" +#include "hw/arm/stm32f100_soc.h" +#include "hw/qdev-properties.h" +#include "hw/misc/unimp.h" +#include "sysemu/sysemu.h" + +/* stm32f100_soc implementation is derived from stm32f205_soc */ + +static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400, + 0x40004800 }; +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 }; + +static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39}; +static const int spi_irq[STM_NUM_SPIS] = {35, 36}; + +static void stm32f100_soc_initfn(Object *obj) +{ + STM32F100State *s = STM32F100_SOC(obj); + int i; + + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); + + for (i = 0; i < STM_NUM_USARTS; i++) { + object_initialize_child(obj, "usart[*]", &s->usart[i], + TYPE_STM32F2XX_USART); + } + + for (i = 0; i < STM_NUM_SPIS; i++) { + object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); + } +} + +static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) +{ + STM32F100State *s = STM32F100_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + int i; + + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *sram = g_new(MemoryRegion, 1); + MemoryRegion *flash = g_new(MemoryRegion, 1); + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); + + /* + * Init flash region + * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 + */ + memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash", + FLASH_SIZE, &error_fatal); + memory_region_init_alias(flash_alias, OBJECT(dev_soc), + "STM32F100.flash.alias", flash, 0, FLASH_SIZE); + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); + memory_region_add_subregion(system_memory, 0, flash_alias); + + /* Init SRAM region */ + memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE, + &error_fatal); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + /* Init ARMv7m */ + armv7m = DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 61); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + object_property_set_link(OBJECT(&s->armv7m), "memory", + OBJECT(get_system_memory()), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { + return; + } + + /* Attach UART (uses USART registers) and USART controllers */ + for (i = 0; i < STM_NUM_USARTS; i++) { + dev = DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); + } + + /* SPI 1 and 2 */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); + } + + create_unimplemented_device("timer[2]", 0x40000000, 0x400); + create_unimplemented_device("timer[3]", 0x40000400, 0x400); + create_unimplemented_device("timer[4]", 0x40000800, 0x400); + create_unimplemented_device("timer[6]", 0x40001000, 0x400); + create_unimplemented_device("timer[7]", 0x40001400, 0x400); + create_unimplemented_device("RTC", 0x40002800, 0x400); + create_unimplemented_device("WWDG", 0x40002C00, 0x400); + create_unimplemented_device("IWDG", 0x40003000, 0x400); + create_unimplemented_device("I2C1", 0x40005400, 0x400); + create_unimplemented_device("I2C2", 0x40005800, 0x400); + create_unimplemented_device("BKP", 0x40006C00, 0x400); + create_unimplemented_device("PWR", 0x40007000, 0x400); + create_unimplemented_device("DAC", 0x40007400, 0x400); + create_unimplemented_device("CEC", 0x40007800, 0x400); + create_unimplemented_device("AFIO", 0x40010000, 0x400); + create_unimplemented_device("EXTI", 0x40010400, 0x400); + create_unimplemented_device("GPIOA", 0x40010800, 0x400); + create_unimplemented_device("GPIOB", 0x40010C00, 0x400); + create_unimplemented_device("GPIOC", 0x40011000, 0x400); + create_unimplemented_device("GPIOD", 0x40011400, 0x400); + create_unimplemented_device("GPIOE", 0x40011800, 0x400); + create_unimplemented_device("ADC1", 0x40012400, 0x400); + create_unimplemented_device("timer[1]", 0x40012C00, 0x400); + create_unimplemented_device("timer[15]", 0x40014000, 0x400); + create_unimplemented_device("timer[16]", 0x40014400, 0x400); + create_unimplemented_device("timer[17]", 0x40014800, 0x400); + create_unimplemented_device("DMA", 0x40020000, 0x400); + create_unimplemented_device("RCC", 0x40021000, 0x400); + create_unimplemented_device("Flash Int", 0x40022000, 0x400); + create_unimplemented_device("CRC", 0x40023000, 0x400); +} + +static Property stm32f100_soc_properties[] = { + DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32f100_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stm32f100_soc_realize; + device_class_set_props(dc, stm32f100_soc_properties); +} + +static const TypeInfo stm32f100_soc_info = { + .name = TYPE_STM32F100_SOC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F100State), + .instance_init = stm32f100_soc_initfn, + .class_init = stm32f100_soc_class_init, +}; + +static void stm32f100_soc_types(void) +{ + type_register_static(&stm32f100_soc_info); +} + +type_init(stm32f100_soc_types) diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h new file mode 100644 index 0000000000..71bffcf4fd --- /dev/null +++ b/include/hw/arm/stm32f100_soc.h @@ -0,0 +1,57 @@ +/* + * STM32F100 SoC + * + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_STM32F100_SOC_H +#define HW_ARM_STM32F100_SOC_H + +#include "hw/char/stm32f2xx_usart.h" +#include "hw/ssi/stm32f2xx_spi.h" +#include "hw/arm/armv7m.h" +#include "qom/object.h" + +#define TYPE_STM32F100_SOC "stm32f100-soc" +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) + +#define STM_NUM_USARTS 3 +#define STM_NUM_SPIS 2 + +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_SIZE (128 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (8 * 1024) + +struct STM32F100State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + char *cpu_type; + + ARMv7MState armv7m; + + STM32F2XXUsartState usart[STM_NUM_USARTS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; +}; + +#endif -- 2.25.1
This is a Cortex-M3 based machine. Information can be found at: https://www.st.com/en/evaluation-tools/stm32vldiscovery.html Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> --- MAINTAINERS | 6 +++ default-configs/devices/arm-softmmu.mak | 1 + hw/arm/Kconfig | 4 ++ hw/arm/meson.build | 1 + hw/arm/stm32vldiscovery.c | 66 +++++++++++++++++++++++++ 5 files changed, 78 insertions(+) create mode 100644 hw/arm/stm32vldiscovery.c diff --git a/MAINTAINERS b/MAINTAINERS index 62dfa31800..0aa8016936 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -891,6 +891,12 @@ F: hw/*/stellaris* F: include/hw/input/gamepad.h F: docs/system/arm/stellaris.rst +STM32VLDISCOVERY +M: Alexandre Iooss <erdnaxe@crans.org> +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/stm32vldiscovery.c + Versatile Express M: Peter Maydell <peter.maydell@linaro.org> L: qemu-arm@nongnu.org diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0500156a0c..cdc0e97f9d 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -18,6 +18,7 @@ CONFIG_CHEETAH=y CONFIG_SX1=y CONFIG_NSERIES=y CONFIG_STELLARIS=y +CONFIG_STM32VLDISCOVERY=y CONFIG_REALVIEW=y CONFIG_VERSATILE=y CONFIG_VEXPRESS=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0bc3ee3e91..dc4e47b721 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -239,6 +239,10 @@ config STELLARIS select STELLARIS_ENET # ethernet select UNIMP +config STM32VLDISCOVERY + bool + select STM32F100_SOC + config STRONGARM bool select PXA2XX diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 0e637e6a9e..721a8eb8be 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -24,6 +24,7 @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) +arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c new file mode 100644 index 0000000000..7e8191ebf5 --- /dev/null +++ b/hw/arm/stm32vldiscovery.c @@ -0,0 +1,66 @@ +/* + * ST STM32VLDISCOVERY machine + * + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f100_soc.h" +#include "hw/arm/boot.h" + +/* stm32vldiscovery implementation is derived from netduinoplus2 */ + +/* Main SYSCLK frequency in Hz (24MHz) */ +#define SYSCLK_FRQ 24000000ULL + +static void stm32vldiscovery_init(MachineState *machine) +{ + DeviceState *dev; + + /* + * TODO: ideally we would model the SoC RCC and let it handle + * system_clock_scale, including its ability to define different + * possible SYSCLK sources. + */ + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; + + dev = qdev_new(TYPE_STM32F100_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + FLASH_SIZE); +} + +static void stm32vldiscovery_machine_init(MachineClass *mc) +{ + mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; + mc->init = stm32vldiscovery_init; +} + +DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) + -- 2.25.1
This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY. Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> --- MAINTAINERS | 1 + docs/system/arm/stm32.rst | 66 ++++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 3 files changed, 68 insertions(+) create mode 100644 docs/system/arm/stm32.rst diff --git a/MAINTAINERS b/MAINTAINERS index 0aa8016936..47fb06e5fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -896,6 +896,7 @@ M: Alexandre Iooss <erdnaxe@crans.org> L: qemu-arm@nongnu.org S: Maintained F: hw/arm/stm32vldiscovery.c +F: docs/system/arm/stm32.rst Versatile Express M: Peter Maydell <peter.maydell@linaro.org> diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst new file mode 100644 index 0000000000..508b92cf86 --- /dev/null +++ b/docs/system/arm/stm32.rst @@ -0,0 +1,66 @@ +STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``) +======================================================================================== + +The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by +STMicroelectronics. + +.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html + +The STM32F1 series is based on ARM Cortex-M3 core. The following machines are +based on this chip : + +- ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller + +The STM32F2 series is based on ARM Cortex-M3 core. The following machines are +based on this chip : + +- ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller + +The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin +compatible with STM32F2 series. The following machines are based on this chip : + +- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller + +There are many other STM32 series that are currently not supported by QEMU. + +Supported devices +----------------- + + * ARM Cortex-M3, Cortex M4F + * Analog to Digital Converter (ADC) + * EXTI interrupt + * Serial ports (USART) + * SPI controller + * System configuration (SYSCFG) + * Timer controller (TIMER) + +Missing devices +--------------- + + * Camera interface (DCMI) + * Controller Area Network (CAN) + * Cycle Redundancy Check (CRC) calculation unit + * Digital to Analog Converter (DAC) + * DMA controller + * Ethernet controller + * Flash Interface Unit + * GPIO controller + * I2C controller + * Inter-Integrated Sound (I2S) controller + * Power supply configuration (PWR) + * Random Number Generator (RNG) + * Real-Time Clock (RTC) controller + * Reset and Clock Controller (RCC) + * Secure Digital Input/Output (SDIO) interface + * USB OTG + * Watchdog controller (IWDG, WWDG) + +Boot options +------------ + +The STM32 machines can be started using the ``-kernel`` option to load a +firmware. Example: + +.. code-block:: bash + + $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index edd013c7bb..addd3d1613 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -96,6 +96,7 @@ undocumented; you can get a complete list by running arm/collie arm/sx1 arm/stellaris + arm/stm32 arm/virt arm/xlnx-versal-virt -- 2.25.1
New mini-kernel test for STM32VLDISCOVERY USART1. Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> --- tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index d40adddafa..96849cec91 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] = { 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */ }; +static const uint8_t kernel_stm32vldiscovery[] = { + 0x00, 0x00, 0x00, 0x00, /* Stack top address */ + 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */ + 0x00, 0x00, 0x00, 0x00, /* NMI */ + 0x00, 0x00, 0x00, 0x00, /* Hard fault */ + 0x00, 0x00, 0x00, 0x00, /* Memory management fault */ + 0x00, 0x00, 0x00, 0x00, /* Bus fault */ + 0x00, 0x00, 0x00, 0x00, /* Usage fault */ + 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */ + 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */ + 0x1a, 0x68, /* ldr r2, [r3] */ + 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x1a, 0x68, /* ldr r2, [r3] */ + 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */ + 0x45, 0x22, /* movs r2, #69 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */ + 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */ + 0x54, 0x22, /* movs r2, 'T' */ + 0x1a, 0x60, /* str r2, [r3] */ + 0xfe, 0xe7, /* b . */ + 0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */ + 0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */ + 0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */ + 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */ + 0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */ +}; + typedef struct testdef { const char *arch; /* Target architecture */ const char *machine; /* Name of the machine */ @@ -144,6 +179,8 @@ static testdef_t tests[] = { { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64), kernel_aarch64 }, { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, + { "arm", "stm32vldiscovery", "", "T", + sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery }, { NULL } }; -- 2.25.1
On 17/06/2021 18.56, Alexandre Iooss wrote:
> New mini-kernel test for STM32VLDISCOVERY USART1.
>
> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
> ---
> tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
> index d40adddafa..96849cec91 100644
> --- a/tests/qtest/boot-serial-test.c
> +++ b/tests/qtest/boot-serial-test.c
> @@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] = {
> 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
> };
>
> +static const uint8_t kernel_stm32vldiscovery[] = {
> + 0x00, 0x00, 0x00, 0x00, /* Stack top address */
> + 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */
> + 0x00, 0x00, 0x00, 0x00, /* NMI */
> + 0x00, 0x00, 0x00, 0x00, /* Hard fault */
> + 0x00, 0x00, 0x00, 0x00, /* Memory management fault */
> + 0x00, 0x00, 0x00, 0x00, /* Bus fault */
> + 0x00, 0x00, 0x00, 0x00, /* Usage fault */
> + 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */
> + 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */
> + 0x1a, 0x60, /* str r2, [r3] */
> + 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */
> + 0x1a, 0x68, /* ldr r2, [r3] */
> + 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */
> + 0x1a, 0x60, /* str r2, [r3] */
> + 0x1a, 0x68, /* ldr r2, [r3] */
> + 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */
> + 0x1a, 0x60, /* str r2, [r3] */
> + 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */
> + 0x45, 0x22, /* movs r2, #69 */
> + 0x1a, 0x60, /* str r2, [r3] */
> + 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */
> + 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */
> + 0x1a, 0x60, /* str r2, [r3] */
> + 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */
> + 0x54, 0x22, /* movs r2, 'T' */
> + 0x1a, 0x60, /* str r2, [r3] */
> + 0xfe, 0xe7, /* b . */
> + 0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */
> + 0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */
> + 0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */
> + 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */
> + 0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */
> +};
> +
> typedef struct testdef {
> const char *arch; /* Target architecture */
> const char *machine; /* Name of the machine */
> @@ -144,6 +179,8 @@ static testdef_t tests[] = {
> { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
> kernel_aarch64 },
> { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
> + { "arm", "stm32vldiscovery", "", "T",
> + sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
>
> { NULL }
> };
>
Acked-by: Thomas Huth <thuth@redhat.com>
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss <erdnaxe@crans.org> wrote: > > This SoC is similar to stm32f205 SoC. > This will be used by the STM32VLDISCOVERY to create a machine. > > Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> Please keep any Reviewed by tags for a patch between versions if you don't make large changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > MAINTAINERS | 6 ++ > hw/arm/Kconfig | 6 ++ > hw/arm/meson.build | 1 + > hw/arm/stm32f100_soc.c | 182 +++++++++++++++++++++++++++++++++ > include/hw/arm/stm32f100_soc.h | 57 +++++++++++ > 5 files changed, 252 insertions(+) > create mode 100644 hw/arm/stm32f100_soc.c > create mode 100644 include/hw/arm/stm32f100_soc.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7d9cd29042..62dfa31800 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -946,6 +946,12 @@ L: qemu-arm@nongnu.org > S: Maintained > F: hw/arm/virt-acpi-build.c > > +STM32F100 > +M: Alexandre Iooss <erdnaxe@crans.org> > +L: qemu-arm@nongnu.org > +S: Maintained > +F: hw/arm/stm32f100_soc.c > + > STM32F205 > M: Alistair Francis <alistair@alistair23.me> > M: Peter Maydell <peter.maydell@linaro.org> > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 67723d9ea6..0bc3ee3e91 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -326,6 +326,12 @@ config RASPI > select SDHCI > select USB_DWC2 > > +config STM32F100_SOC > + bool > + select ARM_V7M > + select STM32F2XX_USART > + select STM32F2XX_SPI > + > config STM32F205_SOC > bool > select ARM_V7M > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index be39117b9b..0e637e6a9e 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) > arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) > arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) > arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c')) > +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) > arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) > arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) > arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c')) > diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c > new file mode 100644 > index 0000000000..0c4a5c6645 > --- /dev/null > +++ b/hw/arm/stm32f100_soc.c > @@ -0,0 +1,182 @@ > +/* > + * STM32F100 SoC > + * > + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu/module.h" > +#include "hw/arm/boot.h" > +#include "exec/address-spaces.h" > +#include "hw/arm/stm32f100_soc.h" > +#include "hw/qdev-properties.h" > +#include "hw/misc/unimp.h" > +#include "sysemu/sysemu.h" > + > +/* stm32f100_soc implementation is derived from stm32f205_soc */ > + > +static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400, > + 0x40004800 }; > +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 }; > + > +static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39}; > +static const int spi_irq[STM_NUM_SPIS] = {35, 36}; > + > +static void stm32f100_soc_initfn(Object *obj) > +{ > + STM32F100State *s = STM32F100_SOC(obj); > + int i; > + > + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); > + > + for (i = 0; i < STM_NUM_USARTS; i++) { > + object_initialize_child(obj, "usart[*]", &s->usart[i], > + TYPE_STM32F2XX_USART); > + } > + > + for (i = 0; i < STM_NUM_SPIS; i++) { > + object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); > + } > +} > + > +static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) > +{ > + STM32F100State *s = STM32F100_SOC(dev_soc); > + DeviceState *dev, *armv7m; > + SysBusDevice *busdev; > + int i; > + > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *sram = g_new(MemoryRegion, 1); > + MemoryRegion *flash = g_new(MemoryRegion, 1); > + MemoryRegion *flash_alias = g_new(MemoryRegion, 1); > + > + /* > + * Init flash region > + * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 > + */ > + memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash", > + FLASH_SIZE, &error_fatal); > + memory_region_init_alias(flash_alias, OBJECT(dev_soc), > + "STM32F100.flash.alias", flash, 0, FLASH_SIZE); > + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); > + memory_region_add_subregion(system_memory, 0, flash_alias); > + > + /* Init SRAM region */ > + memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE, > + &error_fatal); > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); > + > + /* Init ARMv7m */ > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 61); > + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); > + qdev_prop_set_bit(armv7m, "enable-bitband", true); > + object_property_set_link(OBJECT(&s->armv7m), "memory", > + OBJECT(get_system_memory()), &error_abort); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { > + return; > + } > + > + /* Attach UART (uses USART registers) and USART controllers */ > + for (i = 0; i < STM_NUM_USARTS; i++) { > + dev = DEVICE(&(s->usart[i])); > + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, usart_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); > + } > + > + /* SPI 1 and 2 */ > + for (i = 0; i < STM_NUM_SPIS; i++) { > + dev = DEVICE(&(s->spi[i])); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { > + return; > + } > + busdev = SYS_BUS_DEVICE(dev); > + sysbus_mmio_map(busdev, 0, spi_addr[i]); > + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); > + } > + > + create_unimplemented_device("timer[2]", 0x40000000, 0x400); > + create_unimplemented_device("timer[3]", 0x40000400, 0x400); > + create_unimplemented_device("timer[4]", 0x40000800, 0x400); > + create_unimplemented_device("timer[6]", 0x40001000, 0x400); > + create_unimplemented_device("timer[7]", 0x40001400, 0x400); > + create_unimplemented_device("RTC", 0x40002800, 0x400); > + create_unimplemented_device("WWDG", 0x40002C00, 0x400); > + create_unimplemented_device("IWDG", 0x40003000, 0x400); > + create_unimplemented_device("I2C1", 0x40005400, 0x400); > + create_unimplemented_device("I2C2", 0x40005800, 0x400); > + create_unimplemented_device("BKP", 0x40006C00, 0x400); > + create_unimplemented_device("PWR", 0x40007000, 0x400); > + create_unimplemented_device("DAC", 0x40007400, 0x400); > + create_unimplemented_device("CEC", 0x40007800, 0x400); > + create_unimplemented_device("AFIO", 0x40010000, 0x400); > + create_unimplemented_device("EXTI", 0x40010400, 0x400); > + create_unimplemented_device("GPIOA", 0x40010800, 0x400); > + create_unimplemented_device("GPIOB", 0x40010C00, 0x400); > + create_unimplemented_device("GPIOC", 0x40011000, 0x400); > + create_unimplemented_device("GPIOD", 0x40011400, 0x400); > + create_unimplemented_device("GPIOE", 0x40011800, 0x400); > + create_unimplemented_device("ADC1", 0x40012400, 0x400); > + create_unimplemented_device("timer[1]", 0x40012C00, 0x400); > + create_unimplemented_device("timer[15]", 0x40014000, 0x400); > + create_unimplemented_device("timer[16]", 0x40014400, 0x400); > + create_unimplemented_device("timer[17]", 0x40014800, 0x400); > + create_unimplemented_device("DMA", 0x40020000, 0x400); > + create_unimplemented_device("RCC", 0x40021000, 0x400); > + create_unimplemented_device("Flash Int", 0x40022000, 0x400); > + create_unimplemented_device("CRC", 0x40023000, 0x400); > +} > + > +static Property stm32f100_soc_properties[] = { > + DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void stm32f100_soc_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = stm32f100_soc_realize; > + device_class_set_props(dc, stm32f100_soc_properties); > +} > + > +static const TypeInfo stm32f100_soc_info = { > + .name = TYPE_STM32F100_SOC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(STM32F100State), > + .instance_init = stm32f100_soc_initfn, > + .class_init = stm32f100_soc_class_init, > +}; > + > +static void stm32f100_soc_types(void) > +{ > + type_register_static(&stm32f100_soc_info); > +} > + > +type_init(stm32f100_soc_types) > diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h > new file mode 100644 > index 0000000000..71bffcf4fd > --- /dev/null > +++ b/include/hw/arm/stm32f100_soc.h > @@ -0,0 +1,57 @@ > +/* > + * STM32F100 SoC > + * > + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_ARM_STM32F100_SOC_H > +#define HW_ARM_STM32F100_SOC_H > + > +#include "hw/char/stm32f2xx_usart.h" > +#include "hw/ssi/stm32f2xx_spi.h" > +#include "hw/arm/armv7m.h" > +#include "qom/object.h" > + > +#define TYPE_STM32F100_SOC "stm32f100-soc" > +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) > + > +#define STM_NUM_USARTS 3 > +#define STM_NUM_SPIS 2 > + > +#define FLASH_BASE_ADDRESS 0x08000000 > +#define FLASH_SIZE (128 * 1024) > +#define SRAM_BASE_ADDRESS 0x20000000 > +#define SRAM_SIZE (8 * 1024) > + > +struct STM32F100State { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + char *cpu_type; > + > + ARMv7MState armv7m; > + > + STM32F2XXUsartState usart[STM_NUM_USARTS]; > + STM32F2XXSPIState spi[STM_NUM_SPIS]; > +}; > + > +#endif > -- > 2.25.1 >
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss <erdnaxe@crans.org> wrote: > > This is a Cortex-M3 based machine. Information can be found at: > https://www.st.com/en/evaluation-tools/stm32vldiscovery.html > > Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > MAINTAINERS | 6 +++ > default-configs/devices/arm-softmmu.mak | 1 + > hw/arm/Kconfig | 4 ++ > hw/arm/meson.build | 1 + > hw/arm/stm32vldiscovery.c | 66 +++++++++++++++++++++++++ > 5 files changed, 78 insertions(+) > create mode 100644 hw/arm/stm32vldiscovery.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 62dfa31800..0aa8016936 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -891,6 +891,12 @@ F: hw/*/stellaris* > F: include/hw/input/gamepad.h > F: docs/system/arm/stellaris.rst > > +STM32VLDISCOVERY > +M: Alexandre Iooss <erdnaxe@crans.org> > +L: qemu-arm@nongnu.org > +S: Maintained > +F: hw/arm/stm32vldiscovery.c > + > Versatile Express > M: Peter Maydell <peter.maydell@linaro.org> > L: qemu-arm@nongnu.org > diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak > index 0500156a0c..cdc0e97f9d 100644 > --- a/default-configs/devices/arm-softmmu.mak > +++ b/default-configs/devices/arm-softmmu.mak > @@ -18,6 +18,7 @@ CONFIG_CHEETAH=y > CONFIG_SX1=y > CONFIG_NSERIES=y > CONFIG_STELLARIS=y > +CONFIG_STM32VLDISCOVERY=y > CONFIG_REALVIEW=y > CONFIG_VERSATILE=y > CONFIG_VEXPRESS=y > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 0bc3ee3e91..dc4e47b721 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -239,6 +239,10 @@ config STELLARIS > select STELLARIS_ENET # ethernet > select UNIMP > > +config STM32VLDISCOVERY > + bool > + select STM32F100_SOC > + > config STRONGARM > bool > select PXA2XX > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index 0e637e6a9e..721a8eb8be 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -24,6 +24,7 @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) > arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) > arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) > arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) > +arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) > arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) > arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) > arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) > diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c > new file mode 100644 > index 0000000000..7e8191ebf5 > --- /dev/null > +++ b/hw/arm/stm32vldiscovery.c > @@ -0,0 +1,66 @@ > +/* > + * ST STM32VLDISCOVERY machine > + * > + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org> > + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "hw/boards.h" > +#include "hw/qdev-properties.h" > +#include "qemu/error-report.h" > +#include "hw/arm/stm32f100_soc.h" > +#include "hw/arm/boot.h" > + > +/* stm32vldiscovery implementation is derived from netduinoplus2 */ > + > +/* Main SYSCLK frequency in Hz (24MHz) */ > +#define SYSCLK_FRQ 24000000ULL > + > +static void stm32vldiscovery_init(MachineState *machine) > +{ > + DeviceState *dev; > + > + /* > + * TODO: ideally we would model the SoC RCC and let it handle > + * system_clock_scale, including its ability to define different > + * possible SYSCLK sources. > + */ > + system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; > + > + dev = qdev_new(TYPE_STM32F100_SOC); > + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); > + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); > + > + armv7m_load_kernel(ARM_CPU(first_cpu), > + machine->kernel_filename, > + FLASH_SIZE); > +} > + > +static void stm32vldiscovery_machine_init(MachineClass *mc) > +{ > + mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)"; > + mc->init = stm32vldiscovery_init; > +} > + > +DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) > + > -- > 2.25.1 >
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss <erdnaxe@crans.org> wrote: > > This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY. > > Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > MAINTAINERS | 1 + > docs/system/arm/stm32.rst | 66 ++++++++++++++++++++++++++++++++++++++ > docs/system/target-arm.rst | 1 + > 3 files changed, 68 insertions(+) > create mode 100644 docs/system/arm/stm32.rst > > diff --git a/MAINTAINERS b/MAINTAINERS > index 0aa8016936..47fb06e5fc 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -896,6 +896,7 @@ M: Alexandre Iooss <erdnaxe@crans.org> > L: qemu-arm@nongnu.org > S: Maintained > F: hw/arm/stm32vldiscovery.c > +F: docs/system/arm/stm32.rst > > Versatile Express > M: Peter Maydell <peter.maydell@linaro.org> > diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst > new file mode 100644 > index 0000000000..508b92cf86 > --- /dev/null > +++ b/docs/system/arm/stm32.rst > @@ -0,0 +1,66 @@ > +STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``) > +======================================================================================== > + > +The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by > +STMicroelectronics. > + > +.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html > + > +The STM32F1 series is based on ARM Cortex-M3 core. The following machines are > +based on this chip : > + > +- ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller > + > +The STM32F2 series is based on ARM Cortex-M3 core. The following machines are > +based on this chip : > + > +- ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller > + > +The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin > +compatible with STM32F2 series. The following machines are based on this chip : > + > +- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller > + > +There are many other STM32 series that are currently not supported by QEMU. > + > +Supported devices > +----------------- > + > + * ARM Cortex-M3, Cortex M4F > + * Analog to Digital Converter (ADC) > + * EXTI interrupt > + * Serial ports (USART) > + * SPI controller > + * System configuration (SYSCFG) > + * Timer controller (TIMER) > + > +Missing devices > +--------------- > + > + * Camera interface (DCMI) > + * Controller Area Network (CAN) > + * Cycle Redundancy Check (CRC) calculation unit > + * Digital to Analog Converter (DAC) > + * DMA controller > + * Ethernet controller > + * Flash Interface Unit > + * GPIO controller > + * I2C controller > + * Inter-Integrated Sound (I2S) controller > + * Power supply configuration (PWR) > + * Random Number Generator (RNG) > + * Real-Time Clock (RTC) controller > + * Reset and Clock Controller (RCC) > + * Secure Digital Input/Output (SDIO) interface > + * USB OTG > + * Watchdog controller (IWDG, WWDG) > + > +Boot options > +------------ > + > +The STM32 machines can be started using the ``-kernel`` option to load a > +firmware. Example: > + > +.. code-block:: bash > + > + $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin > diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst > index edd013c7bb..addd3d1613 100644 > --- a/docs/system/target-arm.rst > +++ b/docs/system/target-arm.rst > @@ -96,6 +96,7 @@ undocumented; you can get a complete list by running > arm/collie > arm/sx1 > arm/stellaris > + arm/stm32 > arm/virt > arm/xlnx-versal-virt > > -- > 2.25.1 >
On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss <erdnaxe@crans.org> wrote: > > New mini-kernel test for STM32VLDISCOVERY USART1. > > Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c > index d40adddafa..96849cec91 100644 > --- a/tests/qtest/boot-serial-test.c > +++ b/tests/qtest/boot-serial-test.c > @@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] = { > 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */ > }; > > +static const uint8_t kernel_stm32vldiscovery[] = { > + 0x00, 0x00, 0x00, 0x00, /* Stack top address */ > + 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */ > + 0x00, 0x00, 0x00, 0x00, /* NMI */ > + 0x00, 0x00, 0x00, 0x00, /* Hard fault */ > + 0x00, 0x00, 0x00, 0x00, /* Memory management fault */ > + 0x00, 0x00, 0x00, 0x00, /* Bus fault */ > + 0x00, 0x00, 0x00, 0x00, /* Usage fault */ > + 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */ > + 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */ > + 0x1a, 0x68, /* ldr r2, [r3] */ > + 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x1a, 0x68, /* ldr r2, [r3] */ > + 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */ > + 0x45, 0x22, /* movs r2, #69 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */ > + 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */ > + 0x54, 0x22, /* movs r2, 'T' */ > + 0x1a, 0x60, /* str r2, [r3] */ > + 0xfe, 0xe7, /* b . */ > + 0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */ > + 0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */ > + 0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */ > + 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */ > + 0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */ > +}; > + > typedef struct testdef { > const char *arch; /* Target architecture */ > const char *machine; /* Name of the machine */ > @@ -144,6 +179,8 @@ static testdef_t tests[] = { > { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64), > kernel_aarch64 }, > { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, > + { "arm", "stm32vldiscovery", "", "T", > + sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery }, > > { NULL } > }; > -- > 2.25.1 >
Cc'ing Joaquín
On 6/17/21 6:56 PM, Alexandre Iooss wrote:
> This patch series adds the STM32VLDISCOVERY Machine to QEMU
>
> Information on the board is available at:
> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>
> v3:
> - Add test for STM32VLDISCOVERY USART1
>
> v2:
> - Add documentation of STM32 boards
> - Fixed number of interrupts
> - Fixed Cortex-M3 name
>
> Alexandre Iooss (4):
> stm32f100: Add the stm32f100 SoC
> stm32vldiscovery: Add the STM32VLDISCOVERY Machine
> docs/system: arm: Add stm32 boards description
> tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
>
> MAINTAINERS | 13 ++
> default-configs/devices/arm-softmmu.mak | 1 +
> docs/system/arm/stm32.rst | 66 +++++++++
> docs/system/target-arm.rst | 1 +
> hw/arm/Kconfig | 10 ++
> hw/arm/meson.build | 2 +
> hw/arm/stm32f100_soc.c | 182 ++++++++++++++++++++++++
> hw/arm/stm32vldiscovery.c | 66 +++++++++
> include/hw/arm/stm32f100_soc.h | 57 ++++++++
> tests/qtest/boot-serial-test.c | 37 +++++
> 10 files changed, 435 insertions(+)
> create mode 100644 docs/system/arm/stm32.rst
> create mode 100644 hw/arm/stm32f100_soc.c
> create mode 100644 hw/arm/stm32vldiscovery.c
> create mode 100644 include/hw/arm/stm32f100_soc.h
>
On Thu, 17 Jun 2021 at 17:56, Alexandre Iooss <erdnaxe@crans.org> wrote:
>
> This patch series adds the STM32VLDISCOVERY Machine to QEMU
>
> Information on the board is available at:
> https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
>
> v3:
> - Add test for STM32VLDISCOVERY USART1
>
> v2:
> - Add documentation of STM32 boards
> - Fixed number of interrupts
> - Fixed Cortex-M3 name
>
> Alexandre Iooss (4):
> stm32f100: Add the stm32f100 SoC
> stm32vldiscovery: Add the STM32VLDISCOVERY Machine
> docs/system: arm: Add stm32 boards description
> tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
Oops, nearly lost this patchset in the pile somehow.
Applied to target-arm.next, thanks, since Alistair has
kindly reviewed it all.
-- PMM