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From: Alistair Francis <alistair23@gmail.com>
To: Alexandre Iooss <erdnaxe@crans.org>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"open list : STM32VLDISCOVERY" <qemu-arm@nongnu.org>,
	"open list : All patches CC here" <qemu-devel@nongnu.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [PATCH v3 1/4] stm32f100: Add the stm32f100 SoC
Date: Fri, 18 Jun 2021 11:27:50 +1000	[thread overview]
Message-ID: <CAKmqyKOrBEYQS2qzhzvsX7ESUtk-VmT1fvnZFjjm54W2x7KUHA@mail.gmail.com> (raw)
In-Reply-To: <20210617165647.2575955-2-erdnaxe@crans.org>

On Fri, Jun 18, 2021 at 2:56 AM Alexandre Iooss <erdnaxe@crans.org> wrote:
>
> This SoC is similar to stm32f205 SoC.
> This will be used by the STM32VLDISCOVERY to create a machine.
>
> Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>

Please keep any Reviewed by tags for a patch between versions if you
don't make large changes.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  MAINTAINERS                    |   6 ++
>  hw/arm/Kconfig                 |   6 ++
>  hw/arm/meson.build             |   1 +
>  hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
>  include/hw/arm/stm32f100_soc.h |  57 +++++++++++
>  5 files changed, 252 insertions(+)
>  create mode 100644 hw/arm/stm32f100_soc.c
>  create mode 100644 include/hw/arm/stm32f100_soc.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7d9cd29042..62dfa31800 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -946,6 +946,12 @@ L: qemu-arm@nongnu.org
>  S: Maintained
>  F: hw/arm/virt-acpi-build.c
>
> +STM32F100
> +M: Alexandre Iooss <erdnaxe@crans.org>
> +L: qemu-arm@nongnu.org
> +S: Maintained
> +F: hw/arm/stm32f100_soc.c
> +
>  STM32F205
>  M: Alistair Francis <alistair@alistair23.me>
>  M: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 67723d9ea6..0bc3ee3e91 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -326,6 +326,12 @@ config RASPI
>      select SDHCI
>      select USB_DWC2
>
> +config STM32F100_SOC
> +    bool
> +    select ARM_V7M
> +    select STM32F2XX_USART
> +    select STM32F2XX_SPI
> +
>  config STM32F205_SOC
>      bool
>      select ARM_V7M
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index be39117b9b..0e637e6a9e 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
>  arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
>  arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
>  arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
> +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
>  arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
>  arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
>  arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> new file mode 100644
> index 0000000000..0c4a5c6645
> --- /dev/null
> +++ b/hw/arm/stm32f100_soc.c
> @@ -0,0 +1,182 @@
> +/*
> + * STM32F100 SoC
> + *
> + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/module.h"
> +#include "hw/arm/boot.h"
> +#include "exec/address-spaces.h"
> +#include "hw/arm/stm32f100_soc.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/misc/unimp.h"
> +#include "sysemu/sysemu.h"
> +
> +/* stm32f100_soc implementation is derived from stm32f205_soc */
> +
> +static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
> +    0x40004800 };
> +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
> +
> +static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
> +static const int spi_irq[STM_NUM_SPIS] = {35, 36};
> +
> +static void stm32f100_soc_initfn(Object *obj)
> +{
> +    STM32F100State *s = STM32F100_SOC(obj);
> +    int i;
> +
> +    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
> +
> +    for (i = 0; i < STM_NUM_USARTS; i++) {
> +        object_initialize_child(obj, "usart[*]", &s->usart[i],
> +                                TYPE_STM32F2XX_USART);
> +    }
> +
> +    for (i = 0; i < STM_NUM_SPIS; i++) {
> +        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
> +    }
> +}
> +
> +static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> +    STM32F100State *s = STM32F100_SOC(dev_soc);
> +    DeviceState *dev, *armv7m;
> +    SysBusDevice *busdev;
> +    int i;
> +
> +    MemoryRegion *system_memory = get_system_memory();
> +    MemoryRegion *sram = g_new(MemoryRegion, 1);
> +    MemoryRegion *flash = g_new(MemoryRegion, 1);
> +    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
> +
> +    /*
> +     * Init flash region
> +     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> +     */
> +    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
> +                           FLASH_SIZE, &error_fatal);
> +    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> +                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
> +    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> +    memory_region_add_subregion(system_memory, 0, flash_alias);
> +
> +    /* Init SRAM region */
> +    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
> +                           &error_fatal);
> +    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> +
> +    /* Init ARMv7m */
> +    armv7m = DEVICE(&s->armv7m);
> +    qdev_prop_set_uint32(armv7m, "num-irq", 61);
> +    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> +    qdev_prop_set_bit(armv7m, "enable-bitband", true);
> +    object_property_set_link(OBJECT(&s->armv7m), "memory",
> +                             OBJECT(get_system_memory()), &error_abort);
> +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> +        return;
> +    }
> +
> +    /* Attach UART (uses USART registers) and USART controllers */
> +    for (i = 0; i < STM_NUM_USARTS; i++) {
> +        dev = DEVICE(&(s->usart[i]));
> +        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
> +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
> +            return;
> +        }
> +        busdev = SYS_BUS_DEVICE(dev);
> +        sysbus_mmio_map(busdev, 0, usart_addr[i]);
> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
> +    }
> +
> +    /* SPI 1 and 2 */
> +    for (i = 0; i < STM_NUM_SPIS; i++) {
> +        dev = DEVICE(&(s->spi[i]));
> +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
> +            return;
> +        }
> +        busdev = SYS_BUS_DEVICE(dev);
> +        sysbus_mmio_map(busdev, 0, spi_addr[i]);
> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
> +    }
> +
> +    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
> +    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
> +    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
> +    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
> +    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
> +    create_unimplemented_device("RTC",       0x40002800, 0x400);
> +    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
> +    create_unimplemented_device("IWDG",      0x40003000, 0x400);
> +    create_unimplemented_device("I2C1",      0x40005400, 0x400);
> +    create_unimplemented_device("I2C2",      0x40005800, 0x400);
> +    create_unimplemented_device("BKP",       0x40006C00, 0x400);
> +    create_unimplemented_device("PWR",       0x40007000, 0x400);
> +    create_unimplemented_device("DAC",       0x40007400, 0x400);
> +    create_unimplemented_device("CEC",       0x40007800, 0x400);
> +    create_unimplemented_device("AFIO",      0x40010000, 0x400);
> +    create_unimplemented_device("EXTI",      0x40010400, 0x400);
> +    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
> +    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
> +    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
> +    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
> +    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
> +    create_unimplemented_device("ADC1",      0x40012400, 0x400);
> +    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
> +    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
> +    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
> +    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
> +    create_unimplemented_device("DMA",       0x40020000, 0x400);
> +    create_unimplemented_device("RCC",       0x40021000, 0x400);
> +    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
> +    create_unimplemented_device("CRC",       0x40023000, 0x400);
> +}
> +
> +static Property stm32f100_soc_properties[] = {
> +    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +    dc->realize = stm32f100_soc_realize;
> +    device_class_set_props(dc, stm32f100_soc_properties);
> +}
> +
> +static const TypeInfo stm32f100_soc_info = {
> +    .name          = TYPE_STM32F100_SOC,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(STM32F100State),
> +    .instance_init = stm32f100_soc_initfn,
> +    .class_init    = stm32f100_soc_class_init,
> +};
> +
> +static void stm32f100_soc_types(void)
> +{
> +    type_register_static(&stm32f100_soc_info);
> +}
> +
> +type_init(stm32f100_soc_types)
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> new file mode 100644
> index 0000000000..71bffcf4fd
> --- /dev/null
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -0,0 +1,57 @@
> +/*
> + * STM32F100 SoC
> + *
> + * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_ARM_STM32F100_SOC_H
> +#define HW_ARM_STM32F100_SOC_H
> +
> +#include "hw/char/stm32f2xx_usart.h"
> +#include "hw/ssi/stm32f2xx_spi.h"
> +#include "hw/arm/armv7m.h"
> +#include "qom/object.h"
> +
> +#define TYPE_STM32F100_SOC "stm32f100-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
> +
> +#define STM_NUM_USARTS 3
> +#define STM_NUM_SPIS 2
> +
> +#define FLASH_BASE_ADDRESS 0x08000000
> +#define FLASH_SIZE (128 * 1024)
> +#define SRAM_BASE_ADDRESS 0x20000000
> +#define SRAM_SIZE (8 * 1024)
> +
> +struct STM32F100State {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    char *cpu_type;
> +
> +    ARMv7MState armv7m;
> +
> +    STM32F2XXUsartState usart[STM_NUM_USARTS];
> +    STM32F2XXSPIState spi[STM_NUM_SPIS];
> +};
> +
> +#endif
> --
> 2.25.1
>


  reply	other threads:[~2021-06-18  1:29 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-17 16:56 [PATCH v3 0/4] STM32VLDISCOVERY Machine Model Alexandre Iooss
2021-06-17 16:56 ` [PATCH v3 1/4] stm32f100: Add the stm32f100 SoC Alexandre Iooss
2021-06-18  1:27   ` Alistair Francis [this message]
2021-06-17 16:56 ` [PATCH v3 2/4] stm32vldiscovery: Add the STM32VLDISCOVERY Machine Alexandre Iooss
2021-06-18  1:28   ` Alistair Francis
2021-06-17 16:56 ` [PATCH v3 3/4] docs/system: arm: Add stm32 boards description Alexandre Iooss
2021-06-18  1:28   ` Alistair Francis
2021-06-17 16:56 ` [PATCH v3 4/4] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase Alexandre Iooss
2021-06-17 19:51   ` Thomas Huth
2021-06-18  1:32   ` Alistair Francis
2021-06-19 15:53 ` [PATCH v3 0/4] STM32VLDISCOVERY Machine Model Philippe Mathieu-Daudé
2021-07-05 13:00 ` Peter Maydell

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