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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::12c; envelope-from=alistair23@gmail.com; helo=mail-il1-x12c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Frank Chang , "qemu-devel@nongnu.org Developers" , Alistair Francis , Fabien Portas , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , liuzhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Oct 17, 2021 at 3:29 AM Richard Henderson wrote: > > The count zeros instructions require a separate implementation > for RV32 when TARGET_LONG_BITS == 64. > > Reviewed-by: LIU Zhiwei > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c | 16 ++++++++++++ > target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++------------- > 2 files changed, 32 insertions(+), 17 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8f5f39d143..7286791c0f 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -511,6 +511,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, > return true; > } > > +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, > + void (*f_tl)(TCGv, TCGv), > + void (*f_32)(TCGv, TCGv)) > +{ > + int olen = get_olen(ctx); > + > + if (olen != TARGET_LONG_BITS) { > + if (olen == 32) { > + f_tl = f_32; > + } else { > + g_assert_not_reached(); > + } > + } > + return gen_unary(ctx, a, ext, f_tl); > +} > + > static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > { > DisasContext *ctx = container_of(dcbase, DisasContext, base); > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index c62eea433a..0c2120428d 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1) > tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); > } > > +static void gen_clzw(TCGv ret, TCGv arg1) > +{ > + TCGv t = tcg_temp_new(); > + tcg_gen_shli_tl(t, arg1, 32); > + tcg_gen_clzi_tl(ret, t, 32); > + tcg_temp_free(t); > +} > + > static bool trans_clz(DisasContext *ctx, arg_clz *a) > { > REQUIRE_ZBB(ctx); > - return gen_unary(ctx, a, EXT_ZERO, gen_clz); > + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); > } > > static void gen_ctz(TCGv ret, TCGv arg1) > @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1) > tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); > } > > +static void gen_ctzw(TCGv ret, TCGv arg1) > +{ > + tcg_gen_ctzi_tl(ret, arg1, 32); > +} > + > static bool trans_ctz(DisasContext *ctx, arg_ctz *a) > { > REQUIRE_ZBB(ctx); > - return gen_unary(ctx, a, EXT_ZERO, gen_ctz); > + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw); > } > > static bool trans_cpop(DisasContext *ctx, arg_cpop *a) > @@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) > return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); > } > > -static void gen_clzw(TCGv ret, TCGv arg1) > -{ > - TCGv t = tcg_temp_new(); > - tcg_gen_shli_tl(t, arg1, 32); > - tcg_gen_clzi_tl(ret, t, 32); > - tcg_temp_free(t); > -} > - > static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > { > REQUIRE_64BIT(ctx); > @@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > return gen_unary(ctx, a, EXT_NONE, gen_clzw); > } > > -static void gen_ctzw(TCGv ret, TCGv arg1) > -{ > - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); > - tcg_gen_ctzi_tl(ret, ret, 64); > -} > - > static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZBB(ctx); > - return gen_unary(ctx, a, EXT_NONE, gen_ctzw); > + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); > } > > static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) > -- > 2.25.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mcKPm-0006kQ-Sv for mharc-qemu-riscv@gnu.org; Mon, 18 Oct 2021 00:38:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mcKPl-0006id-EP; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::12c; envelope-from=alistair23@gmail.com; helo=mail-il1-x12c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 04:38:21 -0000 On Sun, Oct 17, 2021 at 3:29 AM Richard Henderson wrote: > > The count zeros instructions require a separate implementation > for RV32 when TARGET_LONG_BITS == 64. > > Reviewed-by: LIU Zhiwei > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c | 16 ++++++++++++ > target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++------------- > 2 files changed, 32 insertions(+), 17 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8f5f39d143..7286791c0f 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -511,6 +511,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, > return true; > } > > +static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, > + void (*f_tl)(TCGv, TCGv), > + void (*f_32)(TCGv, TCGv)) > +{ > + int olen = get_olen(ctx); > + > + if (olen != TARGET_LONG_BITS) { > + if (olen == 32) { > + f_tl = f_32; > + } else { > + g_assert_not_reached(); > + } > + } > + return gen_unary(ctx, a, ext, f_tl); > +} > + > static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) > { > DisasContext *ctx = container_of(dcbase, DisasContext, base); > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index c62eea433a..0c2120428d 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1) > tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); > } > > +static void gen_clzw(TCGv ret, TCGv arg1) > +{ > + TCGv t = tcg_temp_new(); > + tcg_gen_shli_tl(t, arg1, 32); > + tcg_gen_clzi_tl(ret, t, 32); > + tcg_temp_free(t); > +} > + > static bool trans_clz(DisasContext *ctx, arg_clz *a) > { > REQUIRE_ZBB(ctx); > - return gen_unary(ctx, a, EXT_ZERO, gen_clz); > + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); > } > > static void gen_ctz(TCGv ret, TCGv arg1) > @@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1) > tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); > } > > +static void gen_ctzw(TCGv ret, TCGv arg1) > +{ > + tcg_gen_ctzi_tl(ret, arg1, 32); > +} > + > static bool trans_ctz(DisasContext *ctx, arg_ctz *a) > { > REQUIRE_ZBB(ctx); > - return gen_unary(ctx, a, EXT_ZERO, gen_ctz); > + return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw); > } > > static bool trans_cpop(DisasContext *ctx, arg_cpop *a) > @@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) > return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); > } > > -static void gen_clzw(TCGv ret, TCGv arg1) > -{ > - TCGv t = tcg_temp_new(); > - tcg_gen_shli_tl(t, arg1, 32); > - tcg_gen_clzi_tl(ret, t, 32); > - tcg_temp_free(t); > -} > - > static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > { > REQUIRE_64BIT(ctx); > @@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a) > return gen_unary(ctx, a, EXT_NONE, gen_clzw); > } > > -static void gen_ctzw(TCGv ret, TCGv arg1) > -{ > - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); > - tcg_gen_ctzi_tl(ret, ret, 64); > -} > - > static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZBB(ctx); > - return gen_unary(ctx, a, EXT_NONE, gen_ctzw); > + return gen_unary(ctx, a, EXT_ZERO, gen_ctzw); > } > > static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) > -- > 2.25.1 > >