From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fFmjG-000833-8S for qemu-devel@nongnu.org; Mon, 07 May 2018 16:27:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fFmjF-0001HJ-6Q for qemu-devel@nongnu.org; Mon, 07 May 2018 16:27:26 -0400 Received: from mail-lf0-x229.google.com ([2a00:1450:4010:c07::229]:38118) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fFmjE-0001Fv-Vx for qemu-devel@nongnu.org; Mon, 07 May 2018 16:27:25 -0400 Received: by mail-lf0-x229.google.com with SMTP id f18-v6so16901582lfc.5 for ; Mon, 07 May 2018 13:27:24 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <107c154303a7f08c452199df250c274f40d274ec.1525464177.git.alistair.francis@wdc.com> From: Alistair Francis Date: Mon, 7 May 2018 13:26:52 -0700 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v1 1/4] hw/riscv/sifive_u: Create a U54 SoC object List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Clark Cc: Alistair Francis , QEMU Developers , Palmer Dabbelt On Fri, May 4, 2018 at 3:55 PM, Michael Clark wrote: > > > On Sat, May 5, 2018 at 8:12 AM, Alistair Francis > wrote: >> >> Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. >> >> We leave the SoC, RAM, device tree and reset/fdt loading as part of the >> machine. All the other device creation has been moved to the SoC. > > > There is a tiny problem that we will have to resolve with renaming, > otherwise we will end up with lots of SOCs that are the essentially same > with a different CPU. > > There is an intention to add a HiFive1 and HiFiveU board in the future > however we were very explicit in renaming sifive_e300 and sifive_u500 to > sifive_e and sifive_u. > > If you read the code more closely you'll notice that we instantiate the > sifive_u board with a U34 if 32-bit and a U54 if 64-bit. > > #if defined(TARGET_RISCV32) > #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > #elif defined(TARGET_RISCV64) > #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > #endif > > The rationale is that sifive_e and sifive_u can eventually be customized to > represent different configurations of SiFive Core IP. We won't want to end > up hardcoding specific models in sifive_e or sifive_u > > SiFive have been talking internally about having sifive_e and sifive_u > reconfigurable, possibly even to the extend where we can configure with a > memory map. This is somewhat consistent with what SiFive do internally as > the FE310 and FU540 are configurations generated by a core generator. > > Now comes the question of whether its the right time to add a 'hifive1' or > 'hifiveu' machine. I don't think it is immediately necessary. The thought > being that we would be able to give a configuration string of file to > sifive_u e.g. "e51,u54,u54,u54". There is a different between the U54 and > the U54-MC which has an E51 core for management tasks. The PLIC has already > been written with this in mind, and is re-configurable to support the U54-MC > memory layout. Aren't the E51, U54, U54-MC, etc. all different SoCs? So doesn't it make sense to break out the SoCs and then in future the user can specify the SoC for the machine/board when they start QEMU? Alistair > > In anycase. The change is simply to use sifive_u_soc or sifive_u without the > 54 (given it configures with a U34 in 32-bit like the sifive_e configures > with an E51 in 64-bit mode, both valid configurations) >