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Tue, 10 May 2022 02:59:02 -0700 (PDT) MIME-Version: 1.0 References: <165156202959.27941.9731161369415852149-0@git.sr.ht> <165156202959.27941.9731161369415852149-12@git.sr.ht> In-Reply-To: <165156202959.27941.9731161369415852149-12@git.sr.ht> From: Alistair Francis Date: Tue, 10 May 2022 11:58:36 +0200 Message-ID: Subject: Re: [PATCH qemu v14 12/15] target/riscv: rvv: Add tail agnostic for vector reduction instructions To: "~eopxd" Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , WeiWei Li , eop Chen Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d33; envelope-from=alistair23@gmail.com; helo=mail-io1-xd33.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, May 3, 2022 at 9:30 AM ~eopxd wrote: > > From: eopXD > > Signed-off-by: eop Chen > Reviewed-by: Frank Chang > Reviewed-by: Weiwei Li Acked-by: Alistair Francis Alistair > --- > target/riscv/vector_helper.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index f67ec1f249..a319cda969 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4537,6 +4537,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > { \ > uint32_t vm = vext_vm(desc); \ > uint32_t vl = env->vl; \ > + uint32_t esz = sizeof(TD); \ > + uint32_t vlenb = simd_maxsz(desc); \ > + uint32_t vta = vext_vta(desc); \ > uint32_t i; \ > TD s1 = *((TD *)vs1 + HD(0)); \ > \ > @@ -4549,6 +4552,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > } \ > *((TD *)vd + HD(0)) = s1; \ > env->vstart = 0; \ > + /* set tail elements to 1s */ \ > + vext_set_elems_1s(vd, vta, esz, vlenb); \ > } > > /* vd[0] = sum(vs1[0], vs2[*]) */ > @@ -4618,6 +4623,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > { \ > uint32_t vm = vext_vm(desc); \ > uint32_t vl = env->vl; \ > + uint32_t esz = sizeof(TD); \ > + uint32_t vlenb = simd_maxsz(desc); \ > + uint32_t vta = vext_vta(desc); \ > uint32_t i; \ > TD s1 = *((TD *)vs1 + HD(0)); \ > \ > @@ -4630,6 +4638,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > } \ > *((TD *)vd + HD(0)) = s1; \ > env->vstart = 0; \ > + /* set tail elements to 1s */ \ > + vext_set_elems_1s(vd, vta, esz, vlenb); \ > } > > /* Unordered sum */ > @@ -4654,6 +4664,9 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, > { > uint32_t vm = vext_vm(desc); > uint32_t vl = env->vl; > + uint32_t esz = sizeof(uint32_t); > + uint32_t vlenb = simd_maxsz(desc); > + uint32_t vta = vext_vta(desc); > uint32_t i; > uint32_t s1 = *((uint32_t *)vs1 + H4(0)); > > @@ -4667,6 +4680,8 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, > } > *((uint32_t *)vd + H4(0)) = s1; > env->vstart = 0; > + /* set tail elements to 1s */ > + vext_set_elems_1s(vd, vta, esz, vlenb); > } > > void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, > @@ -4674,6 +4689,9 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, > { > uint32_t vm = vext_vm(desc); > uint32_t vl = env->vl; > + uint32_t esz = sizeof(uint64_t); > + uint32_t vlenb = simd_maxsz(desc); > + uint32_t vta = vext_vta(desc); > uint32_t i; > uint64_t s1 = *((uint64_t *)vs1); > > @@ -4687,6 +4705,8 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, > } > *((uint64_t *)vd) = s1; > env->vstart = 0; > + /* set tail elements to 1s */ > + vext_set_elems_1s(vd, vta, esz, vlenb); > } > > /* > -- > 2.34.2 > >