From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:34705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gm3zi-0002Am-0o for qemu-devel@nongnu.org; Tue, 22 Jan 2019 16:54:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gm3ze-0003se-Rh for qemu-devel@nongnu.org; Tue, 22 Jan 2019 16:54:05 -0500 MIME-Version: 1.0 References: <20181228220841.4896-1-jimw@sifive.com> In-Reply-To: <20181228220841.4896-1-jimw@sifive.com> From: Alistair Francis Date: Tue, 22 Jan 2019 13:53:30 -0800 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jim Wilson Cc: "qemu-devel@nongnu.org Developers" , qemu-riscv@nongnu.org On Fri, Dec 28, 2018 at 2:20 PM Jim Wilson wrote: > > Signed-off-by: Jim Wilson Acked-by: Alistair Francis Alistair > --- > configure | 1 + > gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++ > gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++ > gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++ > 4 files changed, 346 insertions(+) > create mode 100644 gdb-xml/riscv-64bit-cpu.xml > create mode 100644 gdb-xml/riscv-64bit-csr.xml > create mode 100644 gdb-xml/riscv-64bit-fpu.xml > > diff --git a/configure b/configure > index 4e05eed..00b7495 100755 > --- a/configure > +++ b/configure > @@ -7215,6 +7215,7 @@ case "$target_name" in > TARGET_BASE_ARCH=riscv > TARGET_ABI_DIR=riscv > mttcg=yes > + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" > target_compiler=$cross_cc_riscv64 > ;; > sh4|sh4eb) > diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml > new file mode 100644 > index 0000000..f37d7f3 > --- /dev/null > +++ b/gdb-xml/riscv-64bit-cpu.xml > @@ -0,0 +1,43 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml > new file mode 100644 > index 0000000..a3de834 > --- /dev/null > +++ b/gdb-xml/riscv-64bit-csr.xml > @@ -0,0 +1,250 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml > new file mode 100644 > index 0000000..fb24b72 > --- /dev/null > +++ b/gdb-xml/riscv-64bit-fpu.xml > @@ -0,0 +1,52 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > -- > 2.7.4 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1gm3zu-0002Tq-Pw for mharc-qemu-riscv@gnu.org; Tue, 22 Jan 2019 16:54:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gm3zr-0002Pc-5r for qemu-riscv@nongnu.org; Tue, 22 Jan 2019 16:54:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gm3zm-000483-As for qemu-riscv@nongnu.org; Tue, 22 Jan 2019 16:54:12 -0500 Received: from mail-lf1-x144.google.com ([2a00:1450:4864:20::144]:44243) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gm3ze-0003nH-4m; Tue, 22 Jan 2019 16:54:02 -0500 Received: by mail-lf1-x144.google.com with SMTP id z13so38076lfe.11; Tue, 22 Jan 2019 13:53:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6rCLls5viGRppw4bc/3ZNXt8DIUDh41yvn6qTro+QGs=; b=e0JjZmUt4RmHeNOoq9E26I92739hCpQPHb7xPfcZhkqO3bYVGCSNbX3mKkmiSdcRlR SGokBwHXvd9KlrMJSRVMndHmqnhCU2eUNfcD9ocMQ6Be2YrJDQEb0kWDaypITHGVYQP2 XeWe8b61LShlAFBVkVo5PtqWGGM9n2QVpZXDsUSua9NegDHkElD9MQAoLThzhxJc0zIB bmhlETOo/aU8bmbmdLK/uvnYRISjKKPzi4WcJs9/hYK0hskTxKQt7FG24a+2dB4u4Qlw D754Fszk4+IRDKdauTB/ZEI/ABjU1bQ1u4FHxvE73CJEnCVpklkrXJViZ5E3ybMR8mzS l4EQ== X-Google-DKIM-Signature: v=1; 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X-Received-From: 2a00:1450:4864:20::144 Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files. X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2019 21:54:17 -0000 On Fri, Dec 28, 2018 at 2:20 PM Jim Wilson wrote: > > Signed-off-by: Jim Wilson Acked-by: Alistair Francis Alistair > --- > configure | 1 + > gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++ > gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++ > gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++ > 4 files changed, 346 insertions(+) > create mode 100644 gdb-xml/riscv-64bit-cpu.xml > create mode 100644 gdb-xml/riscv-64bit-csr.xml > create mode 100644 gdb-xml/riscv-64bit-fpu.xml > > diff --git a/configure b/configure > index 4e05eed..00b7495 100755 > --- a/configure > +++ b/configure > @@ -7215,6 +7215,7 @@ case "$target_name" in > TARGET_BASE_ARCH=riscv > TARGET_ABI_DIR=riscv > mttcg=yes > + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" > target_compiler=$cross_cc_riscv64 > ;; > sh4|sh4eb) > diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml > new file mode 100644 > index 0000000..f37d7f3 > --- /dev/null > +++ b/gdb-xml/riscv-64bit-cpu.xml > @@ -0,0 +1,43 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml > new file mode 100644 > index 0000000..a3de834 > --- /dev/null > +++ b/gdb-xml/riscv-64bit-csr.xml > @@ -0,0 +1,250 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml > new file mode 100644 > index 0000000..fb24b72 > --- /dev/null > +++ b/gdb-xml/riscv-64bit-fpu.xml > @@ -0,0 +1,52 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > -- > 2.7.4 > >