From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34940) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YcOWg-000462-QF for qemu-devel@nongnu.org; Sun, 29 Mar 2015 21:30:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YcOWg-0005dL-1m for qemu-devel@nongnu.org; Sun, 29 Mar 2015 21:30:02 -0400 Received: from mail-oi0-x22a.google.com ([2607:f8b0:4003:c06::22a]:36736) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YcOWf-0005cf-UN for qemu-devel@nongnu.org; Sun, 29 Mar 2015 21:30:02 -0400 Received: by oicf142 with SMTP id f142so106204748oic.3 for ; Sun, 29 Mar 2015 18:30:01 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Alistair Francis Date: Mon, 30 Mar 2015 11:29:31 +1000 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: Edgar Iglesias , Peter Maydell , zach.pfeffer@xilinx.com, Ryota Ozaki , "qemu-devel@nongnu.org Developers" , "michals@xilinx.com" On Mon, Mar 23, 2015 at 9:05 PM, Peter Crosthwaite wrote: > Connect the GPIO outputs from the individual CPUs for the timers to the > GIC. > > Signed-off-by: Peter Crosthwaite > --- > hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 9465185..29954f5 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -19,9 +19,17 @@ > > #define GIC_NUM_SPI_INTR 128 > > +#define ARM_PHYS_TIMER_PPI 30 > +#define ARM_VIRT_TIMER_PPI 27 > + > #define GIC_DIST_ADDR 0xf9010000 > #define GIC_CPU_ADDR 0xf9020000 Hey Peter, I'm wondering if the #define's should be in the header file? > > +static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) > +{ > + return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index; Should the 32 also be a #define? Everything else is. Thanks, Alistair > +} > + > static void xlnx_zynqmp_init(Object *obj) > { > XlnxZynqMPState *s = XLNX_ZYNQMP(obj); > @@ -60,11 +68,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR); > > for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { > + qemu_irq irq; > + > object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); > ERR_PROP_CHECK_RETURN(err, errp); > > sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, > qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); > + irq = qdev_get_gpio_in(DEVICE(&s->gic), > + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); > + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq); > + irq = qdev_get_gpio_in(DEVICE(&s->gic), > + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); > + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq); > } > } > > -- > 2.3.1.2.g90df61e.dirty > >