* [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
@ 2021-06-27 12:06 Bin Meng
2021-07-02 7:22 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: Bin Meng @ 2021-06-27 12:06 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
The following check:
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v2:
- rebase on qemu/master
target/riscv/csr.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fe5628fea6..62b968326c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-#endif
*val = riscv_cpu_get_fflags(env);
return RISCV_EXCP_NONE;
}
@@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
env->mstatus |= MSTATUS_FS;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
static RISCVException read_frm(CPURISCVState *env, int csrno,
target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-#endif
*val = env->frm;
return RISCV_EXCP_NONE;
}
@@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
static RISCVException read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
if (vs(env, csrno) >= 0) {
@@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
2021-06-27 12:06 [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng
@ 2021-07-02 7:22 ` Alistair Francis
0 siblings, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-07-02 7:22 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers
On Sun, Jun 27, 2021 at 10:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The following check:
>
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
>
> is redundant in fflags/frm/fcsr read/write routines, as the check was
> already done in fs().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> ---
>
> Changes in v2:
> - rebase on qemu/master
>
> target/riscv/csr.c | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fe5628fea6..62b968326c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
> static RISCVException read_fflags(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = riscv_cpu_get_fflags(env);
> return RISCV_EXCP_NONE;
> }
> @@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> @@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
> static RISCVException read_frm(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = env->frm;
> return RISCV_EXCP_NONE;
> }
> @@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> @@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
> static RISCVException read_fcsr(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> if (vs(env, csrno) >= 0) {
> @@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines
@ 2021-07-02 7:22 ` Alistair Francis
0 siblings, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-07-02 7:22 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V
On Sun, Jun 27, 2021 at 10:06 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The following check:
>
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> return -RISCV_EXCP_ILLEGAL_INST;
> }
>
> is redundant in fflags/frm/fcsr read/write routines, as the check was
> already done in fs().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> ---
>
> Changes in v2:
> - rebase on qemu/master
>
> target/riscv/csr.c | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fe5628fea6..62b968326c 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -215,11 +215,6 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
> static RISCVException read_fflags(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = riscv_cpu_get_fflags(env);
> return RISCV_EXCP_NONE;
> }
> @@ -228,9 +223,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> @@ -240,11 +232,6 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
> static RISCVException read_frm(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = env->frm;
> return RISCV_EXCP_NONE;
> }
> @@ -253,9 +240,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
> @@ -265,11 +249,6 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
> static RISCVException read_fcsr(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -#endif
> *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> if (vs(env, csrno) >= 0) {
> @@ -283,9 +262,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> - if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-07-02 7:23 UTC | newest]
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2021-06-27 12:06 [PATCH v2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng
2021-07-02 7:22 ` Alistair Francis
2021-07-02 7:22 ` Alistair Francis
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