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Tue, 14 Sep 2021 18:16:44 -0700 (PDT) MIME-Version: 1.0 References: <20210902112520.475901-1-anup.patel@wdc.com> <20210902112520.475901-18-anup.patel@wdc.com> In-Reply-To: <20210902112520.475901-18-anup.patel@wdc.com> From: Alistair Francis Date: Wed, 15 Sep 2021 11:16:18 +1000 Message-ID: Subject: Re: [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART To: Anup Patel Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=alistair23@gmail.com; helo=mail-il1-x131.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:RISC-V" , Sagar Karandikar , Anup Patel , "qemu-devel@nongnu.org Developers" , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Sep 2, 2021 at 10:03 PM Anup Patel wrote: > > We add "x-aia" command-line option for RISC-V HART using which > allows users to force enable CPU AIA CSRs without changing the > interrupt controller available in RISC-V machine. > > Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e0f4ae4224..9723d54eaf 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -452,6 +452,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > + if (cpu->cfg.aia) { > + riscv_set_feature(env, RISCV_FEATURE_AIA); > + } > + > set_resetvec(env, cpu->cfg.resetvec); > > /* If only XLEN is set for misa, then set misa from properties */ > @@ -672,6 +676,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), > > DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 16a4596433..cab9e90153 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -337,6 +337,7 @@ struct RISCVCPU { > bool mmu; > bool pmp; > bool epmp; > + bool aia; > uint64_t resetvec; > } cfg; > }; > -- > 2.25.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mQJXe-0001Vz-VZ for mharc-qemu-riscv@gnu.org; Tue, 14 Sep 2021 21:16:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQJXd-0001Tg-Ip; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=alistair23@gmail.com; helo=mail-il1-x131.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Sep 2021 01:16:49 -0000 On Thu, Sep 2, 2021 at 10:03 PM Anup Patel wrote: > > We add "x-aia" command-line option for RISC-V HART using which > allows users to force enable CPU AIA CSRs without changing the > interrupt controller available in RISC-V machine. > > Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e0f4ae4224..9723d54eaf 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -452,6 +452,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > + if (cpu->cfg.aia) { > + riscv_set_feature(env, RISCV_FEATURE_AIA); > + } > + > set_resetvec(env, cpu->cfg.resetvec); > > /* If only XLEN is set for misa, then set misa from properties */ > @@ -672,6 +676,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), > > DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 16a4596433..cab9e90153 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -337,6 +337,7 @@ struct RISCVCPU { > bool mmu; > bool pmp; > bool epmp; > + bool aia; > uint64_t resetvec; > } cfg; > }; > -- > 2.25.1 > >