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bh=n7d5Pcc0VNYj7xJiDh9xXCDiQUNA26uEPx/UGxLUN40=; b=legcRezb6VkJmeOuByvY1pdQj8deIpmOsHyMYBMyFDxLcFrWw1qsWZph8f7R2F9aHz Wu+kK92TtI2n40tI0Me0/13j7ea0KPcBWlyeNznEGb/cJy1wvkA3h4KzGg7qRa2s8qEm U2mmFFD3CHy6XMatOY5cK+JfzWImTIzStR3aH+FMs9XU7TpAl2u6nvp9djElZhYraxIl CV+dhYmFGAKWC/x/i+sa6wjVYCs0+bBuMkpM5dUSXSl5cRt8vofVOArW21ZdLXo2DUGg pb3W4zx0dkPPfDeRSQ5oW2AdHNFk2D+bTaPnB5rBrJJZtx9cKHROKJUdXgqIM6zIXXGC C5aw== X-Gm-Message-State: AOAM533odlccZhAG0jb0hr+tICHaxIzIb/7WFOSW/YRa8K7qQlx3H1IF lOjPjzQpNWgfnSVCu3QFCE7JpFoUuHbx/h9P+SE= X-Google-Smtp-Source: ABdhPJz0bHcyFH6loQKbB7SM4wJ2UxXqwZ4IQTDo24LsulLKqareNjVZld6J05qf/+twje9vI0eg82HjMRHuvoPSVkU= X-Received: by 2002:a92:d90f:: with SMTP id s15mr408088iln.227.1618440015373; Wed, 14 Apr 2021 15:40:15 -0700 (PDT) MIME-Version: 1.0 References: <20210412065246.1853-1-jiangyifei@huawei.com> <20210412065246.1853-5-jiangyifei@huawei.com> In-Reply-To: <20210412065246.1853-5-jiangyifei@huawei.com> From: Alistair Francis Date: Thu, 15 Apr 2021 08:39:49 +1000 Message-ID: Subject: Re: [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers To: Yifei Jiang Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Bin Meng , Sagar Karandikar , "open list:Overall" , libvir-list@redhat.com, Bastian Koppelmann , Anup Patel , yinyipeng , Alistair Francis , kvm-riscv@lists.infradead.org, Palmer Dabbelt , fanliang@huawei.com, "Wubin (H)" , Zhanghailiang Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Apr 12, 2021 at 4:58 PM Yifei Jiang wrote: > > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 149 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 0d924be33f..63485d7b65 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx) > return id; > } > > +#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ > + KVM_REG_RISCV_CORE_REG(name)) > + > +#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ > + KVM_REG_RISCV_CSR_REG(name)) > + > +#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) > + > +#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) > + > +static int kvm_riscv_get_regs_core(CPUState *cs) > +{ > + int ret = 0; > + int i; > + target_ulong reg; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); > + if (ret) { > + return ret; > + } > + env->pc = reg; > + > + for (i = 1; i < 32; i++) { > + __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); > + ret = kvm_get_one_reg(cs, id, ®); > + if (ret) { > + return ret; > + } > + env->gpr[i] = reg; > + } > + > + return ret; > +} > + > +static int kvm_riscv_get_regs_csr(CPUState *cs) > +{ > + int ret = 0; > + target_ulong reg; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®); > + if (ret) { > + return ret; > + } > + env->mstatus = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), ®); > + if (ret) { > + return ret; > + } > + env->mie = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), ®); > + if (ret) { > + return ret; > + } > + env->stvec = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®); > + if (ret) { > + return ret; > + } > + env->sscratch = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), ®); > + if (ret) { > + return ret; > + } > + env->sepc = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), ®); > + if (ret) { > + return ret; > + } > + env->scause = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), ®); > + if (ret) { > + return ret; > + } > + env->sbadaddr = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), ®); > + if (ret) { > + return ret; > + } > + env->mip = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), ®); > + if (ret) { > + return ret; > + } > + env->satp = reg; > + > + return ret; > +} > + > +static int kvm_riscv_get_regs_fp(CPUState *cs) > +{ > + int ret = 0; > + int i; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + if (riscv_has_ext(env, RVD)) { > + uint64_t reg; > + for (i = 0; i < 32; i++) { > + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); > + if (ret) { > + return ret; > + } > + env->fpr[i] = reg; > + } > + return ret; > + } > + > + if (riscv_has_ext(env, RVF)) { > + uint32_t reg; > + for (i = 0; i < 32; i++) { > + ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); > + if (ret) { > + return ret; > + } > + env->fpr[i] = reg; > + } > + return ret; > + } > + > + return ret; > +} > + > const KVMCapabilityInfo kvm_arch_required_capabilities[] = { > KVM_CAP_LAST_INFO > }; > > int kvm_arch_get_registers(CPUState *cs) > { > - return 0; > + int ret = 0; > + > + ret = kvm_riscv_get_regs_core(cs); > + if (ret) { > + return ret; > + } > + > + ret = kvm_riscv_get_regs_csr(cs); > + if (ret) { > + return ret; > + } > + > + ret = kvm_riscv_get_regs_fp(cs); > + if (ret) { > + return ret; > + } > + > + return ret; > } > > int kvm_arch_put_registers(CPUState *cs, int level) > -- > 2.19.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91BFFC433ED for ; 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Wed, 14 Apr 2021 15:40:15 -0700 (PDT) MIME-Version: 1.0 References: <20210412065246.1853-1-jiangyifei@huawei.com> <20210412065246.1853-5-jiangyifei@huawei.com> In-Reply-To: <20210412065246.1853-5-jiangyifei@huawei.com> From: Alistair Francis Date: Thu, 15 Apr 2021 08:39:49 +1000 Message-ID: Subject: Re: [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers To: Yifei Jiang Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::12c; envelope-from=alistair23@gmail.com; helo=mail-il1-x12c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm-riscv@lists.infradead.org, Anup Patel , "open list:RISC-V" , "open list:Overall" , Sagar Karandikar , libvir-list@redhat.com, Bastian Koppelmann , Bin Meng , "qemu-devel@nongnu.org Developers" , Alistair Francis , yinyipeng , Palmer Dabbelt , fanliang@huawei.com, "Wubin \(H\)" , Zhanghailiang Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Apr 12, 2021 at 4:58 PM Yifei Jiang wrote: > > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 149 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 0d924be33f..63485d7b65 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx) > return id; > } > > +#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ > + KVM_REG_RISCV_CORE_REG(name)) > + > +#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ > + KVM_REG_RISCV_CSR_REG(name)) > + > +#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) > + > +#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) > + > +static int kvm_riscv_get_regs_core(CPUState *cs) > +{ > + int ret = 0; > + int i; > + target_ulong reg; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); > + if (ret) { > + return ret; > + } > + env->pc = reg; > + > + for (i = 1; i < 32; i++) { > + __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); > + ret = kvm_get_one_reg(cs, id, ®); > + if (ret) { > + return ret; > + } > + env->gpr[i] = reg; > + } > + > + return ret; > +} > + > +static int kvm_riscv_get_regs_csr(CPUState *cs) > +{ > + int ret = 0; > + target_ulong reg; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®); > + if (ret) { > + return ret; > + } > + env->mstatus = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), ®); > + if (ret) { > + return ret; > + } > + env->mie = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), ®); > + if (ret) { > + return ret; > + } > + env->stvec = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®); > + if (ret) { > + return ret; > + } > + env->sscratch = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), ®); > + if (ret) { > + return ret; > + } > + env->sepc = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), ®); > + if (ret) { > + return ret; > + } > + env->scause = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), ®); > + if (ret) { > + return ret; > + } > + env->sbadaddr = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), ®); > + if (ret) { > + return ret; > + } > + env->mip = reg; > + > + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), ®); > + if (ret) { > + return ret; > + } > + env->satp = reg; > + > + return ret; > +} > + > +static int kvm_riscv_get_regs_fp(CPUState *cs) > +{ > + int ret = 0; > + int i; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + if (riscv_has_ext(env, RVD)) { > + uint64_t reg; > + for (i = 0; i < 32; i++) { > + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); > + if (ret) { > + return ret; > + } > + env->fpr[i] = reg; > + } > + return ret; > + } > + > + if (riscv_has_ext(env, RVF)) { > + uint32_t reg; > + for (i = 0; i < 32; i++) { > + ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); > + if (ret) { > + return ret; > + } > + env->fpr[i] = reg; > + } > + return ret; > + } > + > + return ret; > +} > + > const KVMCapabilityInfo kvm_arch_required_capabilities[] = { > KVM_CAP_LAST_INFO > }; > > int kvm_arch_get_registers(CPUState *cs) > { > - return 0; > + int ret = 0; > + > + ret = kvm_riscv_get_regs_core(cs); > + if (ret) { > + return ret; > + } > + > + ret = kvm_riscv_get_regs_csr(cs); > + if (ret) { > + return ret; > + } > + > + ret = kvm_riscv_get_regs_fp(cs); > + if (ret) { > + return ret; > + } > + > + return ret; > } > > int kvm_arch_put_registers(CPUState *cs, int level) > -- > 2.19.1 > >