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Tue, 10 May 2022 02:19:56 -0700 (PDT) MIME-Version: 1.0 References: <165156202959.27941.9731161369415852149-0@git.sr.ht> <165156202959.27941.9731161369415852149-7@git.sr.ht> In-Reply-To: <165156202959.27941.9731161369415852149-7@git.sr.ht> From: Alistair Francis Date: Tue, 10 May 2022 11:19:30 +0200 Message-ID: Subject: Re: [PATCH qemu v14 07/15] target/riscv: rvv: Add tail agnostic for vector integer shift instructions To: "~eopxd" Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , WeiWei Li , eop Chen Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, May 3, 2022 at 9:40 AM ~eopxd wrote: > > From: eopXD > > Signed-off-by: eop Chen > Reviewed-by: Frank Chang > Reviewed-by: Weiwei Li Acked-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 11 +++++++++++ > target/riscv/vector_helper.c | 11 +++++++++++ > 2 files changed, 22 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index d15858fc6f..430847b0f9 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -1858,6 +1858,16 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, > } > > if (a->vm && s->vl_eq_vlmax) { > + if (s->vta && s->lmul < 0) { > + /* > + * tail elements may pass vlmax when lmul < 0 > + * set tail elements to 1s > + */ > + uint32_t vlenb = s->cfg_ptr->vlen >> 3; > + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), > + vreg_ofs(s, a->rd), -1, > + vlenb, vlenb); > + } > TCGv_i32 src1 = tcg_temp_new_i32(); > > tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE)); > @@ -1916,6 +1926,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > \ > data = FIELD_DP32(data, VDATA, VM, a->vm); \ > data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ > + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ > tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ > vreg_ofs(s, a->rs1), \ > vreg_ofs(s, a->rs2), cpu_env, \ > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index e00f9353b9..c1ae2ea2f1 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -1273,6 +1273,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > { \ > uint32_t vm = vext_vm(desc); \ > uint32_t vl = env->vl; \ > + uint32_t esz = sizeof(TS1); \ > + uint32_t total_elems = vext_get_total_elems(env, desc, esz); \ > + uint32_t vta = vext_vta(desc); \ > uint32_t i; \ > \ > for (i = env->vstart; i < vl; i++) { \ > @@ -1284,6 +1287,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \ > } \ > env->vstart = 0; \ > + /* set tail elements to 1s */ \ > + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ > } > > GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7) > @@ -1308,6 +1313,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ > { \ > uint32_t vm = vext_vm(desc); \ > uint32_t vl = env->vl; \ > + uint32_t esz = sizeof(TD); \ > + uint32_t total_elems = \ > + vext_get_total_elems(env, desc, esz); \ > + uint32_t vta = vext_vta(desc); \ > uint32_t i; \ > \ > for (i = env->vstart; i < vl; i++) { \ > @@ -1318,6 +1327,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ > *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ > } \ > env->vstart = 0; \ > + /* set tail elements to 1s */ \ > + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);\ > } > > GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7) > -- > 2.34.2 > >