diff for duplicates of <CAKohpokLqrydV3b=innvOWrW9ijXtZwPKdT5Ew65cjMxsY2Mvw@mail.gmail.com>
diff --git a/a/1.txt b/N1/1.txt
index ca938d1..bc97500 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -47,7 +47,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cpu0: cpu at 0 {
compatible = "arm,cortex-a15";
reg = <0>;
next-level-cache = <&L2>;
@@ -60,7 +60,7 @@ cpus {
clock-latency = <61036>; /* two CLK32 periods */
};
- cpu1: cpu@1 {
+ cpu1: cpu at 1 {
compatible = "arm,cortex-a15";
reg = <1>;
next-level-cache = <&L2>;
@@ -73,7 +73,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cpu0: cpu at 0 {
compatible = "arm,cortex-a15";
reg = <0>;
next-level-cache = <&L2>;
@@ -86,7 +86,7 @@ cpus {
clock-latency = <61036>; /* two CLK32 periods */
};
- cpu1: cpu@1 {
+ cpu1: cpu at 1 {
compatible = "arm,cortex-a15";
reg = <1>;
next-level-cache = <&L2>;
@@ -107,7 +107,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu0: cpu@0 {
+ cpu0: cpu at 0 {
compatible = "arm,cortex-a15";
reg = <0>;
next-level-cache = <&L2>;
@@ -120,14 +120,14 @@ cpus {
clock-latency = <61036>; /* two CLK32 periods */
};
- cpu1: cpu@1 {
+ cpu1: cpu at 1 {
compatible = "arm,cortex-a15";
reg = <1>;
next-level-cache = <&L2>;
clock-master = <&cpu0>;
};
- cpu2: cpu@100 {
+ cpu2: cpu at 100 {
compatible = "arm,cortex-a7";
reg = <100>;
next-level-cache = <&L2>;
@@ -140,7 +140,7 @@ cpus {
clock-latency = <61036>; /* two CLK32 periods */
};
- cpu3: cpu@101 {
+ cpu3: cpu at 101 {
compatible = "arm,cortex-a7";
reg = <101>;
next-level-cache = <&L2>;
diff --git a/a/content_digest b/N1/content_digest
index 9e9b382..2589fc3 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -11,33 +11,16 @@
"ref\0CAOesGMhuNzVtUkaUjF+JjNgHcgf08WiM0DG-kzwtcyUxkK_zow\@mail.gmail.com\0"
]
[
- "From\0Viresh Kumar <viresh.kumar\@linaro.org>\0"
+ "From\0viresh.kumar\@linaro.org (Viresh Kumar)\0"
]
[
- "Subject\0Re: [RFC] cpufreq: Add bindings for CPU clock sharing topology\0"
+ "Subject\0[RFC] cpufreq: Add bindings for CPU clock sharing topology\0"
]
[
"Date\0Sat, 19 Jul 2014 20:16:36 +0530\0"
]
[
- "To\0Olof Johansson <olof\@lixom.net>\0"
-]
-[
- "Cc\0Rafael J. Wysocki <rjw\@rjwysocki.net>",
- " Mike Turquette <mike.turquette\@linaro.org>",
- " Rob Herring <rob.herring\@linaro.org>",
- " Grant Likely <grant.likely\@linaro.org>",
- " linaro-kernel\@lists.linaro.org <linaro-kernel\@lists.linaro.org>",
- " Nishanth Menon <nm\@ti.com>",
- " Sudeep Holla <Sudeep.Holla\@arm.com>",
- " Stephen Boyd <sboyd\@codeaurora.org>",
- " linux-arm-kernel\@lists.infradead.org <linux-arm-kernel\@lists.infradead.org>",
- " linux-pm\@vger.kernel.org <linux-pm\@vger.kernel.org>",
- " devicetree\@vger.kernel.org <devicetree\@vger.kernel.org>",
- " Santosh Shilimkar <santosh.shilimkar\@ti.com>",
- " Lorenzo Pieralisi <Lorenzo.Pieralisi\@arm.com>",
- " Arvind Chauhan <arvind.chauhan\@arm.com>",
- " Arnd Bergmann <arnd.bergmann\@linaro.org>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -95,7 +78,7 @@
" #address-cells = <1>;\n",
" #size-cells = <0>;\n",
"\n",
- " cpu0: cpu\@0 {\n",
+ " cpu0: cpu at 0 {\n",
" compatible = \"arm,cortex-a15\";\n",
" reg = <0>;\n",
" next-level-cache = <&L2>;\n",
@@ -108,7 +91,7 @@
" clock-latency = <61036>; /* two CLK32 periods */\n",
" };\n",
"\n",
- " cpu1: cpu\@1 {\n",
+ " cpu1: cpu at 1 {\n",
" compatible = \"arm,cortex-a15\";\n",
" reg = <1>;\n",
" next-level-cache = <&L2>;\n",
@@ -121,7 +104,7 @@
" #address-cells = <1>;\n",
" #size-cells = <0>;\n",
"\n",
- " cpu0: cpu\@0 {\n",
+ " cpu0: cpu at 0 {\n",
" compatible = \"arm,cortex-a15\";\n",
" reg = <0>;\n",
" next-level-cache = <&L2>;\n",
@@ -134,7 +117,7 @@
" clock-latency = <61036>; /* two CLK32 periods */\n",
" };\n",
"\n",
- " cpu1: cpu\@1 {\n",
+ " cpu1: cpu at 1 {\n",
" compatible = \"arm,cortex-a15\";\n",
" reg = <1>;\n",
" next-level-cache = <&L2>;\n",
@@ -155,7 +138,7 @@
" #address-cells = <1>;\n",
" #size-cells = <0>;\n",
"\n",
- " cpu0: cpu\@0 {\n",
+ " cpu0: cpu at 0 {\n",
" compatible = \"arm,cortex-a15\";\n",
" reg = <0>;\n",
" next-level-cache = <&L2>;\n",
@@ -168,14 +151,14 @@
" clock-latency = <61036>; /* two CLK32 periods */\n",
" };\n",
"\n",
- " cpu1: cpu\@1 {\n",
+ " cpu1: cpu at 1 {\n",
" compatible = \"arm,cortex-a15\";\n",
" reg = <1>;\n",
" next-level-cache = <&L2>;\n",
" clock-master = <&cpu0>;\n",
" };\n",
"\n",
- " cpu2: cpu\@100 {\n",
+ " cpu2: cpu at 100 {\n",
" compatible = \"arm,cortex-a7\";\n",
" reg = <100>;\n",
" next-level-cache = <&L2>;\n",
@@ -188,7 +171,7 @@
" clock-latency = <61036>; /* two CLK32 periods */\n",
" };\n",
"\n",
- " cpu3: cpu\@101 {\n",
+ " cpu3: cpu at 101 {\n",
" compatible = \"arm,cortex-a7\";\n",
" reg = <101>;\n",
" next-level-cache = <&L2>;\n",
@@ -197,4 +180,4 @@
"};"
]
-457bdd66bc64d41acda166c082b91b6b7e0d12fb16c63744be362b94708b6ad5
+921ce977fc60697e8f43fbe70812ca5a5f91fe0b8d7eec761eb28c9f6e429197
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