From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya2FC-0002Dd-U0 for qemu-devel@nongnu.org; Mon, 23 Mar 2015 09:18:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ya2FB-0003Py-RG for qemu-devel@nongnu.org; Mon, 23 Mar 2015 09:18:14 -0400 Received: from mail-oi0-x235.google.com ([2607:f8b0:4003:c06::235]:34569) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ya2FB-0003Pi-LK for qemu-devel@nongnu.org; Mon, 23 Mar 2015 09:18:13 -0400 Received: by oier21 with SMTP id r21so140100733oie.1 for ; Mon, 23 Mar 2015 06:18:12 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1fdb902f7111a5fa0971ca3c82ea886304053f4a.1427108387.git.peter.crosthwaite@xilinx.com> References: <1fdb902f7111a5fa0971ca3c82ea886304053f4a.1427108387.git.peter.crosthwaite@xilinx.com> From: Ryota Ozaki Date: Mon, 23 Mar 2015 22:17:51 +0900 Message-ID: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH target-arm v4 03/16] target-arm: cpu64: Add support for cortex-a53 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: edgar.iglesias@xilinx.com, Peter Maydell , zach.pfeffer@xilinx.com, "qemu-devel@nongnu.org Developers" , michals@xilinx.com, =?ISO-8859-1?Q?Alex_Benn=E9e?= Hi, On Mon, Mar 23, 2015 at 8:05 PM, Peter Crosthwaite wrote: > Similar to a53, but with different L1 I cache policy, phys addr size and ^^^ I guess a57 :) ozaki-r > different cache geometries. The cache sizes is implementation > configurable, but use these values (from Xilinx MPSoC) as a default > until cache size configurability is added. > > Reviewed-by: Alex Benn=E9e > Signed-off-by: Peter Crosthwaite > --- > Changed since v2: > Added dtb compatible string > > target-arm/cpu64.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c > index 3eb58c6..728d9a7 100644 > --- a/target-arm/cpu64.c > +++ b/target-arm/cpu64.c > @@ -149,6 +149,21 @@ static void aarch64_a57_initfn(Object *obj) > cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ > } > > +static void aarch64_a53_initfn(Object *obj) > +{ > + ARMCPU *cpu =3D ARM_CPU(obj); > + > + aarch64_axx_initfn(cpu); > + > + cpu->dtb_compatible =3D "arm,cortex-a53"; > + cpu->midr =3D 0x410fd034; > + cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ > + cpu->id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ > + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ > + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ > + cpu->ccsidr[2] =3D 0x707fe07a; /* 1024KB L2 cache */ > +} > + > #ifdef CONFIG_USER_ONLY > static void aarch64_any_initfn(Object *obj) > { > @@ -176,6 +191,7 @@ typedef struct ARMCPUInfo { > > static const ARMCPUInfo aarch64_cpus[] =3D { > { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, > + { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, > #ifdef CONFIG_USER_ONLY > { .name =3D "any", .initfn =3D aarch64_any_initfn }, > #endif > -- > 2.3.1.2.g90df61e.dirty >