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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Fri, 14 Dec 2018 17:40:51 +0100
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Subject: Re: [Qemu-devel] [PATCH v1 1/2] target/arm: kvm64 make guest debug
 AA32 break point aware
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To: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>, Mark Rutland <mark.rutland@arm.com>, Peter Maydell <peter.maydell@linaro.org>, qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, Omair Javaid <omair.javaid@linaro.org>

On Fri, 14 Dec 2018 at 17:26, Alex Benn=C3=A9e <alex.bennee@linaro.org> wro=
te:
>
>
> Richard Henderson <richard.henderson@linaro.org> writes:
>
> > On 12/13/18 8:55 AM, Alex Benn=C3=A9e wrote:
> >>
> >> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes:
> >>
> >>> Hi Alex,
> >>>
> >>> Thanks again for looking into this.
> >>>
> >>> On Thu, 13 Dec 2018 at 12:55, Alex Benn=C3=A9e <alex.bennee@linaro.or=
g> wrote:
> >> <snip>
> >>>
> >>>>
> >>>>  int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_break=
point *bp)
> >>>>  {
> >>>> +    CPUARMState *env =3D &ARM_CPU(cs)->env;
> >>>> +    int el =3D arm_current_el(env);
> >>>> +    bool is_aa64 =3D arm_el_is_aa64(env, el);
> >>>> +    const uint32_t *bpi =3D is_aa64 ? &brk_insn : &bkpt_insn;
> >>>> +
> >>>>      if (have_guest_debug) {
> >>>>          if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_i=
nsn, 4, 0) ||
> >>>> -            cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4=
, 1)) {
> >>>> +            cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)bpi, 4, 1)) =
{
> >>>
> >>> Should we be dealing with endianness here?
> >>>
> >> <snip>
> >>
> >> I don't think so - everything eventually ends up (ld|st)n_p which deal=
s
> >> with the endianness details.
> >
> > I think Ard is right.  You need to consider dynamic endianness with
> >
> >     bswap_code(arm_sctlr_b(env))
>
> *sigh* I guess. It of course still a heuristic that can break because we
> don't know if the system will have switched mode by the time it gets to
> the breakpoint.
>

Actually, I was referring to the QEMU/host side. Instruction encodings
are always little endian in ARMv7 and v8 (which is all KVM cares about
in any case), but I guess it is [theoretically?] possible that we are
running a BE QEMU?