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X-Received-From: 2607:f8b0:4864:20::241 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "thuth@redhat.com" , Sarah Harris , "richard.henderson@linaro.org" , "qemu-devel@nongnu.org" , "dovgaluk@ispras.ru" , "imammedo@redhat.com" , "philmd@redhat.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000005c3597059835c107 Content-Type: text/plain; charset="UTF-8" On Sunday, November 24, 2019, Michael Rolnik wrote: > This includes: > - CPU data structures > - object model classes and functions > - migration functions > - GDB hooks > > Co-developed-by: Michael Rolnik > Co-developed-by: Sarah Harris > Signed-off-by: Michael Rolnik > Signed-off-by: Sarah Harris > Signed-off-by: Michael Rolnik > Acked-by: Igor Mammedov > --- > target/avr/cpu-param.h | 37 +++ > target/avr/cpu-qom.h | 54 ++++ > target/avr/cpu.h | 253 ++++++++++++++++++ > target/avr/cpu.c | 576 +++++++++++++++++++++++++++++++++++++++++ > target/avr/gdbstub.c | 85 ++++++ > target/avr/machine.c | 121 +++++++++ > gdb-xml/avr-cpu.xml | 49 ++++ > 7 files changed, 1175 insertions(+) > create mode 100644 target/avr/cpu-param.h > create mode 100644 target/avr/cpu-qom.h > create mode 100644 target/avr/cpu.h > create mode 100644 target/avr/cpu.c > create mode 100644 target/avr/gdbstub.c > create mode 100644 target/avr/machine.c > create mode 100644 gdb-xml/avr-cpu.xml > > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h > new file mode 100644 > index 0000000000..ccd1ea3429 > --- /dev/null > +++ b/target/avr/cpu-param.h > @@ -0,0 +1,37 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef AVR_CPU_PARAM_H > +#define AVR_CPU_PARAM_H 1 > + > +#define TARGET_LONG_BITS 32 > +/* > + * TARGET_PAGE_BITS cannot be more than 8 bits because > + * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they > + * should be implemented as a device and not memory > + * 2. SRAM starts at the address 0x0100 > + */ > +#define TARGET_PAGE_BITS 8 > +#define TARGET_PHYS_ADDR_SPACE_BITS 24 > +#define TARGET_VIRT_ADDR_SPACE_BITS 24 > +#define NB_MMU_MODES 2 > + > + > +#endif > diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h > new file mode 100644 > index 0000000000..e28b58c897 > --- /dev/null > +++ b/target/avr/cpu-qom.h > @@ -0,0 +1,54 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef QEMU_AVR_QOM_H > +#define QEMU_AVR_QOM_H > + > +#include "hw/core/cpu.h" > + > +#define TYPE_AVR_CPU "avr-cpu" > + > +#define AVR_CPU_CLASS(klass) \ > + OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU) > +#define AVR_CPU(obj) \ > + OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU) > +#define AVR_CPU_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU) > + > +/** > + * AVRCPUClass: > + * @parent_realize: The parent class' realize handler. > + * @parent_reset: The parent class' reset handler. > + * @vr: Version Register value. > + * > + * A AVR CPU model. > + */ > +typedef struct AVRCPUClass { > + /*< private >*/ > + CPUClass parent_class; > + /*< public >*/ > + DeviceRealize parent_realize; > + void (*parent_reset)(CPUState *cpu); > +} AVRCPUClass; > + > +typedef struct AVRCPU AVRCPU; > + > + > +#endif /* !defined (QEMU_AVR_CPU_QOM_H) */ > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > new file mode 100644 > index 0000000000..ed9218af5f > --- /dev/null > +++ b/target/avr/cpu.h > @@ -0,0 +1,253 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef QEMU_AVR_CPU_H > +#define QEMU_AVR_CPU_H > + > +#include "cpu-qom.h" > +#include "exec/cpu-defs.h" > + > +#define TCG_GUEST_DEFAULT_MO 0 > + > +#define CPU_RESOLVING_TYPE TYPE_AVR_CPU > + > +/* > + * AVR has two memory spaces, data & code. > + * e.g. both have 0 address > + * ST/LD instructions access data space > + * LPM/SPM and instruction fetching access code memory space > + */ > +#define MMU_CODE_IDX 0 > +#define MMU_DATA_IDX 1 > + > +#define EXCP_RESET 1 > +#define EXCP_INT(n) (EXCP_RESET + (n) + 1) > + > +/* Number of CPU registers */ > +#define NO_CPU_REGISTERS 32 > +/* Number of IO registers accessible by ld/st/in/out */ > +#define NO_IO_REGISTERS 64 > + May I ask you to do a global replace of names of these two constants to CPU_REGISTERS_COUNT / IO_REGISTERS_COUNT or NUMBER_OF_CPU_REGISTERS / NUMBER_OF_IO_REGISTERS, or whatever else you find suitable (the reason being "NO_" is visually/perceptually very confusing - many readers would have first impression that it means a negative ("no"), not a "number of" as you, for sure, want. Thanks, Aleksandar > +/* > + * Offsets of AVR memory regions in host memory space. > + * > + * This is needed because the AVR has separate code and data address > + * spaces that both have start from zero but have to go somewhere in > + * host memory. > + * > + * It's also useful to know where some things are, like the IO registers. > + */ > +/* Flash program memory */ > +#define OFFSET_CODE 0x00000000 > +/* CPU registers, IO registers, and SRAM */ > +#define OFFSET_DATA 0x00800000 > +/* CPU registers specifically, these are mapped at the start of data */ > +#define OFFSET_CPU_REGISTERS OFFSET_DATA > +/* > + * IO registers, including status register, stack pointer, and memory > + * mapped peripherals, mapped just after CPU registers > + */ > +#define OFFSET_IO_REGISTERS (OFFSET_DATA + NO_CPU_REGISTERS) > + > +enum avr_features { > + AVR_FEATURE_SRAM, > + > + AVR_FEATURE_1_BYTE_PC, > + AVR_FEATURE_2_BYTE_PC, > + AVR_FEATURE_3_BYTE_PC, > + > + AVR_FEATURE_1_BYTE_SP, > + AVR_FEATURE_2_BYTE_SP, > + > + AVR_FEATURE_BREAK, > + AVR_FEATURE_DES, > + AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */ > + > + AVR_FEATURE_EIJMP_EICALL, > + AVR_FEATURE_IJMP_ICALL, > + AVR_FEATURE_JMP_CALL, > + > + AVR_FEATURE_ADIW_SBIW, > + > + AVR_FEATURE_SPM, > + AVR_FEATURE_SPMX, > + > + AVR_FEATURE_ELPMX, > + AVR_FEATURE_ELPM, > + AVR_FEATURE_LPMX, > + AVR_FEATURE_LPM, > + > + AVR_FEATURE_MOVW, > + AVR_FEATURE_MUL, > + AVR_FEATURE_RAMPD, > + AVR_FEATURE_RAMPX, > + AVR_FEATURE_RAMPY, > + AVR_FEATURE_RAMPZ, > +}; > + > +typedef struct CPUAVRState CPUAVRState; > + > +struct CPUAVRState { > + uint32_t pc_w; /* 0x003fffff up to 22 bits */ > + > + uint32_t sregC; /* 0x00000001 1 bit */ > + uint32_t sregZ; /* 0x00000001 1 bit */ > + uint32_t sregN; /* 0x00000001 1 bit */ > + uint32_t sregV; /* 0x00000001 1 bit */ > + uint32_t sregS; /* 0x00000001 1 bit */ > + uint32_t sregH; /* 0x00000001 1 bit */ > + uint32_t sregT; /* 0x00000001 1 bit */ > + uint32_t sregI; /* 0x00000001 1 bit */ > + > + uint32_t rampD; /* 0x00ff0000 8 bits */ > + uint32_t rampX; /* 0x00ff0000 8 bits */ > + uint32_t rampY; /* 0x00ff0000 8 bits */ > + uint32_t rampZ; /* 0x00ff0000 8 bits */ > + uint32_t eind; /* 0x00ff0000 8 bits */ > + > + uint32_t r[NO_CPU_REGISTERS]; /* 8 bits each */ > + uint32_t sp; /* 16 bits */ > + > + uint32_t skip; /* if set skip instruction */ > + > + uint64_t intsrc; /* interrupt sources */ > + bool fullacc; /* CPU/MEM if true MEM only otherwise */ > + > + uint32_t features; > +}; > + > +/** > + * AVRCPU: > + * @env: #CPUAVRState > + * > + * A AVR CPU. > + */ > +typedef struct AVRCPU { > + /*< private >*/ > + CPUState parent_obj; > + /*< public >*/ > + > + CPUNegativeOffsetState neg; > + CPUAVRState env; > +} AVRCPU; > + > +#ifndef CONFIG_USER_ONLY > +extern const struct VMStateDescription vms_avr_cpu; > +#endif > + > +void avr_cpu_do_interrupt(CPUState *cpu); > +bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); > +hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > +int avr_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); > +int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > + > +static inline int avr_feature(CPUAVRState *env, int feature) > +{ > + return (env->features & (1U << feature)) != 0; > +} > + > +static inline void avr_set_feature(CPUAVRState *env, int feature) > +{ > + env->features |= (1U << feature); > +} > + > +#define cpu_list avr_cpu_list > +#define cpu_signal_handler cpu_avr_signal_handler > +#define cpu_mmu_index avr_cpu_mmu_index > + > +static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) > +{ > + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; > +} > + > +void avr_cpu_tcg_init(void); > + > +void avr_cpu_list(void); > +int cpu_avr_exec(CPUState *cpu); > +int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); > +int avr_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, > + int rw, int mmu_idx); > +int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, > + int len, bool is_write); > + > +enum { > + TB_FLAGS_FULL_ACCESS = 1, > + TB_FLAGS_SKIP = 2, > +}; > + > +static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong > *pc, > + target_ulong *cs_base, uint32_t *pflags) > +{ > + uint32_t flags = 0; > + > + *pc = env->pc_w * 2; > + *cs_base = 0; > + > + if (env->fullacc) { > + flags |= TB_FLAGS_FULL_ACCESS; > + } > + if (env->skip) { > + flags |= TB_FLAGS_SKIP; > + } > + > + *pflags = flags; > +} > + > +static inline int cpu_interrupts_enabled(CPUAVRState *env) > +{ > + return env->sregI != 0; > +} > + > +static inline uint8_t cpu_get_sreg(CPUAVRState *env) > +{ > + uint8_t sreg; > + sreg = (env->sregC) << 0 > + | (env->sregZ) << 1 > + | (env->sregN) << 2 > + | (env->sregV) << 3 > + | (env->sregS) << 4 > + | (env->sregH) << 5 > + | (env->sregT) << 6 > + | (env->sregI) << 7; > + return sreg; > +} > + > +static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg) > +{ > + env->sregC = (sreg >> 0) & 0x01; > + env->sregZ = (sreg >> 1) & 0x01; > + env->sregN = (sreg >> 2) & 0x01; > + env->sregV = (sreg >> 3) & 0x01; > + env->sregS = (sreg >> 4) & 0x01; > + env->sregH = (sreg >> 5) & 0x01; > + env->sregT = (sreg >> 6) & 0x01; > + env->sregI = (sreg >> 7) & 0x01; > +} > + > +bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > + MMUAccessType access_type, int mmu_idx, > + bool probe, uintptr_t retaddr); > + > +typedef CPUAVRState CPUArchState; > +typedef AVRCPU ArchCPU; > + > +#include "exec/cpu-all.h" > + > +#endif /* !defined (QEMU_AVR_CPU_H) */ > diff --git a/target/avr/cpu.c b/target/avr/cpu.c > new file mode 100644 > index 0000000000..dae56d7845 > --- /dev/null > +++ b/target/avr/cpu.c > @@ -0,0 +1,576 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qapi/error.h" > +#include "qemu/qemu-print.h" > +#include "exec/exec-all.h" > +#include "cpu.h" > + > +static void avr_cpu_set_pc(CPUState *cs, vaddr value) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + > + cpu->env.pc_w = value / 2; /* internally PC points to words */ > +} > + > +static bool avr_cpu_has_work(CPUState *cs) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + CPUAVRState *env = &cpu->env; > + > + return (cs->interrupt_request & (CPU_INTERRUPT_HARD | > CPU_INTERRUPT_RESET)) > + && cpu_interrupts_enabled(env); > +} > + > +static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock > *tb) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + CPUAVRState *env = &cpu->env; > + > + env->pc_w = tb->pc / 2; /* internally PC points to words */ > +} > + > +static void avr_cpu_reset(CPUState *cs) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); > + CPUAVRState *env = &cpu->env; > + > + mcc->parent_reset(cs); > + > + env->pc_w = 0; > + env->sregI = 1; > + env->sregC = 0; > + env->sregZ = 0; > + env->sregN = 0; > + env->sregV = 0; > + env->sregS = 0; > + env->sregH = 0; > + env->sregT = 0; > + > + env->rampD = 0; > + env->rampX = 0; > + env->rampY = 0; > + env->rampZ = 0; > + env->eind = 0; > + env->sp = 0; > + > + env->skip = 0; > + > + memset(env->r, 0, sizeof(env->r)); > + > + tlb_flush(cs); > +} > + > +static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) > +{ > + info->mach = bfd_arch_avr; > + info->print_insn = NULL; > +} > + > +static void avr_cpu_realizefn(DeviceState *dev, Error **errp) > +{ > + CPUState *cs = CPU(dev); > + AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); > + Error *local_err = NULL; > + > + cpu_exec_realizefn(cs, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + qemu_init_vcpu(cs); > + cpu_reset(cs); > + > + mcc->parent_realize(dev, errp); > +} > + > +static void avr_cpu_set_int(void *opaque, int irq, int level) > +{ > + AVRCPU *cpu = opaque; > + CPUAVRState *env = &cpu->env; > + CPUState *cs = CPU(cpu); > + > + uint64_t mask = (1ull << irq); > + if (level) { > + env->intsrc |= mask; > + cpu_interrupt(cs, CPU_INTERRUPT_HARD); > + } else { > + env->intsrc &= ~mask; > + if (env->intsrc == 0) { > + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); > + } > + } > +} > + > +static void avr_cpu_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + > + cpu_set_cpustate_pointers(cpu); > + > +#ifndef CONFIG_USER_ONLY > + /* Set the number of interrupts supported by the CPU. */ > + qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 57); > +#endif > +} > + > +static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) > +{ > + ObjectClass *oc; > + > + oc = object_class_by_name(cpu_model); > + if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || > + object_class_is_abstract(oc)) { > + oc = NULL; > + } > + return oc; > +} > + > +static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + CPUAVRState *env = &cpu->env; > + int i; > + > + qemu_fprintf(f, "\n"); > + qemu_fprintf(f, "PC: %06x\n", env->pc_w); > + qemu_fprintf(f, "SP: %04x\n", env->sp); > + qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); > + qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); > + qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); > + qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); > + qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); > + qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); > + qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); > + qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); > + qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", > + env->sregI ? 'I' : '-', > + env->sregT ? 'T' : '-', > + env->sregH ? 'H' : '-', > + env->sregS ? 'S' : '-', > + env->sregV ? 'V' : '-', > + env->sregN ? '-' : 'N', /* Zf has negative logic > */ > + env->sregZ ? 'Z' : '-', > + env->sregC ? 'I' : '-'); > + qemu_fprintf(f, "SKIP: %02x\n", env->skip); > + > + qemu_fprintf(f, "\n"); > + for (i = 0; i < ARRAY_SIZE(env->r); i++) { > + qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); > + > + if ((i % 8) == 7) { > + qemu_fprintf(f, "\n"); > + } > + } > + qemu_fprintf(f, "\n"); > +} > + > +static void avr_cpu_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + CPUClass *cc = CPU_CLASS(oc); > + AVRCPUClass *mcc = AVR_CPU_CLASS(oc); > + > + mcc->parent_realize = dc->realize; > + dc->realize = avr_cpu_realizefn; > + > + mcc->parent_reset = cc->reset; > + cc->reset = avr_cpu_reset; > + > + cc->class_by_name = avr_cpu_class_by_name; > + > + cc->has_work = avr_cpu_has_work; > + cc->do_interrupt = avr_cpu_do_interrupt; > + cc->cpu_exec_interrupt = avr_cpu_exec_interrupt; > + cc->dump_state = avr_cpu_dump_state; > + cc->set_pc = avr_cpu_set_pc; > +#if !defined(CONFIG_USER_ONLY) > + cc->memory_rw_debug = avr_cpu_memory_rw_debug; > +#endif > +#ifdef CONFIG_USER_ONLY > + cc->handle_mmu_fault = avr_cpu_handle_mmu_fault; > +#else > + cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; > + cc->vmsd = &vms_avr_cpu; > +#endif > + cc->disas_set_info = avr_cpu_disas_set_info; > + cc->tlb_fill = avr_cpu_tlb_fill; > + cc->tcg_initialize = avr_cpu_tcg_init; > + cc->synchronize_from_tb = avr_cpu_synchronize_from_tb; > + cc->gdb_read_register = avr_cpu_gdb_read_register; > + cc->gdb_write_register = avr_cpu_gdb_write_register; > + cc->gdb_num_core_regs = 35; > + cc->gdb_core_xml_file = "avr-cpu.xml"; > +} > + > +static void avr_avr1_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > +} > + > +static void avr_avr2_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > +} > + > +static void avr_avr25_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > +} > + > +static void avr_avr3_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > +} > + > +static void avr_avr31_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > +} > + > +static void avr_avr35_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > +} > + > +static void avr_avr4_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > +} > + > +static void avr_avr5_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > +} > + > +static void avr_avr51_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_ELPMX); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > +} > + > +static void avr_avr6_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_3_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); > + avr_set_feature(env, AVR_FEATURE_ELPMX); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > +} > + > +static void avr_xmega2_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > + avr_set_feature(env, AVR_FEATURE_RMW); > +} > + > +static void avr_xmega4_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_ELPMX); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > + avr_set_feature(env, AVR_FEATURE_RMW); > +} > + > +static void avr_xmega5_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_2_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPD); > + avr_set_feature(env, AVR_FEATURE_RAMPX); > + avr_set_feature(env, AVR_FEATURE_RAMPY); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_ELPMX); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > + avr_set_feature(env, AVR_FEATURE_RMW); > +} > + > +static void avr_xmega6_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_3_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); > + avr_set_feature(env, AVR_FEATURE_ELPMX); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > + avr_set_feature(env, AVR_FEATURE_RMW); > +} > + > +static void avr_xmega7_initfn(Object *obj) > +{ > + AVRCPU *cpu = AVR_CPU(obj); > + CPUAVRState *env = &cpu->env; > + > + avr_set_feature(env, AVR_FEATURE_LPM); > + avr_set_feature(env, AVR_FEATURE_IJMP_ICALL); > + avr_set_feature(env, AVR_FEATURE_ADIW_SBIW); > + avr_set_feature(env, AVR_FEATURE_SRAM); > + avr_set_feature(env, AVR_FEATURE_BREAK); > + > + avr_set_feature(env, AVR_FEATURE_3_BYTE_PC); > + avr_set_feature(env, AVR_FEATURE_2_BYTE_SP); > + avr_set_feature(env, AVR_FEATURE_RAMPD); > + avr_set_feature(env, AVR_FEATURE_RAMPX); > + avr_set_feature(env, AVR_FEATURE_RAMPY); > + avr_set_feature(env, AVR_FEATURE_RAMPZ); > + avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL); > + avr_set_feature(env, AVR_FEATURE_ELPMX); > + avr_set_feature(env, AVR_FEATURE_ELPM); > + avr_set_feature(env, AVR_FEATURE_JMP_CALL); > + avr_set_feature(env, AVR_FEATURE_LPMX); > + avr_set_feature(env, AVR_FEATURE_MOVW); > + avr_set_feature(env, AVR_FEATURE_MUL); > + avr_set_feature(env, AVR_FEATURE_RMW); > +} > + > +typedef struct AVRCPUInfo { > + const char *name; > + void (*initfn)(Object *obj); > +} AVRCPUInfo; > + > + > +static void avr_cpu_list_entry(gpointer data, gpointer user_data) > +{ > + const char *typename = object_class_get_name(OBJECT_CLASS(data)); > + > + qemu_printf("%s\n", typename); > +} > + > +void avr_cpu_list(void) > +{ > + GSList *list; > + list = object_class_get_list_sorted(TYPE_AVR_CPU, false); > + g_slist_foreach(list, avr_cpu_list_entry, NULL); > + g_slist_free(list); > +} > + > +#define DEFINE_AVR_CPU_TYPE(model, initfn) \ > + { \ > + .parent = TYPE_AVR_CPU, \ > + .instance_init = initfn, \ > + .name = model "-avr-cpu", \ > + } > + > +static const TypeInfo avr_cpu_type_info[] = { > + { > + .name = TYPE_AVR_CPU, > + .parent = TYPE_CPU, > + .instance_size = sizeof(AVRCPU), > + .instance_init = avr_cpu_initfn, > + .class_size = sizeof(AVRCPUClass), > + .class_init = avr_cpu_class_init, > + .abstract = true, > + }, > + DEFINE_AVR_CPU_TYPE("avr1", avr_avr1_initfn), > + DEFINE_AVR_CPU_TYPE("avr2", avr_avr2_initfn), > + DEFINE_AVR_CPU_TYPE("avr25", avr_avr25_initfn), > + DEFINE_AVR_CPU_TYPE("avr3", avr_avr3_initfn), > + DEFINE_AVR_CPU_TYPE("avr31", avr_avr31_initfn), > + DEFINE_AVR_CPU_TYPE("avr35", avr_avr35_initfn), > + DEFINE_AVR_CPU_TYPE("avr4", avr_avr4_initfn), > + DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), > + DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), > + DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), > + DEFINE_AVR_CPU_TYPE("xmega2", avr_xmega2_initfn), > + DEFINE_AVR_CPU_TYPE("xmega4", avr_xmega4_initfn), > + DEFINE_AVR_CPU_TYPE("xmega5", avr_xmega5_initfn), > + DEFINE_AVR_CPU_TYPE("xmega6", avr_xmega6_initfn), > + DEFINE_AVR_CPU_TYPE("xmega7", avr_xmega7_initfn), > +}; > + > +DEFINE_TYPES(avr_cpu_type_info) > diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c > new file mode 100644 > index 0000000000..20a5252482 > --- /dev/null > +++ b/target/avr/gdbstub.c > @@ -0,0 +1,85 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "exec/gdbstub.h" > + > +int avr_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + CPUAVRState *env = &cpu->env; > + > + /* R */ > + if (n < 32) { > + return gdb_get_reg8(mem_buf, env->r[n]); > + } > + > + /* SREG */ > + if (n == 32) { > + uint8_t sreg = cpu_get_sreg(env); > + > + return gdb_get_reg8(mem_buf, sreg); > + } > + > + /* SP */ > + if (n == 33) { > + return gdb_get_reg16(mem_buf, env->sp & 0x0000ffff); > + } > + > + /* PC */ > + if (n == 34) { > + return gdb_get_reg32(mem_buf, env->pc_w * 2); > + } > + > + return 0; > +} > + > +int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) > +{ > + AVRCPU *cpu = AVR_CPU(cs); > + CPUAVRState *env = &cpu->env; > + > + /* R */ > + if (n < 32) { > + env->r[n] = *mem_buf; > + return 1; > + } > + > + /* SREG */ > + if (n == 32) { > + cpu_set_sreg(env, *mem_buf); > + return 1; > + } > + > + /* SP */ > + if (n == 33) { > + env->sp = lduw_p(mem_buf); > + return 2; > + } > + > + /* PC */ > + if (n == 34) { > + env->pc_w = ldl_p(mem_buf) / 2; > + return 4; > + } > + > + return 0; > +} > diff --git a/target/avr/machine.c b/target/avr/machine.c > new file mode 100644 > index 0000000000..f6dcda7adc > --- /dev/null > +++ b/target/avr/machine.c > @@ -0,0 +1,121 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#include "qemu/osdep.h" > +#include "cpu.h" > +#include "migration/cpu.h" > + > +static int get_sreg(QEMUFile *f, void *opaque, size_t size, > + const VMStateField *field) > +{ > + CPUAVRState *env = opaque; > + uint8_t sreg; > + > + sreg = qemu_get_byte(f); > + cpu_set_sreg(env, sreg); > + return 0; > +} > + > +static int put_sreg( > + QEMUFile *f, void *opaque, size_t size, > + const VMStateField *field, QJSON *vmdesc) > +{ > + CPUAVRState *env = opaque; > + uint8_t sreg = cpu_get_sreg(env); > + > + qemu_put_byte(f, sreg); > + return 0; > +} > + > +static const VMStateInfo vms_sreg = { > + .name = "sreg", > + .get = get_sreg, > + .put = put_sreg, > +}; > + > +static int get_segment( > + QEMUFile *f, void *opaque, size_t size, const VMStateField *field) > +{ > + uint32_t *ramp = opaque; > + uint8_t temp; > + > + temp = qemu_get_byte(f); > + *ramp = ((uint32_t)temp) << 16; > + return 0; > +} > + > +static int put_segment( > + QEMUFile *f, void *opaque, size_t size, > + const VMStateField *field, QJSON *vmdesc) > +{ > + uint32_t *ramp = opaque; > + uint8_t temp = *ramp >> 16; > + > + qemu_put_byte(f, temp); > + return 0; > +} > + > +static const VMStateInfo vms_rampD = { > + .name = "rampD", > + .get = get_segment, > + .put = put_segment, > +}; > +static const VMStateInfo vms_rampX = { > + .name = "rampX", > + .get = get_segment, > + .put = put_segment, > +}; > +static const VMStateInfo vms_rampY = { > + .name = "rampY", > + .get = get_segment, > + .put = put_segment, > +}; > +static const VMStateInfo vms_rampZ = { > + .name = "rampZ", > + .get = get_segment, > + .put = put_segment, > +}; > +static const VMStateInfo vms_eind = { > + .name = "eind", > + .get = get_segment, > + .put = put_segment, > +}; > + > +const VMStateDescription vms_avr_cpu = { > + .name = "cpu", > + .version_id = 0, > + .minimum_version_id = 0, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32(env.pc_w, AVRCPU), > + VMSTATE_UINT32(env.sp, AVRCPU), > + VMSTATE_UINT32(env.skip, AVRCPU), > + > + VMSTATE_UINT32_ARRAY(env.r, AVRCPU, NO_CPU_REGISTERS), > + > + VMSTATE_SINGLE(env, AVRCPU, 0, vms_sreg, CPUAVRState), > + VMSTATE_SINGLE(env.rampD, AVRCPU, 0, vms_rampD, uint32_t), > + VMSTATE_SINGLE(env.rampX, AVRCPU, 0, vms_rampX, uint32_t), > + VMSTATE_SINGLE(env.rampY, AVRCPU, 0, vms_rampY, uint32_t), > + VMSTATE_SINGLE(env.rampZ, AVRCPU, 0, vms_rampZ, uint32_t), > + VMSTATE_SINGLE(env.eind, AVRCPU, 0, vms_eind, uint32_t), > + > + VMSTATE_END_OF_LIST() > + } > +}; > diff --git a/gdb-xml/avr-cpu.xml b/gdb-xml/avr-cpu.xml > new file mode 100644 > index 0000000000..c4747f5b40 > --- /dev/null > +++ b/gdb-xml/avr-cpu.xml > @@ -0,0 +1,49 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > -- > 2.17.2 (Apple Git-113) > > --0000000000005c3597059835c107 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Sunday, November 24, 2019, Michael Rolnik <mrolnik@gmail.com> wrote:
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks

Co-developed-by: Michael Rolnik <mr= olnik@gmail.com>
Co-developed-by: Sarah Harris <= S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrol= nik@gmail.com>
Signed-off-by: Sarah Harris <S.= E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrol= nik@gmail.com>
Acked-by: Igor Mammedov <imammedo= @redhat.com>
---
=C2=A0target/avr/cpu-param.h |=C2=A0 37 +++
=C2=A0target/avr/cpu-qom.h=C2=A0 =C2=A0|=C2=A0 54 ++++
=C2=A0target/avr/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0| 253 ++++++++++++++++++ =C2=A0target/avr/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0| 576 ++++++++++++++++++++= +++++++++++++++++++++
=C2=A0target/avr/gdbstub.c=C2=A0 =C2=A0|=C2=A0 85 ++++++
=C2=A0target/avr/machine.c=C2=A0 =C2=A0| 121 +++++++++
=C2=A0gdb-xml/avr-cpu.xml=C2=A0 =C2=A0 |=C2=A0 49 ++++
=C2=A07 files changed, 1175 insertions(+)
=C2=A0create mode 100644 target/avr/cpu-param.h
=C2=A0create mode 100644 target/avr/cpu-qom.h
=C2=A0create mode 100644 target/avr/cpu.h
=C2=A0create mode 100644 target/avr/cpu.c
=C2=A0create mode 100644 target/avr/gdbstub.c
=C2=A0create mode 100644 target/avr/machine.c
=C2=A0create mode 100644 gdb-xml/avr-cpu.xml

diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
new file mode 100644
index 0000000000..ccd1ea3429
--- /dev/null
+++ b/target/avr/cpu-param.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef AVR_CPU_PARAM_H
+#define AVR_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+/*
+ * TARGET_PAGE_BITS cannot be more than 8 bits because
+ * 1.=C2=A0 all IO registers occupy [0x0000 .. 0x00ff] address range, and = they
+ *=C2=A0 =C2=A0 =C2=A0should be implemented as a device and not memory
+ * 2.=C2=A0 SRAM starts at the address 0x0100
+ */
+#define TARGET_PAGE_BITS 8
+#define TARGET_PHYS_ADDR_SPACE_BITS 24
+#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define NB_MMU_MODES 2
+
+
+#endif
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
new file mode 100644
index 0000000000..e28b58c897
--- /dev/null
+++ b/target/avr/cpu-qom.h
@@ -0,0 +1,54 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef QEMU_AVR_QOM_H
+#define QEMU_AVR_QOM_H
+
+#include "hw/core/cpu.h"
+
+#define TYPE_AVR_CPU "avr-cpu"
+
+#define AVR_CPU_CLASS(klass) \
+=C2=A0 =C2=A0 OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)<= br> +#define AVR_CPU(obj) \
+=C2=A0 =C2=A0 OBJECT_CHECK(AVRCPU, (obj), TYPE_AVR_CPU)
+#define AVR_CPU_GET_CLASS(obj) \
+=C2=A0 =C2=A0 OBJECT_GET_CLASS(AVRCPUClass, (obj), TYPE_AVR_CPU)
+
+/**
+ *=C2=A0 AVRCPUClass:
+ *=C2=A0 @parent_realize: The parent class' realize handler.
+ *=C2=A0 @parent_reset: The parent class' reset handler.
+ *=C2=A0 @vr: Version Register value.
+ *
+ *=C2=A0 A AVR CPU model.
+ */
+typedef struct AVRCPUClass {
+=C2=A0 =C2=A0 /*< private >*/
+=C2=A0 =C2=A0 CPUClass parent_class;
+=C2=A0 =C2=A0 /*< public >*/
+=C2=A0 =C2=A0 DeviceRealize parent_realize;
+=C2=A0 =C2=A0 void (*parent_reset)(CPUState *cpu);
+} AVRCPUClass;
+
+typedef struct AVRCPU AVRCPU;
+
+
+#endif /* !defined (QEMU_AVR_CPU_QOM_H) */
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
new file mode 100644
index 0000000000..ed9218af5f
--- /dev/null
+++ b/target/avr/cpu.h
@@ -0,0 +1,253 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef QEMU_AVR_CPU_H
+#define QEMU_AVR_CPU_H
+
+#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
+
+#define TCG_GUEST_DEFAULT_MO 0
+
+#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
+
+/*
+ * AVR has two memory spaces, data & code.
+ * e.g. both have 0 address
+ * ST/LD instructions access data space
+ * LPM/SPM and instruction fetching access code memory space
+ */
+#define MMU_CODE_IDX 0
+#define MMU_DATA_IDX 1
+
+#define EXCP_RESET 1
+#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
+
+/* Number of CPU registers */
+#define NO_CPU_REGISTERS 32
+/* Number of IO registers accessible by ld/st/in/out */
+#define NO_IO_REGISTERS 64
+

May I ask you to do a global repla= ce of names of these two constants
to CPU_REGISTERS_COUNT= / IO_REGISTERS_COUNT or NUMBER_OF_CPU_REGISTERS
/ NUMBER= _OF_IO_REGISTERS, or whatever else you find suitable (the
reason being "NO_" is visually/perceptually very confusing - m= any
readers would have first impression that it means a n= egative ("no"),
not a "number of" as = you, for sure, want.

Thanks,
Alek= sandar
=C2=A0
+/*
+ * Offsets of AVR memory regions in host memory space.
+ *
+ * This is needed because the AVR has separate code and data address
+ * spaces that both have start from zero but have to go somewhere in
+ * host memory.
+ *
+ * It's also useful to know where some things are, like the IO registe= rs.
+ */
+/* Flash program memory */
+#define OFFSET_CODE 0x00000000
+/* CPU registers, IO registers, and SRAM */
+#define OFFSET_DATA 0x00800000
+/* CPU registers specifically, these are mapped at the start of data */ +#define OFFSET_CPU_REGISTERS OFFSET_DATA
+/*
+ * IO registers, including status register, stack pointer, and memory
+ * mapped peripherals, mapped just after CPU registers
+ */
+#define OFFSET_IO_REGISTERS (OFFSET_DATA + NO_CPU_REGISTERS)
+
+enum avr_features {
+=C2=A0 =C2=A0 AVR_FEATURE_SRAM,
+
+=C2=A0 =C2=A0 AVR_FEATURE_1_BYTE_PC,
+=C2=A0 =C2=A0 AVR_FEATURE_2_BYTE_PC,
+=C2=A0 =C2=A0 AVR_FEATURE_3_BYTE_PC,
+
+=C2=A0 =C2=A0 AVR_FEATURE_1_BYTE_SP,
+=C2=A0 =C2=A0 AVR_FEATURE_2_BYTE_SP,
+
+=C2=A0 =C2=A0 AVR_FEATURE_BREAK,
+=C2=A0 =C2=A0 AVR_FEATURE_DES,
+=C2=A0 =C2=A0 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */ +
+=C2=A0 =C2=A0 AVR_FEATURE_EIJMP_EICALL,
+=C2=A0 =C2=A0 AVR_FEATURE_IJMP_ICALL,
+=C2=A0 =C2=A0 AVR_FEATURE_JMP_CALL,
+
+=C2=A0 =C2=A0 AVR_FEATURE_ADIW_SBIW,
+
+=C2=A0 =C2=A0 AVR_FEATURE_SPM,
+=C2=A0 =C2=A0 AVR_FEATURE_SPMX,
+
+=C2=A0 =C2=A0 AVR_FEATURE_ELPMX,
+=C2=A0 =C2=A0 AVR_FEATURE_ELPM,
+=C2=A0 =C2=A0 AVR_FEATURE_LPMX,
+=C2=A0 =C2=A0 AVR_FEATURE_LPM,
+
+=C2=A0 =C2=A0 AVR_FEATURE_MOVW,
+=C2=A0 =C2=A0 AVR_FEATURE_MUL,
+=C2=A0 =C2=A0 AVR_FEATURE_RAMPD,
+=C2=A0 =C2=A0 AVR_FEATURE_RAMPX,
+=C2=A0 =C2=A0 AVR_FEATURE_RAMPY,
+=C2=A0 =C2=A0 AVR_FEATURE_RAMPZ,
+};
+
+typedef struct CPUAVRState CPUAVRState;
+
+struct CPUAVRState {
+=C2=A0 =C2=A0 uint32_t pc_w; /* 0x003fffff up to 22 bits */
+
+=C2=A0 =C2=A0 uint32_t sregC; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregZ; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregN; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregV; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregS; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregH; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregT; /* 0x00000001 1 bit */
+=C2=A0 =C2=A0 uint32_t sregI; /* 0x00000001 1 bit */
+
+=C2=A0 =C2=A0 uint32_t rampD; /* 0x00ff0000 8 bits */
+=C2=A0 =C2=A0 uint32_t rampX; /* 0x00ff0000 8 bits */
+=C2=A0 =C2=A0 uint32_t rampY; /* 0x00ff0000 8 bits */
+=C2=A0 =C2=A0 uint32_t rampZ; /* 0x00ff0000 8 bits */
+=C2=A0 =C2=A0 uint32_t eind; /* 0x00ff0000 8 bits */
+
+=C2=A0 =C2=A0 uint32_t r[NO_CPU_REGISTERS]; /* 8 bits each */
+=C2=A0 =C2=A0 uint32_t sp; /* 16 bits */
+
+=C2=A0 =C2=A0 uint32_t skip; /* if set skip instruction */
+
+=C2=A0 =C2=A0 uint64_t intsrc; /* interrupt sources */
+=C2=A0 =C2=A0 bool fullacc; /* CPU/MEM if true MEM only otherwise */
+
+=C2=A0 =C2=A0 uint32_t features;
+};
+
+/**
+ *=C2=A0 AVRCPU:
+ *=C2=A0 @env: #CPUAVRState
+ *
+ *=C2=A0 A AVR CPU.
+ */
+typedef struct AVRCPU {
+=C2=A0 =C2=A0 /*< private >*/
+=C2=A0 =C2=A0 CPUState parent_obj;
+=C2=A0 =C2=A0 /*< public >*/
+
+=C2=A0 =C2=A0 CPUNegativeOffsetState neg;
+=C2=A0 =C2=A0 CPUAVRState env;
+} AVRCPU;
+
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vms_avr_cpu;
+#endif
+
+void avr_cpu_do_interrupt(CPUState *cpu);
+bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
+hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int avr_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);<= br> +int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);=
+
+static inline int avr_feature(CPUAVRState *env, int feature)
+{
+=C2=A0 =C2=A0 return (env->features & (1U << feature)) !=3D 0= ;
+}
+
+static inline void avr_set_feature(CPUAVRState *env, int feature)
+{
+=C2=A0 =C2=A0 env->features |=3D (1U << feature);
+}
+
+#define cpu_list avr_cpu_list
+#define cpu_signal_handler cpu_avr_signal_handler
+#define cpu_mmu_index avr_cpu_mmu_index
+
+static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
+{
+=C2=A0 =C2=A0 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
+}
+
+void avr_cpu_tcg_init(void);
+
+void avr_cpu_list(void);
+int cpu_avr_exec(CPUState *cpu);
+int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
+int avr_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int rw, int mmu_idx);
+int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int len, bool is_write);
+
+enum {
+=C2=A0 =C2=A0 TB_FLAGS_FULL_ACCESS =3D 1,
+=C2=A0 =C2=A0 TB_FLAGS_SKIP =3D 2,
+};
+
+static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulon= g *pc,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong *cs_base, uint32_t *pfl= ags)
+{
+=C2=A0 =C2=A0 uint32_t flags =3D 0;
+
+=C2=A0 =C2=A0 *pc =3D env->pc_w * 2;
+=C2=A0 =C2=A0 *cs_base =3D 0;
+
+=C2=A0 =C2=A0 if (env->fullacc) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 flags |=3D TB_FLAGS_FULL_ACCESS;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 if (env->skip) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 flags |=3D TB_FLAGS_SKIP;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 *pflags =3D flags;
+}
+
+static inline int cpu_interrupts_enabled(CPUAVRState *env)
+{
+=C2=A0 =C2=A0 return env->sregI !=3D 0;
+}
+
+static inline uint8_t cpu_get_sreg(CPUAVRState *env)
+{
+=C2=A0 =C2=A0 uint8_t sreg;
+=C2=A0 =C2=A0 sreg =3D (env->sregC) << 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregZ) << 1
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregN) << 2
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregV) << 3
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregS) << 4
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregH) << 5
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregT) << 6
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| (env->sregI) << 7;
+=C2=A0 =C2=A0 return sreg;
+}
+
+static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg)
+{
+=C2=A0 =C2=A0 env->sregC =3D (sreg >> 0) & 0x01;
+=C2=A0 =C2=A0 env->sregZ =3D (sreg >> 1) & 0x01;
+=C2=A0 =C2=A0 env->sregN =3D (sreg >> 2) & 0x01;
+=C2=A0 =C2=A0 env->sregV =3D (sreg >> 3) & 0x01;
+=C2=A0 =C2=A0 env->sregS =3D (sreg >> 4) & 0x01;
+=C2=A0 =C2=A0 env->sregH =3D (sreg >> 5) & 0x01;
+=C2=A0 =C2=A0 env->sregT =3D (sreg >> 6) & 0x01;
+=C2=A0 =C2=A0 env->sregI =3D (sreg >> 7) & 0x01;
+}
+
+bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 MMUAccessType access_type, int mmu_idx,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 bool probe, uintptr_t retaddr);
+
+typedef CPUAVRState CPUArchState;
+typedef AVRCPU ArchCPU;
+
+#include "exec/cpu-all.h"
+
+#endif /* !defined (QEMU_AVR_CPU_H) */
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
new file mode 100644
index 0000000000..dae56d7845
--- /dev/null
+++ b/target/avr/cpu.c
@@ -0,0 +1,576 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/qemu-print.h"
+#include "exec/exec-all.h"
+#include "cpu.h"
+
+static void avr_cpu_set_pc(CPUState *cs, vaddr value)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+
+=C2=A0 =C2=A0 cpu->env.pc_w =3D value / 2; /* internally PC points to w= ords */
+}
+
+static bool avr_cpu_has_work(CPUState *cs)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 return (cs->interrupt_request & (CPU_INTERRUPT_HARD |= CPU_INTERRUPT_RESET))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 && cpu_interrupts_enable= d(env);
+}
+
+static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBloc= k *tb)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 env->pc_w =3D tb->pc / 2; /* internally PC points to w= ords */
+}
+
+static void avr_cpu_reset(CPUState *cs)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+=C2=A0 =C2=A0 AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(cpu);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 mcc->parent_reset(cs);
+
+=C2=A0 =C2=A0 env->pc_w =3D 0;
+=C2=A0 =C2=A0 env->sregI =3D 1;
+=C2=A0 =C2=A0 env->sregC =3D 0;
+=C2=A0 =C2=A0 env->sregZ =3D 0;
+=C2=A0 =C2=A0 env->sregN =3D 0;
+=C2=A0 =C2=A0 env->sregV =3D 0;
+=C2=A0 =C2=A0 env->sregS =3D 0;
+=C2=A0 =C2=A0 env->sregH =3D 0;
+=C2=A0 =C2=A0 env->sregT =3D 0;
+
+=C2=A0 =C2=A0 env->rampD =3D 0;
+=C2=A0 =C2=A0 env->rampX =3D 0;
+=C2=A0 =C2=A0 env->rampY =3D 0;
+=C2=A0 =C2=A0 env->rampZ =3D 0;
+=C2=A0 =C2=A0 env->eind =3D 0;
+=C2=A0 =C2=A0 env->sp =3D 0;
+
+=C2=A0 =C2=A0 env->skip =3D 0;
+
+=C2=A0 =C2=A0 memset(env->r, 0, sizeof(env->r));
+
+=C2=A0 =C2=A0 tlb_flush(cs);
+}
+
+static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *i= nfo)
+{
+=C2=A0 =C2=A0 info->mach =3D bfd_arch_avr;
+=C2=A0 =C2=A0 info->print_insn =3D NULL;
+}
+
+static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+=C2=A0 =C2=A0 CPUState *cs =3D CPU(dev);
+=C2=A0 =C2=A0 AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(dev);
+=C2=A0 =C2=A0 Error *local_err =3D NULL;
+
+=C2=A0 =C2=A0 cpu_exec_realizefn(cs, &local_err);
+=C2=A0 =C2=A0 if (local_err !=3D NULL) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 error_propagate(errp, local_err);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 qemu_init_vcpu(cs);
+=C2=A0 =C2=A0 cpu_reset(cs);
+
+=C2=A0 =C2=A0 mcc->parent_realize(dev, errp);
+}
+
+static void avr_cpu_set_int(void *opaque, int irq, int level)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D opaque;
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+=C2=A0 =C2=A0 CPUState *cs =3D CPU(cpu);
+
+=C2=A0 =C2=A0 uint64_t mask =3D (1ull << irq);
+=C2=A0 =C2=A0 if (level) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->intsrc |=3D mask;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->intsrc &=3D ~mask;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (env->intsrc =3D=3D 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_reset_interrupt(cs, CPU_INTE= RRUPT_HARD);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+}
+
+static void avr_cpu_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+
+=C2=A0 =C2=A0 cpu_set_cpustate_pointers(cpu);
+
+#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 /* Set the number of interrupts supported by the CPU. */
+=C2=A0 =C2=A0 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 57);
+#endif
+}
+
+static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
+{
+=C2=A0 =C2=A0 ObjectClass *oc;
+
+=C2=A0 =C2=A0 oc =3D object_class_by_name(cpu_model);
+=C2=A0 =C2=A0 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) =3D=3D NULL = ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_class_is_abstract(oc)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 oc =3D NULL;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 return oc;
+}
+
+static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+=C2=A0 =C2=A0 int i;
+
+=C2=A0 =C2=A0 qemu_fprintf(f, "\n");
+=C2=A0 =C2=A0 qemu_fprintf(f, "PC:=C2=A0 =C2=A0 %06x\n", env->= ;pc_w);
+=C2=A0 =C2=A0 qemu_fprintf(f, "SP:=C2=A0 =C2=A0 =C2=A0 %04x\n", = env->sp);
+=C2=A0 =C2=A0 qemu_fprintf(f, "rampD:=C2=A0 =C2=A0 =C2=A0%02x\n"= , env->rampD >> 16);
+=C2=A0 =C2=A0 qemu_fprintf(f, "rampX:=C2=A0 =C2=A0 =C2=A0%02x\n"= , env->rampX >> 16);
+=C2=A0 =C2=A0 qemu_fprintf(f, "rampY:=C2=A0 =C2=A0 =C2=A0%02x\n"= , env->rampY >> 16);
+=C2=A0 =C2=A0 qemu_fprintf(f, "rampZ:=C2=A0 =C2=A0 =C2=A0%02x\n"= , env->rampZ >> 16);
+=C2=A0 =C2=A0 qemu_fprintf(f, "EIND:=C2=A0 =C2=A0 =C2=A0 %02x\n"= , env->eind >> 16);
+=C2=A0 =C2=A0 qemu_fprintf(f, "X:=C2=A0 =C2=A0 =C2=A0 =C2=A0%02x%02x\= n", env->r[27], env->r[26]);
+=C2=A0 =C2=A0 qemu_fprintf(f, "Y:=C2=A0 =C2=A0 =C2=A0 =C2=A0%02x%02x\= n", env->r[29], env->r[28]);
+=C2=A0 =C2=A0 qemu_fprintf(f, "Z:=C2=A0 =C2=A0 =C2=A0 =C2=A0%02x%02x\= n", env->r[31], env->r[30]);
+=C2=A0 =C2=A0 qemu_fprintf(f, "SREG:=C2=A0 =C2=A0 [ %c %c %c %c %c %c= %c %c ]\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregI ? 'I' : '-',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregT ? 'T' : '-',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregH ? 'H' : '-',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregS ? 'S' : '-',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregV ? 'V' : '-',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregN ? '-' : 'N', /* Zf has negative lo= gic */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregZ ? 'Z' : '-',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 env->sregC ? 'I' : '-');
+=C2=A0 =C2=A0 qemu_fprintf(f, "SKIP:=C2=A0 =C2=A0 %02x\n", env-&= gt;skip);
+
+=C2=A0 =C2=A0 qemu_fprintf(f, "\n");
+=C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SIZE(env->r); i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_fprintf(f, "R[%02d]:=C2=A0 %02x=C2= =A0 =C2=A0", i, env->r[i]);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((i % 8) =3D=3D 7) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_fprintf(f, "\n");=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 qemu_fprintf(f, "\n");
+}
+
+static void avr_cpu_class_init(ObjectClass *oc, void *data)
+{
+=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(oc);
+=C2=A0 =C2=A0 CPUClass *cc =3D CPU_CLASS(oc);
+=C2=A0 =C2=A0 AVRCPUClass *mcc =3D AVR_CPU_CLASS(oc);
+
+=C2=A0 =C2=A0 mcc->parent_realize =3D dc->realize;
+=C2=A0 =C2=A0 dc->realize =3D avr_cpu_realizefn;
+
+=C2=A0 =C2=A0 mcc->parent_reset =3D cc->reset;
+=C2=A0 =C2=A0 cc->reset =3D avr_cpu_reset;
+
+=C2=A0 =C2=A0 cc->class_by_name =3D avr_cpu_class_by_name;
+
+=C2=A0 =C2=A0 cc->has_work =3D avr_cpu_has_work;
+=C2=A0 =C2=A0 cc->do_interrupt =3D avr_cpu_do_interrupt;
+=C2=A0 =C2=A0 cc->cpu_exec_interrupt =3D avr_cpu_exec_interrupt;
+=C2=A0 =C2=A0 cc->dump_state =3D avr_cpu_dump_state;
+=C2=A0 =C2=A0 cc->set_pc =3D avr_cpu_set_pc;
+#if !defined(CONFIG_USER_ONLY)
+=C2=A0 =C2=A0 cc->memory_rw_debug =3D avr_cpu_memory_rw_debug;
+#endif
+#ifdef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 cc->handle_mmu_fault =3D avr_cpu_handle_mmu_fault;
+#else
+=C2=A0 =C2=A0 cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug;<= br> +=C2=A0 =C2=A0 cc->vmsd =3D &vms_avr_cpu;
+#endif
+=C2=A0 =C2=A0 cc->disas_set_info =3D avr_cpu_disas_set_info;
+=C2=A0 =C2=A0 cc->tlb_fill =3D avr_cpu_tlb_fill;
+=C2=A0 =C2=A0 cc->tcg_initialize =3D avr_cpu_tcg_init;
+=C2=A0 =C2=A0 cc->synchronize_from_tb =3D avr_cpu_synchronize_from_tb;<= br> +=C2=A0 =C2=A0 cc->gdb_read_register =3D avr_cpu_gdb_read_register;
+=C2=A0 =C2=A0 cc->gdb_write_register =3D avr_cpu_gdb_write_register; +=C2=A0 =C2=A0 cc->gdb_num_core_regs =3D 35;
+=C2=A0 =C2=A0 cc->gdb_core_xml_file =3D "avr-cpu.xml";
+}
+
+static void avr_avr1_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+}
+
+static void avr_avr2_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+}
+
+static void avr_avr25_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+}
+
+static void avr_avr3_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+}
+
+static void avr_avr31_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+}
+
+static void avr_avr35_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+}
+
+static void avr_avr4_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_avr5_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_avr51_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_avr6_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+}
+
+static void avr_xmega2_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega4_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega5_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPD);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPY);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega6_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+static void avr_xmega7_initfn(Object *obj)
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(obj);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_IJMP_ICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ADIW_SBIW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_SRAM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_BREAK);
+
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_3_BYTE_PC);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_2_BYTE_SP);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPD);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPY);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RAMPZ);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_EIJMP_EICALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_ELPM);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_JMP_CALL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_LPMX);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MOVW);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_MUL);
+=C2=A0 =C2=A0 avr_set_feature(env, AVR_FEATURE_RMW);
+}
+
+typedef struct AVRCPUInfo {
+=C2=A0 =C2=A0 const char *name;
+=C2=A0 =C2=A0 void (*initfn)(Object *obj);
+} AVRCPUInfo;
+
+
+static void avr_cpu_list_entry(gpointer data, gpointer user_data)
+{
+=C2=A0 =C2=A0 const char *typename =3D object_class_get_name(OBJECT_C= LASS(data));
+
+=C2=A0 =C2=A0 qemu_printf("%s\n", typename);
+}
+
+void avr_cpu_list(void)
+{
+=C2=A0 =C2=A0 GSList *list;
+=C2=A0 =C2=A0 list =3D object_class_get_list_sorted(TYPE_AVR_CPU, fal= se);
+=C2=A0 =C2=A0 g_slist_foreach(list, avr_cpu_list_entry, NULL);
+=C2=A0 =C2=A0 g_slist_free(list);
+}
+
+#define DEFINE_AVR_CPU_TYPE(model, initfn) \
+=C2=A0 =C2=A0 { \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .parent =3D TYPE_AVR_CPU, \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .instance_init =3D initfn, \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .name =3D model "-avr-cpu", \
+=C2=A0 =C2=A0 }
+
+static const TypeInfo avr_cpu_type_info[] =3D {
+=C2=A0 =C2=A0 {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .name =3D TYPE_AVR_CPU,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .parent =3D TYPE_CPU,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .instance_size =3D sizeof(AVRCPU),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .instance_init =3D avr_cpu_initfn,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .class_size =3D sizeof(AVRCPUClass),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .class_init =3D avr_cpu_class_init,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .abstract =3D true,
+=C2=A0 =C2=A0 },
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr1", avr_avr1_initfn),
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr2", avr_avr2_initfn),
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr25", avr_avr25_initfn), +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr3", avr_avr3_initfn),
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr31", avr_avr31_initfn), +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr35", avr_avr35_initfn), +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr4", avr_avr4_initfn),
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
+=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega2", avr_xmega2_initfn),<= br> +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega4", avr_xmega4_initfn),<= br> +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega5", avr_xmega5_initfn),<= br> +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega6", avr_xmega6_initfn),<= br> +=C2=A0 =C2=A0 DEFINE_AVR_CPU_TYPE("xmega7", avr_xmega7_initfn),<= br> +};
+
+DEFINE_TYPES(avr_cpu_type_info)
diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c
new file mode 100644
index 0000000000..20a5252482
--- /dev/null
+++ b/target/avr/gdbstub.c
@@ -0,0 +1,85 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
+
+int avr_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)<= br> +{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 /*=C2=A0 R */
+=C2=A0 =C2=A0 if (n < 32) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg8(mem_buf, env->r[n]); +=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*=C2=A0 SREG */
+=C2=A0 =C2=A0 if (n =3D=3D 32) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint8_t sreg =3D cpu_get_sreg(env);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg8(mem_buf, sreg);
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*=C2=A0 SP */
+=C2=A0 =C2=A0 if (n =3D=3D 33) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg16(mem_buf, env->sp &= 0x0000ffff);
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*=C2=A0 PC */
+=C2=A0 =C2=A0 if (n =3D=3D 34) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return gdb_get_reg32(mem_buf, env->pc_w * 2= );
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 return 0;
+}
+
+int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)=
+{
+=C2=A0 =C2=A0 AVRCPU *cpu =3D AVR_CPU(cs);
+=C2=A0 =C2=A0 CPUAVRState *env =3D &cpu->env;
+
+=C2=A0 =C2=A0 /*=C2=A0 R */
+=C2=A0 =C2=A0 if (n < 32) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->r[n] =3D *mem_buf;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 1;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*=C2=A0 SREG */
+=C2=A0 =C2=A0 if (n =3D=3D 32) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_set_sreg(env, *mem_buf);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 1;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*=C2=A0 SP */
+=C2=A0 =C2=A0 if (n =3D=3D 33) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->sp =3D lduw_p(mem_buf);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 2;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /*=C2=A0 PC */
+=C2=A0 =C2=A0 if (n =3D=3D 34) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->pc_w =3D ldl_p(mem_buf) / 2;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 4;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 return 0;
+}
diff --git a/target/avr/machine.c b/target/avr/machine.c
new file mode 100644
index 0000000000..f6dcda7adc
--- /dev/null
+++ b/target/avr/machine.c
@@ -0,0 +1,121 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+static int get_sreg(QEMUFile *f, void *opaque, size_t size,
+=C2=A0 =C2=A0 const VMStateField *field)
+{
+=C2=A0 =C2=A0 CPUAVRState *env =3D opaque;
+=C2=A0 =C2=A0 uint8_t sreg;
+
+=C2=A0 =C2=A0 sreg =3D qemu_get_byte(f);
+=C2=A0 =C2=A0 cpu_set_sreg(env, sreg);
+=C2=A0 =C2=A0 return 0;
+}
+
+static int put_sreg(
+=C2=A0 =C2=A0 QEMUFile *f, void *opaque, size_t size,
+=C2=A0 =C2=A0 const VMStateField *field, QJSON *vmdesc)
+{
+=C2=A0 =C2=A0 CPUAVRState *env =3D opaque;
+=C2=A0 =C2=A0 uint8_t sreg =3D cpu_get_sreg(env);
+
+=C2=A0 =C2=A0 qemu_put_byte(f, sreg);
+=C2=A0 =C2=A0 return 0;
+}
+
+static const VMStateInfo vms_sreg =3D {
+=C2=A0 =C2=A0 .name =3D "sreg",
+=C2=A0 =C2=A0 .get =3D get_sreg,
+=C2=A0 =C2=A0 .put =3D put_sreg,
+};
+
+static int get_segment(
+=C2=A0 =C2=A0 QEMUFile *f, void *opaque, size_t size, const VMStateField *= field)
+{
+=C2=A0 =C2=A0 uint32_t *ramp =3D opaque;
+=C2=A0 =C2=A0 uint8_t temp;
+
+=C2=A0 =C2=A0 temp =3D qemu_get_byte(f);
+=C2=A0 =C2=A0 *ramp =3D ((uint32_t)temp) << 16;
+=C2=A0 =C2=A0 return 0;
+}
+
+static int put_segment(
+=C2=A0 =C2=A0 QEMUFile *f, void *opaque, size_t size,
+=C2=A0 =C2=A0 const VMStateField *field, QJSON *vmdesc)
+{
+=C2=A0 =C2=A0 uint32_t *ramp =3D opaque;
+=C2=A0 =C2=A0 uint8_t temp =3D *ramp >> 16;
+
+=C2=A0 =C2=A0 qemu_put_byte(f, temp);
+=C2=A0 =C2=A0 return 0;
+}
+
+static const VMStateInfo vms_rampD =3D {
+=C2=A0 =C2=A0 .name =3D "rampD",
+=C2=A0 =C2=A0 .get =3D get_segment,
+=C2=A0 =C2=A0 .put =3D put_segment,
+};
+static const VMStateInfo vms_rampX =3D {
+=C2=A0 =C2=A0 .name =3D "rampX",
+=C2=A0 =C2=A0 .get =3D get_segment,
+=C2=A0 =C2=A0 .put =3D put_segment,
+};
+static const VMStateInfo vms_rampY =3D {
+=C2=A0 =C2=A0 .name =3D "rampY",
+=C2=A0 =C2=A0 .get =3D get_segment,
+=C2=A0 =C2=A0 .put =3D put_segment,
+};
+static const VMStateInfo vms_rampZ =3D {
+=C2=A0 =C2=A0 .name =3D "rampZ",
+=C2=A0 =C2=A0 .get =3D get_segment,
+=C2=A0 =C2=A0 .put =3D put_segment,
+};
+static const VMStateInfo vms_eind =3D {
+=C2=A0 =C2=A0 .name =3D "eind",
+=C2=A0 =C2=A0 .get =3D get_segment,
+=C2=A0 =C2=A0 .put =3D put_segment,
+};
+
+const VMStateDescription vms_avr_cpu =3D {
+=C2=A0 =C2=A0 .name =3D "cpu",
+=C2=A0 =C2=A0 .version_id =3D 0,
+=C2=A0 =C2=A0 .minimum_version_id =3D 0,
+=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(env.pc_w, AVRCPU),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(env.sp, AVRCPU),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32(env.skip, AVRCPU),
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT32_ARRAY(env.r, AVRCPU, NO_CPU_REG= ISTERS),
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_SINGLE(env, AVRCPU, 0, vms_sreg, CPUAV= RState),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_SINGLE(env.rampD, AVRCPU, 0, vms_rampD= , uint32_t),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_SINGLE(env.rampX, AVRCPU, 0, vms_rampX= , uint32_t),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_SINGLE(env.rampY, AVRCPU, 0, vms_rampY= , uint32_t),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_SINGLE(env.rampZ, AVRCPU, 0, vms_rampZ= , uint32_t),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_SINGLE(env.eind, AVRCPU, 0, vms_eind, = uint32_t),
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
+=C2=A0 =C2=A0 }
+};
diff --git a/gdb-xml/avr-cpu.xml b/gdb-xml/avr-cpu.xml
new file mode 100644
index 0000000000..c4747f5b40
--- /dev/null
+++ b/gdb-xml/avr-cpu.xml
@@ -0,0 +1,49 @@
+<?xml version=3D"1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+=C2=A0 =C2=A0 =C2=A0Copying and distribution of this file, with or without= modification,
+=C2=A0 =C2=A0 =C2=A0are permitted in any medium without royalty provided t= he copyright
+=C2=A0 =C2=A0 =C2=A0notice and this notice are preserved.=C2=A0 -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+=C2=A0 =C2=A0 =C2=A0compatibility with older versions of tools that didn&#= 39;t use xml
+=C2=A0 =C2=A0 =C2=A0register descriptions.=C2=A0 -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name=3D"org.gnu.gdb.riscv.cpu">
+=C2=A0 <reg name=3D"r0" bitsize=3D"8" type=3D"= int" regnum=3D"0"/>
+=C2=A0 <reg name=3D"r1" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r2" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r3" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r4" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r5" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r6" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r7" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r8" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r9" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"r10" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r11" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r12" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r13" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r14" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r15" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r16" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r17" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r18" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r19" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r20" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r21" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r22" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r23" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r24" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r25" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r26" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r27" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r28" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r29" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r30" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"r31" bitsize=3D"8" type=3D"= ;int"/>
+=C2=A0 <reg name=3D"sreg" bitsize=3D"8" type=3D&quo= t;int"/>
+=C2=A0 <reg name=3D"sp" bitsize=3D"8" type=3D"= int"/>
+=C2=A0 <reg name=3D"pc" bitsize=3D"8" type=3D"= int"/>
+</feature>
--
2.17.2 (Apple Git-113)

--0000000000005c3597059835c107--