* [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState
@ 2019-05-08 0:06 Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc Richard Henderson
` (38 more replies)
0 siblings, 39 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Patches missing review/ack:
0010-target-cris-Reindent-mmu.c.patch (new)
0011-target-cris-Reindent-op_helper.c.patch (new)
0034-cpu-Move-icount_decr-to-CPUNegativeOffsetState.patch
0037-tcg-aarch64-Use-LDP-to-load-tlb-mask-table.patch
0038-tcg-arm-Use-LDRD-to-load-tlb-mask-table.patch
0039-tcg-arm-Remove-mostly-unreachable-tlb-special-cas.patch (new)
Changes from v2->v3:
* Incorporate review from pm215:
include guards and copyright/license for new headers;
qemu_build_bug_on for tcg/{arm,aarch64}/ load-pair expectations;
split out an independant tlb change in tcg/arm/;
split out some re-indent patches for target/cris/.
Changes from v1->v2:
* Add cpu_set_cpustate_pointers.
* Add icount_decr_ptr to CPUState.
Blurb from v1:
This started merely as an attempt to reduce the size of each
softmmu lookup by using smaller offsets from env. But in the
end it also represents a significant cleanup in the boilerplate
that each target must define.
With respect to the initial goal, here are the relevant code
snips generated for loading the mask & table fields for a
qemu_ld from an aarch64 guest on the indicated host.
r~
Richard Henderson (39):
tcg: Fold CPUTLBWindow into CPUTLBDesc
tcg: Split out target/arch/cpu-param.h
tcg: Create struct CPUTLB
cpu: Define CPUArchState with typedef
cpu: Define ArchCPU
cpu: Replace ENV_GET_CPU with env_cpu
cpu: Introduce env_archcpu
target/alpha: Use env_cpu, env_archcpu
target/arm: Use env_cpu, env_archcpu
target/cris: Reindent mmu.c
target/cris: Reindent op_helper.c
target/cris: Use env_cpu, env_archcpu
target/hppa: Use env_cpu, env_archcpu
target/i386: Use env_cpu, env_archcpu
target/lm32: Use env_cpu, env_archcpu
target/m68k: Use env_cpu, env_archcpu
target/microblaze: Use env_cpu, env_archcpu
target/mips: Use env_cpu, env_archcpu
target/moxie: Use env_cpu, env_archcpu
target/nios2: Use env_cpu, env_archcpu
target/openrisc: Use env_cpu, env_archcpu
target/ppc: Use env_cpu, env_archcpu
target/riscv: Use env_cpu, env_archcpu
target/s390x: Use env_cpu, env_archcpu
target/sh4: Use env_cpu, env_archcpu
target/sparc: Use env_cpu, env_archcpu
target/tilegx: Use env_cpu
target/tricore: Use env_cpu
target/unicore32: Use env_cpu, env_archcpu
target/xtensa: Use env_cpu, env_archcpu
cpu: Move ENV_OFFSET to exec/gen-icount.h
cpu: Introduce cpu_set_cpustate_pointers
cpu: Introduce CPUNegativeOffsetState
cpu: Move icount_decr to CPUNegativeOffsetState
cpu: Move the softmmu tlb to CPUNegativeOffsetState
cpu: Remove CPU_COMMON
tcg/aarch64: Use LDP to load tlb mask+table
tcg/arm: Use LDRD to load tlb mask+table
tcg/arm: Remove mostly unreachable tlb special case
accel/tcg/atomic_template.h | 8 +-
accel/tcg/softmmu_template.h | 24 +-
include/exec/cpu-all.h | 58 ++
include/exec/cpu-defs.h | 113 ++-
include/exec/cpu_ldst.h | 6 +-
include/exec/cpu_ldst_template.h | 6 +-
include/exec/cpu_ldst_useronly_template.h | 6 +-
include/exec/gen-icount.h | 14 +-
include/exec/softmmu-semi.h | 16 +-
include/qom/cpu.h | 40 +-
linux-user/cpu_loop-common.h | 2 +-
linux-user/m68k/target_cpu.h | 2 +-
target/alpha/cpu-param.h | 31 +
target/alpha/cpu.h | 40 +-
target/arm/cpu-param.h | 34 +
target/arm/cpu.h | 52 +-
target/cris/cpu-param.h | 17 +
target/cris/cpu.h | 25 +-
target/hppa/cpu-param.h | 34 +
target/hppa/cpu.h | 38 +-
target/i386/cpu-param.h | 28 +
target/i386/cpu.h | 40 +-
target/lm32/cpu-param.h | 17 +
target/lm32/cpu.h | 25 +-
target/m68k/cpu-param.h | 22 +
target/m68k/cpu.h | 28 +-
target/microblaze/cpu-param.h | 18 +
target/microblaze/cpu.h | 63 +-
target/mips/cpu-param.h | 29 +
target/mips/cpu.h | 21 +-
target/mips/mips-defs.h | 15 -
target/moxie/cpu-param.h | 17 +
target/moxie/cpu.h | 29 +-
target/nios2/cpu-param.h | 21 +
target/nios2/cpu.h | 33 +-
target/openrisc/cpu-param.h | 17 +
target/openrisc/cpu.h | 31 +-
target/ppc/cpu-param.h | 37 +
target/ppc/cpu.h | 61 +-
target/ppc/helper_regs.h | 4 +-
target/riscv/cpu-param.h | 23 +
target/riscv/cpu.h | 35 +-
target/s390x/cpu-param.h | 17 +
target/s390x/cpu.h | 31 +-
target/sh4/cpu-param.h | 21 +
target/sh4/cpu.h | 30 +-
target/sparc/cpu-param.h | 28 +
target/sparc/cpu.h | 36 +-
target/tilegx/cpu-param.h | 17 +
target/tilegx/cpu.h | 23 +-
target/tricore/cpu-param.h | 17 +
target/tricore/cpu.h | 22 +-
target/tricore/tricore-defs.h | 5 -
target/unicore32/cpu-param.h | 17 +
target/unicore32/cpu.h | 24 +-
target/xtensa/cpu-param.h | 21 +
target/xtensa/cpu.h | 40 +-
accel/tcg/cpu-exec.c | 23 +-
accel/tcg/cputlb.c | 195 ++---
accel/tcg/tcg-all.c | 6 +-
accel/tcg/tcg-runtime.c | 4 +-
accel/tcg/translate-all.c | 10 +-
accel/tcg/user-exec.c | 2 +-
bsd-user/main.c | 5 +-
bsd-user/syscall.c | 6 +-
cpus.c | 9 +-
hw/i386/kvmvapic.c | 4 +-
hw/i386/pc.c | 2 +-
hw/intc/mips_gic.c | 2 +-
hw/mips/mips_int.c | 2 +-
hw/nios2/cpu_pic.c | 5 +-
hw/ppc/ppc.c | 18 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc_booke.c | 4 +-
hw/sparc/leon3.c | 4 +-
hw/sparc/sun4m.c | 4 +-
hw/sparc64/sparc64.c | 2 +-
hw/unicore32/puv3.c | 2 +-
hw/xtensa/pic_cpu.c | 2 +-
linux-user/aarch64/cpu_loop.c | 6 +-
linux-user/aarch64/signal.c | 4 +-
linux-user/alpha/cpu_loop.c | 2 +-
linux-user/arm/cpu_loop.c | 4 +-
linux-user/cris/cpu_loop.c | 4 +-
linux-user/elfload.c | 6 +-
linux-user/hppa/cpu_loop.c | 2 +-
linux-user/i386/cpu_loop.c | 2 +-
linux-user/i386/signal.c | 2 +-
linux-user/m68k-sim.c | 3 +-
linux-user/m68k/cpu_loop.c | 4 +-
linux-user/main.c | 2 +-
linux-user/microblaze/cpu_loop.c | 2 +-
linux-user/mips/cpu_loop.c | 4 +-
linux-user/nios2/cpu_loop.c | 2 +-
linux-user/openrisc/cpu_loop.c | 2 +-
linux-user/ppc/cpu_loop.c | 2 +-
linux-user/riscv/cpu_loop.c | 4 +-
linux-user/s390x/cpu_loop.c | 2 +-
linux-user/sh4/cpu_loop.c | 2 +-
linux-user/signal.c | 8 +-
linux-user/sparc/cpu_loop.c | 2 +-
linux-user/syscall.c | 26 +-
linux-user/tilegx/cpu_loop.c | 2 +-
linux-user/uname.c | 2 +-
linux-user/vm86.c | 18 +-
linux-user/xtensa/cpu_loop.c | 2 +-
qom/cpu.c | 4 +-
target/alpha/cpu.c | 3 +-
target/alpha/helper.c | 8 +-
target/alpha/sys_helper.c | 8 +-
target/arm/arm-semi.c | 4 +-
target/arm/cpu.c | 3 +-
target/arm/cpu64.c | 2 +-
target/arm/helper-a64.c | 4 +-
target/arm/helper.c | 162 ++---
target/arm/op_helper.c | 21 +-
target/arm/translate-a64.c | 4 +-
target/arm/translate.c | 2 +-
target/arm/vfp_helper.c | 2 +-
target/cris/cpu.c | 3 +-
target/cris/mmu.c | 482 +++++++------
target/cris/op_helper.c | 827 +++++++++++-----------
target/cris/translate.c | 2 +-
target/hppa/cpu.c | 2 +-
target/hppa/helper.c | 3 +-
target/hppa/int_helper.c | 4 +-
target/hppa/mem_helper.c | 10 +-
target/hppa/op_helper.c | 10 +-
target/i386/bpt_helper.c | 4 +-
target/i386/cpu.c | 7 +-
target/i386/excp_helper.c | 2 +-
target/i386/fpu_helper.c | 2 +-
target/i386/hax-all.c | 6 +-
target/i386/helper.c | 16 +-
target/i386/hvf/x86_decode.c | 22 +-
target/i386/hvf/x86_emu.c | 60 +-
target/i386/mem_helper.c | 4 +-
target/i386/misc_helper.c | 24 +-
target/i386/seg_helper.c | 14 +-
target/i386/smm_helper.c | 4 +-
target/i386/svm_helper.c | 22 +-
target/lm32/cpu.c | 3 +-
target/lm32/helper.c | 19 +-
target/lm32/op_helper.c | 6 +-
target/lm32/translate.c | 2 +-
target/m68k/cpu.c | 4 +-
target/m68k/helper.c | 33 +-
target/m68k/m68k-semi.c | 4 +-
target/m68k/op_helper.c | 14 +-
target/m68k/translate.c | 4 +-
target/microblaze/cpu.c | 3 +-
target/microblaze/mmu.c | 5 +-
target/microblaze/op_helper.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/cpu.c | 3 +-
target/mips/helper.c | 15 +-
target/mips/op_helper.c | 25 +-
target/mips/translate.c | 3 +-
target/mips/translate_init.inc.c | 4 +-
target/moxie/cpu.c | 3 +-
target/moxie/helper.c | 6 +-
target/moxie/translate.c | 2 +-
target/nios2/cpu.c | 6 +-
target/nios2/mmu.c | 14 +-
target/nios2/op_helper.c | 2 +-
target/openrisc/cpu.c | 3 +-
target/openrisc/exception_helper.c | 5 +-
target/openrisc/sys_helper.c | 8 +-
target/ppc/excp_helper.c | 14 +-
target/ppc/fpu_helper.c | 14 +-
target/ppc/kvm.c | 5 +-
target/ppc/misc_helper.c | 22 +-
target/ppc/mmu-hash64.c | 14 +-
target/ppc/mmu_helper.c | 117 ++-
target/ppc/translate_init.inc.c | 88 ++-
target/riscv/cpu.c | 3 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 12 +-
target/riscv/op_helper.c | 8 +-
target/s390x/cc_helper.c | 5 +-
target/s390x/cpu.c | 9 +-
target/s390x/diag.c | 2 +-
target/s390x/excp_helper.c | 6 +-
target/s390x/fpu_helper.c | 4 +-
target/s390x/gdbstub.c | 24 +-
target/s390x/helper.c | 7 +-
target/s390x/int_helper.c | 3 +-
target/s390x/interrupt.c | 6 +-
target/s390x/mem_helper.c | 30 +-
target/s390x/misc_helper.c | 50 +-
target/s390x/mmu_helper.c | 8 +-
target/s390x/sigp.c | 4 +-
target/sh4/cpu.c | 3 +-
target/sh4/helper.c | 26 +-
target/sh4/op_helper.c | 11 +-
target/sparc/cpu.c | 3 +-
target/sparc/fop_helper.c | 2 +-
target/sparc/helper.c | 8 +-
target/sparc/ldst_helper.c | 33 +-
target/sparc/mmu_helper.c | 10 +-
target/tilegx/cpu.c | 4 +-
target/tilegx/helper.c | 2 +-
target/tricore/cpu.c | 4 +-
target/tricore/op_helper.c | 4 +-
target/unicore32/cpu.c | 3 +-
target/unicore32/helper.c | 8 +-
target/unicore32/op_helper.c | 2 +-
target/unicore32/softmmu.c | 11 +-
target/unicore32/translate.c | 26 +-
target/unicore32/ucf64_helper.c | 2 +-
target/xtensa/cpu.c | 3 +-
target/xtensa/dbg_helper.c | 4 +-
target/xtensa/exc_helper.c | 9 +-
target/xtensa/helper.c | 2 +-
target/xtensa/mmu_helper.c | 11 +-
target/xtensa/xtensa-semi.c | 2 +-
tcg/aarch64/tcg-target.inc.c | 40 +-
tcg/arm/tcg-target.inc.c | 149 ++--
tcg/i386/tcg-target.inc.c | 6 +-
tcg/mips/tcg-target.inc.c | 45 +-
tcg/ppc/tcg-target.inc.c | 32 +-
tcg/riscv/tcg-target.inc.c | 37 +-
tcg/s390/tcg-target.inc.c | 13 +-
tcg/sparc/tcg-target.inc.c | 40 +-
docs/devel/tracing.txt | 4 +-
scripts/tracetool/format/tcg_helper_c.py | 2 +-
226 files changed, 2371 insertions(+), 2569 deletions(-)
create mode 100644 target/alpha/cpu-param.h
create mode 100644 target/arm/cpu-param.h
create mode 100644 target/cris/cpu-param.h
create mode 100644 target/hppa/cpu-param.h
create mode 100644 target/i386/cpu-param.h
create mode 100644 target/lm32/cpu-param.h
create mode 100644 target/m68k/cpu-param.h
create mode 100644 target/microblaze/cpu-param.h
create mode 100644 target/mips/cpu-param.h
create mode 100644 target/moxie/cpu-param.h
create mode 100644 target/nios2/cpu-param.h
create mode 100644 target/openrisc/cpu-param.h
create mode 100644 target/ppc/cpu-param.h
create mode 100644 target/riscv/cpu-param.h
create mode 100644 target/s390x/cpu-param.h
create mode 100644 target/sh4/cpu-param.h
create mode 100644 target/sparc/cpu-param.h
create mode 100644 target/tilegx/cpu-param.h
create mode 100644 target/tricore/cpu-param.h
create mode 100644 target/unicore32/cpu-param.h
create mode 100644 target/xtensa/cpu-param.h
--
2.17.1
^ permalink raw reply [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 17:48 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 02/39] tcg: Split out target/arch/cpu-param.h Richard Henderson
` (37 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 17 ++++-------------
accel/tcg/cputlb.c | 24 ++++++++++++------------
2 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 8f2a848bf5..52d150aaf1 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -127,18 +127,6 @@ typedef struct CPUIOTLBEntry {
MemTxAttrs attrs;
} CPUIOTLBEntry;
-/**
- * struct CPUTLBWindow
- * @begin_ns: host time (in ns) at the beginning of the time window
- * @max_entries: maximum number of entries observed in the window
- *
- * See also: tlb_mmu_resize_locked()
- */
-typedef struct CPUTLBWindow {
- int64_t begin_ns;
- size_t max_entries;
-} CPUTLBWindow;
-
typedef struct CPUTLBDesc {
/*
* Describe a region covering all of the large pages allocated
@@ -148,9 +136,12 @@ typedef struct CPUTLBDesc {
*/
target_ulong large_page_addr;
target_ulong large_page_mask;
+ /* host time (in ns) at the beginning of the time window */
+ int64_t window_begin_ns;
+ /* maximum number of entries observed in the window */
+ size_t window_max_entries;
/* The next index to use in the tlb victim table. */
size_t vindex;
- CPUTLBWindow window;
size_t n_used_entries;
} CPUTLBDesc;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f2f618217d..6c7593235c 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -79,11 +79,11 @@ static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS);
}
-static void tlb_window_reset(CPUTLBWindow *window, int64_t ns,
+static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
size_t max_entries)
{
- window->begin_ns = ns;
- window->max_entries = max_entries;
+ desc->window_begin_ns = ns;
+ desc->window_max_entries = max_entries;
}
static void tlb_dyn_init(CPUArchState *env)
@@ -94,7 +94,7 @@ static void tlb_dyn_init(CPUArchState *env)
CPUTLBDesc *desc = &env->tlb_d[i];
size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
- tlb_window_reset(&desc->window, get_clock_realtime(), 0);
+ tlb_window_reset(desc, get_clock_realtime(), 0);
desc->n_used_entries = 0;
env->tlb_mask[i] = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
env->tlb_table[i] = g_new(CPUTLBEntry, n_entries);
@@ -151,18 +151,18 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
int64_t now = get_clock_realtime();
int64_t window_len_ms = 100;
int64_t window_len_ns = window_len_ms * 1000 * 1000;
- bool window_expired = now > desc->window.begin_ns + window_len_ns;
+ bool window_expired = now > desc->window_begin_ns + window_len_ns;
- if (desc->n_used_entries > desc->window.max_entries) {
- desc->window.max_entries = desc->n_used_entries;
+ if (desc->n_used_entries > desc->window_max_entries) {
+ desc->window_max_entries = desc->n_used_entries;
}
- rate = desc->window.max_entries * 100 / old_size;
+ rate = desc->window_max_entries * 100 / old_size;
if (rate > 70) {
new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
} else if (rate < 30 && window_expired) {
- size_t ceil = pow2ceil(desc->window.max_entries);
- size_t expected_rate = desc->window.max_entries * 100 / ceil;
+ size_t ceil = pow2ceil(desc->window_max_entries);
+ size_t expected_rate = desc->window_max_entries * 100 / ceil;
/*
* Avoid undersizing when the max number of entries seen is just below
@@ -182,7 +182,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
if (new_size == old_size) {
if (window_expired) {
- tlb_window_reset(&desc->window, now, desc->n_used_entries);
+ tlb_window_reset(desc, now, desc->n_used_entries);
}
return;
}
@@ -190,7 +190,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
g_free(env->tlb_table[mmu_idx]);
g_free(env->iotlb[mmu_idx]);
- tlb_window_reset(&desc->window, now, 0);
+ tlb_window_reset(desc, now, 0);
/* desc->n_used_entries is cleared by the caller */
env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS;
env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size);
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 02/39] tcg: Split out target/arch/cpu-param.h
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 03/39] tcg: Create struct CPUTLB Richard Henderson
` (36 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Include this new file from exec/cpu-defs.h.
This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the
bulk of the includes within target/arch/cpu.h to the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Add header comment + include guards.
Copyright and license copied from cpu.h, when present.
---
include/exec/cpu-defs.h | 22 +++++++++++++++++-
target/alpha/cpu-param.h | 31 ++++++++++++++++++++++++++
target/alpha/cpu.h | 23 +------------------
target/arm/cpu-param.h | 34 ++++++++++++++++++++++++++++
target/arm/cpu.h | 33 +++------------------------
target/cris/cpu-param.h | 17 ++++++++++++++
target/cris/cpu.h | 11 +--------
target/hppa/cpu-param.h | 34 ++++++++++++++++++++++++++++
target/hppa/cpu.h | 24 +-------------------
target/i386/cpu-param.h | 28 +++++++++++++++++++++++
target/i386/cpu.h | 21 ------------------
target/lm32/cpu-param.h | 17 ++++++++++++++
target/lm32/cpu.h | 12 +++-------
target/m68k/cpu-param.h | 22 ++++++++++++++++++
target/m68k/cpu.h | 16 ++-----------
target/microblaze/cpu-param.h | 18 +++++++++++++++
target/microblaze/cpu.h | 14 ++----------
target/mips/cpu-param.h | 29 ++++++++++++++++++++++++
target/mips/cpu.h | 3 +--
target/mips/mips-defs.h | 15 -------------
target/moxie/cpu-param.h | 17 ++++++++++++++
target/moxie/cpu.h | 12 +---------
target/nios2/cpu-param.h | 21 ++++++++++++++++++
target/nios2/cpu.h | 17 ++------------
target/openrisc/cpu-param.h | 17 ++++++++++++++
target/openrisc/cpu.h | 14 +++---------
target/ppc/cpu-param.h | 37 ++++++++++++++++++++++++++++++
target/ppc/cpu.h | 42 ++++-------------------------------
target/riscv/cpu-param.h | 23 +++++++++++++++++++
target/riscv/cpu.h | 21 ++++--------------
target/s390x/cpu-param.h | 17 ++++++++++++++
target/s390x/cpu.h | 11 +--------
target/sh4/cpu-param.h | 21 ++++++++++++++++++
target/sh4/cpu.h | 14 +-----------
target/sparc/cpu-param.h | 28 +++++++++++++++++++++++
target/sparc/cpu.h | 20 ++---------------
target/tilegx/cpu-param.h | 17 ++++++++++++++
target/tilegx/cpu.h | 9 +-------
target/tricore/cpu-param.h | 17 ++++++++++++++
target/tricore/cpu.h | 4 +---
target/tricore/tricore-defs.h | 5 -----
target/unicore32/cpu-param.h | 17 ++++++++++++++
target/unicore32/cpu.h | 10 +--------
target/xtensa/cpu-param.h | 21 ++++++++++++++++++
target/xtensa/cpu.h | 21 +++++-------------
45 files changed, 544 insertions(+), 333 deletions(-)
create mode 100644 target/alpha/cpu-param.h
create mode 100644 target/arm/cpu-param.h
create mode 100644 target/cris/cpu-param.h
create mode 100644 target/hppa/cpu-param.h
create mode 100644 target/i386/cpu-param.h
create mode 100644 target/lm32/cpu-param.h
create mode 100644 target/m68k/cpu-param.h
create mode 100644 target/microblaze/cpu-param.h
create mode 100644 target/mips/cpu-param.h
create mode 100644 target/moxie/cpu-param.h
create mode 100644 target/nios2/cpu-param.h
create mode 100644 target/openrisc/cpu-param.h
create mode 100644 target/ppc/cpu-param.h
create mode 100644 target/riscv/cpu-param.h
create mode 100644 target/s390x/cpu-param.h
create mode 100644 target/sh4/cpu-param.h
create mode 100644 target/sparc/cpu-param.h
create mode 100644 target/tilegx/cpu-param.h
create mode 100644 target/tricore/cpu-param.h
create mode 100644 target/unicore32/cpu-param.h
create mode 100644 target/xtensa/cpu-param.h
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 52d150aaf1..2694481769 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -34,8 +34,28 @@
#endif
#include "exec/memattrs.h"
+#include "cpu-param.h"
+
#ifndef TARGET_LONG_BITS
-#error TARGET_LONG_BITS must be defined before including this header
+# error TARGET_LONG_BITS must be defined in cpu-param.h
+#endif
+#ifndef NB_MMU_MODES
+# error NB_MMU_MODES must be defined in cpu-param.h
+#endif
+#ifndef TARGET_PHYS_ADDR_SPACE_BITS
+# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
+#endif
+#ifndef TARGET_VIRT_ADDR_SPACE_BITS
+# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
+#endif
+#ifndef TARGET_PAGE_BITS
+# ifdef TARGET_PAGE_BITS_VARY
+# ifndef TARGET_PAGE_BITS_MIN
+# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
+# endif
+# else
+# error TARGET_PAGE_BITS must be defined in cpu-param.h
+# endif
#endif
#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
new file mode 100644
index 0000000000..692aee27ca
--- /dev/null
+++ b/target/alpha/cpu-param.h
@@ -0,0 +1,31 @@
+/*
+ * Alpha cpu parameters for qemu.
+ *
+ * Copyright (c) 2007 Jocelyn Mayer
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef ALPHA_CPU_PARAM_H
+#define ALPHA_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 64
+#define TARGET_PAGE_BITS 13
+#ifdef CONFIG_USER_ONLY
+/*
+ * ??? The kernel likes to give addresses in high memory. If the host has
+ * more virtual address space than the guest, this can lead to impossible
+ * allocations. Honor the long-standing assumption that only kernel addrs
+ * are negative, but otherwise allow allocations anywhere. This could lead
+ * to tricky emulation problems for programs doing tagged addressing, but
+ * that's far fewer than encounter the impossible allocation problem.
+ */
+#define TARGET_PHYS_ADDR_SPACE_BITS 63
+#define TARGET_VIRT_ADDR_SPACE_BITS 63
+#else
+/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
+#define TARGET_PHYS_ADDR_SPACE_BITS 44
+#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
+#endif
+#define NB_MMU_MODES 3
+
+#endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 63bf3618ff..2ab468ffd6 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,8 +22,8 @@
#include "qemu-common.h"
#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
-#define TARGET_LONG_BITS 64
#define ALIGNED_ONLY
#define CPUArchState struct CPUAlphaState
@@ -31,28 +31,9 @@
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
-#include "exec/cpu-defs.h"
-
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32
-#define TARGET_PAGE_BITS 13
-
-#ifdef CONFIG_USER_ONLY
-/* ??? The kernel likes to give addresses in high memory. If the host has
- more virtual address space than the guest, this can lead to impossible
- allocations. Honor the long-standing assumption that only kernel addrs
- are negative, but otherwise allow allocations anywhere. This could lead
- to tricky emulation problems for programs doing tagged addressing, but
- that's far fewer than encounter the impossible allocation problem. */
-#define TARGET_PHYS_ADDR_SPACE_BITS 63
-#define TARGET_VIRT_ADDR_SPACE_BITS 63
-#else
-/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
-#define TARGET_PHYS_ADDR_SPACE_BITS 44
-#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
-#endif
-
/* Alpha major type */
enum {
ALPHA_EV3 = 1,
@@ -215,8 +196,6 @@ enum {
PALcode cheats and usees the KSEG mapping for its code+data rather than
physical addresses. */
-#define NB_MMU_MODES 3
-
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX 0
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
new file mode 100644
index 0000000000..6e6948e960
--- /dev/null
+++ b/target/arm/cpu-param.h
@@ -0,0 +1,34 @@
+/*
+ * ARM cpu parameters for qemu.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef ARM_CPU_PARAM_H
+#define ARM_CPU_PARAM_H 1
+
+#ifdef TARGET_AARCH64
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 48
+# define TARGET_VIRT_ADDR_SPACE_BITS 48
+#else
+# define TARGET_LONG_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 40
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+
+#ifdef CONFIG_USER_ONLY
+#define TARGET_PAGE_BITS 12
+#else
+/*
+ * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
+ * have to support 1K tiny pages.
+ */
+# define TARGET_PAGE_BITS_VARY
+# define TARGET_PAGE_BITS_MIN 10
+#endif
+
+#define NB_MMU_MODES 8
+
+#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 22bc6e00ab..ca199d1afb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -22,23 +22,15 @@
#include "kvm-consts.h"
#include "hw/registerfields.h"
-
-#if defined(TARGET_AARCH64)
- /* AArch64 definitions */
-# define TARGET_LONG_BITS 64
-#else
-# define TARGET_LONG_BITS 32
-#endif
+#include "qemu-common.h"
+#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#define CPUArchState struct CPUARMState
-#include "qemu-common.h"
-#include "cpu-qom.h"
-#include "exec/cpu-defs.h"
-
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
#define EXCP_PREFETCH_ABORT 3
@@ -114,7 +106,6 @@ enum {
#define ARM_CPU_VIRQ 2
#define ARM_CPU_VFIQ 3
-#define NB_MMU_MODES 8
/* ARM-specific extra insn start words:
* 1: Conditional execution bits
* 2: Partial exception syndrome for data aborts
@@ -2626,24 +2617,6 @@ bool write_cpustate_to_list(ARMCPU *cpu);
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
-#if defined(CONFIG_USER_ONLY)
-#define TARGET_PAGE_BITS 12
-#else
-/* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
- * have to support 1K tiny pages.
- */
-#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 10
-#endif
-
-#if defined(TARGET_AARCH64)
-# define TARGET_PHYS_ADDR_SPACE_BITS 48
-# define TARGET_VIRT_ADDR_SPACE_BITS 48
-#else
-# define TARGET_PHYS_ADDR_SPACE_BITS 40
-# define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
unsigned int target_el)
{
diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h
new file mode 100644
index 0000000000..36a3058761
--- /dev/null
+++ b/target/cris/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * CRIS cpu parameters for qemu.
+ *
+ * Copyright (c) 2007 AXIS Communications AB
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef CRIS_CPU_PARAM_H
+#define CRIS_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 13
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 0fbe771639..3fbe1232ab 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,13 +23,10 @@
#include "qemu-common.h"
#include "cpu-qom.h"
-
-#define TARGET_LONG_BITS 32
+#include "exec/cpu-defs.h"
#define CPUArchState struct CPUCRISState
-#include "exec/cpu-defs.h"
-
#define EXCP_NMI 1
#define EXCP_GURU 2
#define EXCP_BUSFAULT 3
@@ -105,8 +102,6 @@
#define CC_A 14
#define CC_P 15
-#define NB_MMU_MODES 2
-
typedef struct {
uint32_t hi;
uint32_t lo;
@@ -260,12 +255,8 @@ enum {
};
/* CRIS uses 8k pages. */
-#define TARGET_PAGE_BITS 13
#define MMAP_SHIFT TARGET_PAGE_BITS
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
new file mode 100644
index 0000000000..a97d1428df
--- /dev/null
+++ b/target/hppa/cpu-param.h
@@ -0,0 +1,34 @@
+/*
+ * PA-RISC cpu parameters for qemu.
+ *
+ * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef HPPA_CPU_PARAM_H
+#define HPPA_CPU_PARAM_H 1
+
+#ifdef TARGET_HPPA64
+# define TARGET_LONG_BITS 64
+# define TARGET_REGISTER_BITS 64
+# define TARGET_VIRT_ADDR_SPACE_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 64
+#elif defined(CONFIG_USER_ONLY)
+# define TARGET_LONG_BITS 32
+# define TARGET_REGISTER_BITS 32
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 32
+#else
+/*
+ * In order to form the GVA from space:offset,
+ * we need a 64-bit virtual address space.
+ */
+# define TARGET_LONG_BITS 64
+# define TARGET_REGISTER_BITS 32
+# define TARGET_VIRT_ADDR_SPACE_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 32
+#endif
+#define TARGET_PAGE_BITS 12
+#define NB_MMU_MODES 5
+
+#endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 923346adb6..f96c3a17e4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -22,25 +22,8 @@
#include "qemu-common.h"
#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
-#ifdef TARGET_HPPA64
-#define TARGET_LONG_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
-#define TARGET_REGISTER_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
-#elif defined(CONFIG_USER_ONLY)
-#define TARGET_LONG_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_REGISTER_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#else
-/* In order to form the GVA from space:offset,
- we need a 64-bit virtual address space. */
-#define TARGET_LONG_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
-#define TARGET_REGISTER_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
@@ -50,12 +33,7 @@
#define CPUArchState struct CPUHPPAState
-#include "exec/cpu-defs.h"
-
-#define TARGET_PAGE_BITS 12
-
#define ALIGNED_ONLY
-#define NB_MMU_MODES 5
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
#define MMU_PHYS_IDX 4
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
new file mode 100644
index 0000000000..57abc64c0d
--- /dev/null
+++ b/target/i386/cpu-param.h
@@ -0,0 +1,28 @@
+/*
+ * i386 cpu parameters for qemu.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef I386_CPU_PARAM_H
+#define I386_CPU_PARAM_H 1
+
+#ifdef TARGET_X86_64
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 52
+/*
+ * ??? This is really 48 bits, sign-extended, but the only thing
+ * accessible to userland with bit 48 set is the VSYSCALL, and that
+ * is handled via other mechanisms.
+ */
+# define TARGET_VIRT_ADDR_SPACE_BITS 47
+#else
+# define TARGET_LONG_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 36
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+#define TARGET_PAGE_BITS 12
+#define NB_MMU_MODES 3
+
+#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0128910661..e53dbdeee5 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -24,13 +24,6 @@
#include "qemu-common.h"
#include "cpu-qom.h"
#include "hyperv-proto.h"
-
-#ifdef TARGET_X86_64
-#define TARGET_LONG_BITS 64
-#else
-#define TARGET_LONG_BITS 32
-#endif
-
#include "exec/cpu-defs.h"
/* The x86 has a strong memory model with some store-after-load re-ordering */
@@ -955,7 +948,6 @@ typedef struct {
#define MAX_FIXED_COUNTERS 3
#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
-#define NB_MMU_MODES 3
#define TARGET_INSN_START_EXTRA_WORDS 1
#define NB_OPMASK_REGS 8
@@ -1693,19 +1685,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
-#define TARGET_PAGE_BITS 12
-
-#ifdef TARGET_X86_64
-#define TARGET_PHYS_ADDR_SPACE_BITS 52
-/* ??? This is really 48 bits, sign-extended, but the only thing
- accessible to userland with bit 48 set is the VSYSCALL, and that
- is handled via other mechanisms. */
-#define TARGET_VIRT_ADDR_SPACE_BITS 47
-#else
-#define TARGET_PHYS_ADDR_SPACE_BITS 36
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-
/* XXX: This value should match the one returned by CPUID
* and in exec.c */
# if defined(TARGET_X86_64)
diff --git a/target/lm32/cpu-param.h b/target/lm32/cpu-param.h
new file mode 100644
index 0000000000..d89574ad19
--- /dev/null
+++ b/target/lm32/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * LatticeMico32 cpu parameters for qemu.
+ *
+ * Copyright (c) 2010 Michael Walle <michael@walle.cc>
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef LM32_CPU_PARAM_H
+#define LM32_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 1
+
+#endif
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 9b1e6c2d58..79852dda5a 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -20,26 +20,20 @@
#ifndef LM32_CPU_H
#define LM32_CPU_H
-#define TARGET_LONG_BITS 32
-
-#define CPUArchState struct CPULM32State
-
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+
+#define CPUArchState struct CPULM32State
+
struct CPULM32State;
typedef struct CPULM32State CPULM32State;
-#define NB_MMU_MODES 1
-#define TARGET_PAGE_BITS 12
static inline int cpu_mmu_index(CPULM32State *env, bool ifetch)
{
return 0;
}
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
/* Exceptions indices */
enum {
EXCP_RESET = 0,
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
new file mode 100644
index 0000000000..06556dfbf3
--- /dev/null
+++ b/target/m68k/cpu-param.h
@@ -0,0 +1,22 @@
+/*
+ * m68k cpu parameters for qemu.
+ *
+ * Copyright (c) 2005-2007 CodeSourcery
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef M68K_CPU_PARAM_H
+#define M68K_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+/*
+ * Coldfire Linux uses 8k pages
+ * and m68k linux uses 4k pages
+ * use the smallest one
+ */
+#define TARGET_PAGE_BITS 12
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index ad41608341..bad85174ca 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -21,14 +21,12 @@
#ifndef M68K_CPU_H
#define M68K_CPU_H
-#define TARGET_LONG_BITS 32
-
-#define CPUArchState struct CPUM68KState
-
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#define CPUArchState struct CPUM68KState
+
#define OS_BYTE 0
#define OS_WORD 1
#define OS_LONG 2
@@ -82,7 +80,6 @@
#define M68K_MAX_TTR 2
#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
-#define NB_MMU_MODES 2
#define TARGET_INSN_START_EXTRA_WORDS 1
typedef CPU_LDoubleU FPReg;
@@ -502,12 +499,6 @@ void m68k_cpu_list(void);
void register_m68k_insns (CPUM68KState *env);
-/* Coldfire Linux uses 8k pages
- * and m68k linux uses 4k pages
- * use the smallest one
- */
-#define TARGET_PAGE_BITS 12
-
enum {
/* 1 bit to define user level / supervisor access */
ACCESS_SUPER = 0x01,
@@ -522,9 +513,6 @@ enum {
ACCESS_DATA = 0x20, /* Data load/store access */
};
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
new file mode 100644
index 0000000000..4abbc62d50
--- /dev/null
+++ b/target/microblaze/cpu-param.h
@@ -0,0 +1,18 @@
+/*
+ * MicroBlaze cpu parameters for qemu.
+ *
+ * Copyright (c) 2009 Edgar E. Iglesias
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef MICROBLAZE_CPU_PARAM_H
+#define MICROBLAZE_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 64
+#define TARGET_PHYS_ADDR_SPACE_BITS 64
+#define TARGET_VIRT_ADDR_SPACE_BITS 64
+/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
+#define TARGET_PAGE_BITS 12
+#define NB_MMU_MODES 3
+
+#endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index f20e796865..406dc0b5a3 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -22,13 +22,11 @@
#include "qemu-common.h"
#include "cpu-qom.h"
-
-#define TARGET_LONG_BITS 64
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat-types.h"
#define CPUArchState struct CPUMBState
-#include "exec/cpu-defs.h"
-#include "fpu/softfloat-types.h"
struct CPUMBState;
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
@@ -228,8 +226,6 @@ typedef struct CPUMBState CPUMBState;
#define CC_NE 1
#define CC_EQ 0
-#define NB_MMU_MODES 3
-
#define STREAM_EXCEPTION (1 << 0)
#define STREAM_ATOMIC (1 << 1)
#define STREAM_TEST (1 << 2)
@@ -340,12 +336,6 @@ void mb_tcg_init(void);
int cpu_mb_signal_handler(int host_signum, void *pinfo,
void *puc);
-/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
-#define TARGET_PAGE_BITS 12
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
-
#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
#define cpu_signal_handler cpu_mb_signal_handler
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
new file mode 100644
index 0000000000..308660d29d
--- /dev/null
+++ b/target/mips/cpu-param.h
@@ -0,0 +1,29 @@
+/*
+ * MIPS cpu parameters for qemu.
+ *
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef MIPS_CPU_PARAM_H
+#define MIPS_CPU_PARAM_H 1
+
+#ifdef TARGET_MIPS64
+# define TARGET_LONG_BITS 64
+#else
+# define TARGET_LONG_BITS 32
+#endif
+#ifdef TARGET_MIPS64
+#define TARGET_PHYS_ADDR_SPACE_BITS 48
+#define TARGET_VIRT_ADDR_SPACE_BITS 48
+#else
+#define TARGET_PHYS_ADDR_SPACE_BITS 40
+# ifdef CONFIG_USER_ONLY
+# define TARGET_VIRT_ADDR_SPACE_BITS 31
+# else
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+#endif
+#define TARGET_PAGE_BITS 12
+#define NB_MMU_MODES 4
+
+#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1f41cf66d5..b97b018399 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -7,9 +7,9 @@
#include "qemu-common.h"
#include "cpu-qom.h"
-#include "mips-defs.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
+#include "mips-defs.h"
#define TCG_GUEST_DEFAULT_MO (0)
@@ -89,7 +89,6 @@ struct CPUMIPSFPUContext {
#define FP_UNIMPLEMENTED 32
};
-#define NB_MMU_MODES 4
#define TARGET_INSN_START_EXTRA_WORDS 2
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index dbdb4b2b2d..bbf056a548 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -5,23 +5,8 @@
//#define USE_HOST_FLOAT_REGS
/* Real pages are variable size... */
-#define TARGET_PAGE_BITS 12
#define MIPS_TLB_MAX 128
-#if defined(TARGET_MIPS64)
-#define TARGET_LONG_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 48
-#define TARGET_VIRT_ADDR_SPACE_BITS 48
-#else
-#define TARGET_LONG_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 40
-# ifdef CONFIG_USER_ONLY
-# define TARGET_VIRT_ADDR_SPACE_BITS 31
-# else
-# define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-#endif
-
/*
* bit definitions for insn_flags (ISAs/ASEs flags)
* ------------------------------------------------
diff --git a/target/moxie/cpu-param.h b/target/moxie/cpu-param.h
new file mode 100644
index 0000000000..9a40ef525c
--- /dev/null
+++ b/target/moxie/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * Moxie cpu parameters for qemu.
+ *
+ * Copyright (c) 2008, 2010, 2013 Anthony Green
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#ifndef MOXIE_CPU_PARAM_H
+#define MOXIE_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12 /* 4k */
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 1
+
+#endif
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index f3b6d83ae7..fcb2ea76b7 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -21,8 +21,7 @@
#define MOXIE_CPU_H
#include "qemu-common.h"
-
-#define TARGET_LONG_BITS 32
+#include "exec/cpu-defs.h"
#define CPUArchState struct CPUMoxieState
@@ -33,15 +32,6 @@
#define MOXIE_EX_MMU_MISS 4
#define MOXIE_EX_BREAK 16
-#include "exec/cpu-defs.h"
-
-#define TARGET_PAGE_BITS 12 /* 4k */
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
-#define NB_MMU_MODES 1
-
typedef struct CPUMoxieState {
uint32_t flags; /* general execution flags */
diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h
new file mode 100644
index 0000000000..38bedbfd61
--- /dev/null
+++ b/target/nios2/cpu-param.h
@@ -0,0 +1,21 @@
+/*
+ * Altera Nios II cpu parameters for qemu.
+ *
+ * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#ifndef NIOS2_CPU_PARAM_H
+#define NIOS2_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#ifdef CONFIG_USER_ONLY
+# define TARGET_VIRT_ADDR_SPACE_BITS 31
+#else
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 881e7d58c9..b737b23fc5 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -21,13 +21,11 @@
#define CPU_NIOS2_H
#include "qemu-common.h"
-
-#define TARGET_LONG_BITS 32
+#include "exec/cpu-defs.h"
+#include "qom/cpu.h"
#define CPUArchState struct CPUNios2State
-#include "exec/cpu-defs.h"
-#include "qom/cpu.h"
struct CPUNios2State;
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
@@ -163,8 +161,6 @@ typedef struct Nios2CPUClass {
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
-#define NB_MMU_MODES 2
-
struct CPUNios2State {
uint32_t regs[NUM_CORE_REGS];
@@ -224,13 +220,6 @@ void nios2_check_interrupts(CPUNios2State *env);
void do_nios2_semihosting(CPUNios2State *env);
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#ifdef CONFIG_USER_ONLY
-# define TARGET_VIRT_ADDR_SPACE_BITS 31
-#else
-# define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-
#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
#define cpu_gen_code cpu_nios2_gen_code
@@ -238,8 +227,6 @@ void do_nios2_semihosting(CPUNios2State *env);
#define CPU_SAVE_VERSION 1
-#define TARGET_PAGE_BITS 12
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
new file mode 100644
index 0000000000..06ee64d171
--- /dev/null
+++ b/target/openrisc/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * OpenRISC cpu parameters for qemu.
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef OPENRISC_CPU_PARAM_H
+#define OPENRISC_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 13
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 3
+
+#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index a50861955a..bf8a354307 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -20,17 +20,15 @@
#ifndef OPENRISC_CPU_H
#define OPENRISC_CPU_H
-#define TARGET_LONG_BITS 32
+#include "qemu-common.h"
+#include "exec/cpu-defs.h"
+#include "qom/cpu.h"
#define CPUArchState struct CPUOpenRISCState
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
-#include "qemu-common.h"
-#include "exec/cpu-defs.h"
-#include "qom/cpu.h"
-
#define TYPE_OPENRISC_CPU "or1k-cpu"
#define OPENRISC_CPU_CLASS(klass) \
@@ -56,7 +54,6 @@ typedef struct OpenRISCCPUClass {
void (*parent_reset)(CPUState *cpu);
} OpenRISCCPUClass;
-#define NB_MMU_MODES 3
#define TARGET_INSN_START_EXTRA_WORDS 1
enum {
@@ -65,11 +62,6 @@ enum {
MMU_USER_IDX = 2,
};
-#define TARGET_PAGE_BITS 13
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
#define SET_FP_CAUSE(reg, v) do {\
(reg) = ((reg) & ~(0x3f << 12)) | \
((v & 0x3f) << 12);\
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
new file mode 100644
index 0000000000..37b458d33d
--- /dev/null
+++ b/target/ppc/cpu-param.h
@@ -0,0 +1,37 @@
+/*
+ * PowerPC cpu parameters for qemu.
+ *
+ * Copyright (c) 2007 Jocelyn Mayer
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef PPC_CPU_PARAM_H
+#define PPC_CPU_PARAM_H 1
+
+#ifdef TARGET_PPC64
+# define TARGET_LONG_BITS 64
+/*
+ * Note that the official physical address space bits is 62-M where M
+ * is implementation dependent. I've not looked up M for the set of
+ * cpus we emulate at the system level.
+ */
+#define TARGET_PHYS_ADDR_SPACE_BITS 62
+/*
+ * Note that the PPC environment architecture talks about 80 bit virtual
+ * addresses, with segmentation. Obviously that's not all visible to a
+ * single process, which is all we're concerned with here.
+ */
+# ifdef TARGET_ABI32
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# else
+# define TARGET_VIRT_ADDR_SPACE_BITS 64
+# endif
+#else
+# define TARGET_LONG_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 36
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+#define TARGET_PAGE_BITS 12
+#define NB_MMU_MODES 10
+
+#endif
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 5e7cf54b2f..e86f1650d5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -22,53 +22,20 @@
#include "qemu-common.h"
#include "qemu/int128.h"
+#include "exec/cpu-defs.h"
+#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
+#include "cpu-qom.h"
/* #define PPC_EMULATE_32BITS_HYPV */
-#if defined(TARGET_PPC64)
-/* PowerPC 64 definitions */
-#define TARGET_LONG_BITS 64
-#define TARGET_PAGE_BITS 12
-
#define TCG_GUEST_DEFAULT_MO 0
-/*
- * Note that the official physical address space bits is 62-M where M
- * is implementation dependent. I've not looked up M for the set of
- * cpus we emulate at the system level.
- */
-#define TARGET_PHYS_ADDR_SPACE_BITS 62
-
-/*
- * Note that the PPC environment architecture talks about 80 bit
- * virtual addresses, with segmentation. Obviously that's not all
- * visible to a single process, which is all we're concerned with
- * here.
- */
-#ifdef TARGET_ABI32
-# define TARGET_VIRT_ADDR_SPACE_BITS 32
-#else
-# define TARGET_VIRT_ADDR_SPACE_BITS 64
-#endif
-
#define TARGET_PAGE_BITS_64K 16
#define TARGET_PAGE_BITS_16M 24
-#else /* defined(TARGET_PPC64) */
-/* PowerPC 32 definitions */
-#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 12
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 36
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
-#endif /* defined(TARGET_PPC64) */
-
#define CPUArchState struct CPUPPCState
-#include "exec/cpu-defs.h"
-#include "cpu-qom.h"
-
#if defined(TARGET_PPC64)
#define PPC_ELF_MACHINE EM_PPC64
#else
@@ -974,7 +941,6 @@ struct ppc_radix_page_info {
* + real/paged mode combinations. The other two modes are for
* external PID load/store.
*/
-#define NB_MMU_MODES 10
#define MMU_MODE8_SUFFIX _epl
#define MMU_MODE9_SUFFIX _eps
#define PPC_TLB_EPID_LOAD 8
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
new file mode 100644
index 0000000000..664fc1d371
--- /dev/null
+++ b/target/riscv/cpu-param.h
@@ -0,0 +1,23 @@
+/*
+ * RISC-V cpu parameters for qemu.
+ *
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef RISCV_CPU_PARAM_H
+#define RISCV_CPU_PARAM_H 1
+
+#if defined(TARGET_RISCV64)
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
+#elif defined(TARGET_RISCV32)
+# define TARGET_LONG_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
+#endif
+#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+#define NB_MMU_MODES 4
+
+#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d9f48973f..8f480de324 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -20,27 +20,15 @@
#ifndef RISCV_CPU_H
#define RISCV_CPU_H
-/* QEMU addressing/paging config */
-#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
-#if defined(TARGET_RISCV64)
-#define TARGET_LONG_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
-#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
-#elif defined(TARGET_RISCV32)
-#define TARGET_LONG_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
-#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
-#endif
-
-#define TCG_GUEST_DEFAULT_MO 0
-
-#define CPUArchState struct CPURISCVState
-
#include "qemu-common.h"
#include "qom/cpu.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
+#define TCG_GUEST_DEFAULT_MO 0
+
+#define CPUArchState struct CPURISCVState
+
#define TYPE_RISCV_CPU "riscv-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
@@ -96,7 +84,6 @@ enum {
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
-#define NB_MMU_MODES 4
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
new file mode 100644
index 0000000000..472db648d7
--- /dev/null
+++ b/target/s390x/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * S/390 cpu parameters for qemu.
+ *
+ * Copyright (c) 2009 Ulrich Hecht
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef S390_CPU_PARAM_H
+#define S390_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 64
+#define TARGET_PAGE_BITS 12
+#define TARGET_PHYS_ADDR_SPACE_BITS 64
+#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define NB_MMU_MODES 4
+
+#endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7305cacc7b..3a82ea53e1 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -24,26 +24,17 @@
#include "qemu-common.h"
#include "cpu-qom.h"
#include "cpu_models.h"
-
-#define TARGET_LONG_BITS 64
+#include "exec/cpu-defs.h"
#define ELF_MACHINE_UNAME "S390X"
#define CPUArchState struct CPUS390XState
-#include "exec/cpu-defs.h"
-
/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-#define TARGET_PAGE_BITS 12
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
-
#include "exec/cpu-all.h"
-#define NB_MMU_MODES 4
#define TARGET_INSN_START_EXTRA_WORDS 1
#define MMU_MODE0_SUFFIX _primary
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
new file mode 100644
index 0000000000..81ace3503b
--- /dev/null
+++ b/target/sh4/cpu-param.h
@@ -0,0 +1,21 @@
+/*
+ * SH4 cpu parameters for qemu.
+ *
+ * Copyright (c) 2005 Samuel Tardieu
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef SH4_CPU_PARAM_H
+#define SH4_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12 /* 4k */
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#ifdef CONFIG_USER_ONLY
+# define TARGET_VIRT_ADDR_SPACE_BITS 31
+#else
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 84b08ff640..75d8e1b235 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,8 +22,8 @@
#include "qemu-common.h"
#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
-#define TARGET_LONG_BITS 32
#define ALIGNED_ONLY
/* CPU Subtypes */
@@ -38,17 +38,6 @@
#define CPUArchState struct CPUSH4State
-#include "exec/cpu-defs.h"
-
-#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#ifdef CONFIG_USER_ONLY
-# define TARGET_VIRT_ADDR_SPACE_BITS 31
-#else
-# define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-
#define SR_MD 30
#define SR_RB 29
#define SR_BL 28
@@ -132,7 +121,6 @@ typedef struct tlb_t {
#define UTLB_SIZE 64
#define ITLB_SIZE 4
-#define NB_MMU_MODES 2
#define TARGET_INSN_START_EXTRA_WORDS 1
enum sh_features {
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
new file mode 100644
index 0000000000..4746d89411
--- /dev/null
+++ b/target/sparc/cpu-param.h
@@ -0,0 +1,28 @@
+/*
+ * Sparc cpu parameters for qemu.
+ *
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef SPARC_CPU_PARAM_H
+#define SPARC_CPU_PARAM_H 1
+
+#ifdef TARGET_SPARC64
+# define TARGET_LONG_BITS 64
+# define TARGET_PAGE_BITS 13 /* 8k */
+# define TARGET_PHYS_ADDR_SPACE_BITS 41
+# ifdef TARGET_ABI32
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# else
+# define TARGET_VIRT_ADDR_SPACE_BITS 44
+# endif
+# define NB_MMU_MODES 6
+#else
+# define TARGET_LONG_BITS 32
+# define TARGET_PAGE_BITS 12 /* 4k */
+# define TARGET_PHYS_ADDR_SPACE_BITS 36
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# define NB_MMU_MODES 3
+#endif
+
+#endif
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 85b9665ccc..b11a1bd3fa 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,31 +4,18 @@
#include "qemu-common.h"
#include "qemu/bswap.h"
#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
#define ALIGNED_ONLY
#if !defined(TARGET_SPARC64)
-#define TARGET_LONG_BITS 32
#define TARGET_DPREGS 16
-#define TARGET_PAGE_BITS 12 /* 4k */
-#define TARGET_PHYS_ADDR_SPACE_BITS 36
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
#else
-#define TARGET_LONG_BITS 64
#define TARGET_DPREGS 32
-#define TARGET_PAGE_BITS 13 /* 8k */
-#define TARGET_PHYS_ADDR_SPACE_BITS 41
-# ifdef TARGET_ABI32
-# define TARGET_VIRT_ADDR_SPACE_BITS 32
-# else
-# define TARGET_VIRT_ADDR_SPACE_BITS 44
-# endif
#endif
#define CPUArchState struct CPUSPARCState
-#include "exec/cpu-defs.h"
-
/*#define EXCP_INTERRUPT 0x100*/
/* trap definitions */
@@ -225,10 +212,7 @@ enum {
#define MIN_NWINDOWS 3
#define MAX_NWINDOWS 32
-#if !defined(TARGET_SPARC64)
-#define NB_MMU_MODES 3
-#else
-#define NB_MMU_MODES 6
+#ifdef TARGET_SPARC64
typedef struct trap_state {
uint64_t tpc;
uint64_t tnpc;
diff --git a/target/tilegx/cpu-param.h b/target/tilegx/cpu-param.h
new file mode 100644
index 0000000000..80a341cbb7
--- /dev/null
+++ b/target/tilegx/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * TILE-Gx cpu parameters for qemu.
+ *
+ * Copyright (c) 2015 Chen Gang
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef TILEGX_CPU_PARAM_H
+#define TILEGX_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 64
+#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
+#define TARGET_PHYS_ADDR_SPACE_BITS 42
+#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define NB_MMU_MODES 1
+
+#endif
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 238f8d36d7..429a6c6b43 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -21,13 +21,9 @@
#define TILEGX_CPU_H
#include "qemu-common.h"
-
-#define TARGET_LONG_BITS 64
-
-#define CPUArchState struct CPUTLGState
-
#include "exec/cpu-defs.h"
+#define CPUArchState struct CPUTLGState
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
@@ -154,9 +150,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
-#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
-#define TARGET_PHYS_ADDR_SPACE_BITS 42
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
#include "exec/cpu-all.h"
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
new file mode 100644
index 0000000000..cf5d9af89d
--- /dev/null
+++ b/target/tricore/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * TriCore cpu parameters for qemu.
+ *
+ * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#ifndef TRICORE_CPU_PARAM_H
+#define TRICORE_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 14
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 3
+
+#endif
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 64d1a9c75e..79f5068c25 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -20,10 +20,10 @@
#ifndef TRICORE_CPU_H
#define TRICORE_CPU_H
-#include "tricore-defs.h"
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "tricore-defs.h"
#define CPUArchState struct CPUTriCoreState
@@ -31,8 +31,6 @@ struct CPUTriCoreState;
struct tricore_boot_info;
-#define NB_MMU_MODES 3
-
typedef struct tricore_def_t tricore_def_t;
typedef struct CPUTriCoreState CPUTriCoreState;
diff --git a/target/tricore/tricore-defs.h b/target/tricore/tricore-defs.h
index e871aa1c6b..f5e0a0bed8 100644
--- a/target/tricore/tricore-defs.h
+++ b/target/tricore/tricore-defs.h
@@ -18,11 +18,6 @@
#ifndef QEMU_TRICORE_DEFS_H
#define QEMU_TRICORE_DEFS_H
-#define TARGET_PAGE_BITS 14
-#define TARGET_LONG_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
#define TRICORE_TLB_MAX 128
#endif /* QEMU_TRICORE_DEFS_H */
diff --git a/target/unicore32/cpu-param.h b/target/unicore32/cpu-param.h
new file mode 100644
index 0000000000..94d8a5daa1
--- /dev/null
+++ b/target/unicore32/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * UniCore32 cpu parameters for qemu.
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef UNICORE32_CPU_PARAM_H
+#define UNICORE32_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 24abe5e5c0..e15088eb91 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -12,19 +12,11 @@
#ifndef UNICORE32_CPU_H
#define UNICORE32_CPU_H
-#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 12
-
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
-#define CPUArchState struct CPUUniCore32State
-
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define NB_MMU_MODES 2
+#define CPUArchState struct CPUUniCore32State
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
new file mode 100644
index 0000000000..4fde21b941
--- /dev/null
+++ b/target/xtensa/cpu-param.h
@@ -0,0 +1,21 @@
+/*
+ * Xtensa cpu parameters for qemu.
+ *
+ * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef XTENSA_CPU_PARAM_H
+#define XTENSA_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 12
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#ifdef CONFIG_USER_ONLY
+#define TARGET_VIRT_ADDR_SPACE_BITS 30
+#else
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#endif
+#define NB_MMU_MODES 4
+
+#endif
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 5d23e1345b..970c223cf7 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -28,28 +28,17 @@
#ifndef XTENSA_CPU_H
#define XTENSA_CPU_H
-#define ALIGNED_ONLY
-#define TARGET_LONG_BITS 32
-
-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
-#define CPUArchState struct CPUXtensaState
-
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
-#define NB_MMU_MODES 4
+#define ALIGNED_ONLY
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#ifdef CONFIG_USER_ONLY
-#define TARGET_VIRT_ADDR_SPACE_BITS 30
-#else
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#endif
-#define TARGET_PAGE_BITS 12
+/* Xtensa processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO (0)
+
+#define CPUArchState struct CPUXtensaState
enum {
/* Additional instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 03/39] tcg: Create struct CPUTLB
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 02/39] tcg: Split out target/arch/cpu-param.h Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 04/39] cpu: Define CPUArchState with typedef Richard Henderson
` (35 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/softmmu_template.h | 4 +-
include/exec/cpu-defs.h | 61 ++++++++------
include/exec/cpu_ldst.h | 6 +-
accel/tcg/cputlb.c | 149 ++++++++++++++++++-----------------
target/arm/translate-a64.c | 2 +-
tcg/aarch64/tcg-target.inc.c | 10 +--
tcg/arm/tcg-target.inc.c | 10 +--
tcg/i386/tcg-target.inc.c | 4 +-
tcg/mips/tcg-target.inc.c | 12 +--
tcg/ppc/tcg-target.inc.c | 8 +-
tcg/riscv/tcg-target.inc.c | 12 +--
tcg/s390/tcg-target.inc.c | 8 +-
tcg/sparc/tcg-target.inc.c | 12 +--
13 files changed, 137 insertions(+), 161 deletions(-)
diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h
index e970a8b378..fc6371aed1 100644
--- a/accel/tcg/softmmu_template.h
+++ b/accel/tcg/softmmu_template.h
@@ -102,7 +102,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
bool recheck,
MMUAccessType access_type)
{
- CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck,
access_type, DATA_SIZE);
}
@@ -273,7 +273,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
uintptr_t retaddr,
bool recheck)
{
- CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
+ CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr,
recheck, DATA_SIZE);
}
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 2694481769..fbe8945606 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -78,6 +78,7 @@ typedef uint64_t target_ulong;
#endif
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+
/* use a fully associative victim tlb of 8 entries */
#define CPU_VTLB_SIZE 8
@@ -147,6 +148,10 @@ typedef struct CPUIOTLBEntry {
MemTxAttrs attrs;
} CPUIOTLBEntry;
+/*
+ * Data elements that are per MMU mode, minus the bits accessed by
+ * the TCG fast path.
+ */
typedef struct CPUTLBDesc {
/*
* Describe a region covering all of the large pages allocated
@@ -160,16 +165,31 @@ typedef struct CPUTLBDesc {
int64_t window_begin_ns;
/* maximum number of entries observed in the window */
size_t window_max_entries;
+ size_t n_used_entries;
/* The next index to use in the tlb victim table. */
size_t vindex;
- size_t n_used_entries;
+ /* The tlb victim table, in two parts. */
+ CPUTLBEntry vtable[CPU_VTLB_SIZE];
+ CPUIOTLBEntry viotlb[CPU_VTLB_SIZE];
+ /* The iotlb. */
+ CPUIOTLBEntry *iotlb;
} CPUTLBDesc;
+/*
+ * Data elements that are per MMU mode, accessed by the fast path.
+ */
+typedef struct CPUTLBDescFast {
+ /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
+ uintptr_t mask;
+ /* The array of tlb entries itself. */
+ CPUTLBEntry *table;
+} CPUTLBDescFast;
+
/*
* Data elements that are shared between all MMU modes.
*/
typedef struct CPUTLBCommon {
- /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */
+ /* Serialize updates to tlb_table and vtable, and others as noted. */
QemuSpin lock;
/*
* Within dirty, for each bit N, modifications have been made to
@@ -187,35 +207,24 @@ typedef struct CPUTLBCommon {
size_t elide_flush_count;
} CPUTLBCommon;
-# define CPU_TLB \
- /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ \
- uintptr_t tlb_mask[NB_MMU_MODES]; \
- CPUTLBEntry *tlb_table[NB_MMU_MODES];
-# define CPU_IOTLB \
- CPUIOTLBEntry *iotlb[NB_MMU_MODES];
-
/*
+ * The entire softmmu tlb, for all MMU modes.
* The meaning of each of the MMU modes is defined in the target code.
- * Note that NB_MMU_MODES is not yet defined; we can only reference it
- * within preprocessor defines that will be expanded later.
*/
-#define CPU_COMMON_TLB \
- CPUTLBCommon tlb_c; \
- CPUTLBDesc tlb_d[NB_MMU_MODES]; \
- CPU_TLB \
- CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
- CPU_IOTLB \
- CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE];
+typedef struct CPUTLB {
+ CPUTLBDescFast f[NB_MMU_MODES];
+ CPUTLBDesc d[NB_MMU_MODES];
+ CPUTLBCommon c;
+} CPUTLB;
+
+/* There are target-specific members named "tlb". This is temporary. */
+#define CPU_COMMON CPUTLB tlb_;
+#define env_tlb(ENV) (&(ENV)->tlb_)
#else
-#define CPU_COMMON_TLB
-
-#endif
-
-
-#define CPU_COMMON \
- /* soft mmu support */ \
- CPU_COMMON_TLB \
+#define CPU_COMMON /* Nothing */
+
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
#endif
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index d78041d7a0..09abd95008 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -139,21 +139,21 @@ static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
target_ulong addr)
{
- uintptr_t size_mask = env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS;
+ uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
return (addr >> TARGET_PAGE_BITS) & size_mask;
}
static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx)
{
- return (env->tlb_mask[mmu_idx] >> CPU_TLB_ENTRY_BITS) + 1;
+ return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1;
}
/* Find the TLB entry corresponding to the mmu_idx + address pair. */
static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
target_ulong addr)
{
- return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)];
+ return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
}
#ifdef MMU_MODE0_SUFFIX
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c7593235c..2225640fc1 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -76,7 +76,7 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
{
- return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS);
+ return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS);
}
static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
@@ -91,14 +91,14 @@ static void tlb_dyn_init(CPUArchState *env)
int i;
for (i = 0; i < NB_MMU_MODES; i++) {
- CPUTLBDesc *desc = &env->tlb_d[i];
+ CPUTLBDesc *desc = &env_tlb(env)->d[i];
size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
tlb_window_reset(desc, get_clock_realtime(), 0);
desc->n_used_entries = 0;
- env->tlb_mask[i] = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
- env->tlb_table[i] = g_new(CPUTLBEntry, n_entries);
- env->iotlb[i] = g_new(CPUIOTLBEntry, n_entries);
+ env_tlb(env)->f[i].mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
+ env_tlb(env)->f[i].table = g_new(CPUTLBEntry, n_entries);
+ env_tlb(env)->d[i].iotlb = g_new(CPUIOTLBEntry, n_entries);
}
}
@@ -144,7 +144,7 @@ static void tlb_dyn_init(CPUArchState *env)
*/
static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
{
- CPUTLBDesc *desc = &env->tlb_d[mmu_idx];
+ CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx];
size_t old_size = tlb_n_entries(env, mmu_idx);
size_t rate;
size_t new_size = old_size;
@@ -187,14 +187,14 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
return;
}
- g_free(env->tlb_table[mmu_idx]);
- g_free(env->iotlb[mmu_idx]);
+ g_free(env_tlb(env)->f[mmu_idx].table);
+ g_free(env_tlb(env)->d[mmu_idx].iotlb);
tlb_window_reset(desc, now, 0);
/* desc->n_used_entries is cleared by the caller */
- env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS;
- env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size);
- env->iotlb[mmu_idx] = g_try_new(CPUIOTLBEntry, new_size);
+ env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
+ env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);
+ env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);
/*
* If the allocations fail, try smaller sizes. We just freed some
* memory, so going back to half of new_size has a good chance of working.
@@ -202,46 +202,47 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
* allocations to fail though, so we progressively reduce the allocation
* size, aborting if we cannot even allocate the smallest TLB we support.
*/
- while (env->tlb_table[mmu_idx] == NULL || env->iotlb[mmu_idx] == NULL) {
+ while (env_tlb(env)->f[mmu_idx].table == NULL ||
+ env_tlb(env)->d[mmu_idx].iotlb == NULL) {
if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
error_report("%s: %s", __func__, strerror(errno));
abort();
}
new_size = MAX(new_size >> 1, 1 << CPU_TLB_DYN_MIN_BITS);
- env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS;
+ env_tlb(env)->f[mmu_idx].mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
- g_free(env->tlb_table[mmu_idx]);
- g_free(env->iotlb[mmu_idx]);
- env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size);
- env->iotlb[mmu_idx] = g_try_new(CPUIOTLBEntry, new_size);
+ g_free(env_tlb(env)->f[mmu_idx].table);
+ g_free(env_tlb(env)->d[mmu_idx].iotlb);
+ env_tlb(env)->f[mmu_idx].table = g_try_new(CPUTLBEntry, new_size);
+ env_tlb(env)->d[mmu_idx].iotlb = g_try_new(CPUIOTLBEntry, new_size);
}
}
static inline void tlb_table_flush_by_mmuidx(CPUArchState *env, int mmu_idx)
{
tlb_mmu_resize_locked(env, mmu_idx);
- memset(env->tlb_table[mmu_idx], -1, sizeof_tlb(env, mmu_idx));
- env->tlb_d[mmu_idx].n_used_entries = 0;
+ memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx));
+ env_tlb(env)->d[mmu_idx].n_used_entries = 0;
}
static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu_idx)
{
- env->tlb_d[mmu_idx].n_used_entries++;
+ env_tlb(env)->d[mmu_idx].n_used_entries++;
}
static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu_idx)
{
- env->tlb_d[mmu_idx].n_used_entries--;
+ env_tlb(env)->d[mmu_idx].n_used_entries--;
}
void tlb_init(CPUState *cpu)
{
CPUArchState *env = cpu->env_ptr;
- qemu_spin_init(&env->tlb_c.lock);
+ qemu_spin_init(&env_tlb(env)->c.lock);
/* Ensure that cpu_reset performs a full flush. */
- env->tlb_c.dirty = ALL_MMUIDX_BITS;
+ env_tlb(env)->c.dirty = ALL_MMUIDX_BITS;
tlb_dyn_init(env);
}
@@ -273,9 +274,9 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide)
CPU_FOREACH(cpu) {
CPUArchState *env = cpu->env_ptr;
- full += atomic_read(&env->tlb_c.full_flush_count);
- part += atomic_read(&env->tlb_c.part_flush_count);
- elide += atomic_read(&env->tlb_c.elide_flush_count);
+ full += atomic_read(&env_tlb(env)->c.full_flush_count);
+ part += atomic_read(&env_tlb(env)->c.part_flush_count);
+ elide += atomic_read(&env_tlb(env)->c.elide_flush_count);
}
*pfull = full;
*ppart = part;
@@ -285,10 +286,11 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide)
static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx)
{
tlb_table_flush_by_mmuidx(env, mmu_idx);
- memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
- env->tlb_d[mmu_idx].large_page_addr = -1;
- env->tlb_d[mmu_idx].large_page_mask = -1;
- env->tlb_d[mmu_idx].vindex = 0;
+ env_tlb(env)->d[mmu_idx].large_page_addr = -1;
+ env_tlb(env)->d[mmu_idx].large_page_mask = -1;
+ env_tlb(env)->d[mmu_idx].vindex = 0;
+ memset(env_tlb(env)->d[mmu_idx].vtable, -1,
+ sizeof(env_tlb(env)->d[0].vtable));
}
static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
@@ -301,31 +303,31 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked);
- qemu_spin_lock(&env->tlb_c.lock);
+ qemu_spin_lock(&env_tlb(env)->c.lock);
- all_dirty = env->tlb_c.dirty;
+ all_dirty = env_tlb(env)->c.dirty;
to_clean = asked & all_dirty;
all_dirty &= ~to_clean;
- env->tlb_c.dirty = all_dirty;
+ env_tlb(env)->c.dirty = all_dirty;
for (work = to_clean; work != 0; work &= work - 1) {
int mmu_idx = ctz32(work);
tlb_flush_one_mmuidx_locked(env, mmu_idx);
}
- qemu_spin_unlock(&env->tlb_c.lock);
+ qemu_spin_unlock(&env_tlb(env)->c.lock);
cpu_tb_jmp_cache_clear(cpu);
if (to_clean == ALL_MMUIDX_BITS) {
- atomic_set(&env->tlb_c.full_flush_count,
- env->tlb_c.full_flush_count + 1);
+ atomic_set(&env_tlb(env)->c.full_flush_count,
+ env_tlb(env)->c.full_flush_count + 1);
} else {
- atomic_set(&env->tlb_c.part_flush_count,
- env->tlb_c.part_flush_count + ctpop16(to_clean));
+ atomic_set(&env_tlb(env)->c.part_flush_count,
+ env_tlb(env)->c.part_flush_count + ctpop16(to_clean));
if (to_clean != asked) {
- atomic_set(&env->tlb_c.elide_flush_count,
- env->tlb_c.elide_flush_count +
+ atomic_set(&env_tlb(env)->c.elide_flush_count,
+ env_tlb(env)->c.elide_flush_count +
ctpop16(asked & ~to_clean));
}
}
@@ -410,11 +412,12 @@ static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry,
static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
target_ulong page)
{
+ CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx];
int k;
assert_cpu_is_self(ENV_GET_CPU(env));
for (k = 0; k < CPU_VTLB_SIZE; k++) {
- if (tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page)) {
+ if (tlb_flush_entry_locked(&d->vtable[k], page)) {
tlb_n_used_entries_dec(env, mmu_idx);
}
}
@@ -423,8 +426,8 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
static void tlb_flush_page_locked(CPUArchState *env, int midx,
target_ulong page)
{
- target_ulong lp_addr = env->tlb_d[midx].large_page_addr;
- target_ulong lp_mask = env->tlb_d[midx].large_page_mask;
+ target_ulong lp_addr = env_tlb(env)->d[midx].large_page_addr;
+ target_ulong lp_mask = env_tlb(env)->d[midx].large_page_mask;
/* Check if we need to flush due to large pages. */
if ((page & lp_mask) == lp_addr) {
@@ -459,13 +462,13 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu,
tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n",
addr, mmu_idx_bitmap);
- qemu_spin_lock(&env->tlb_c.lock);
+ qemu_spin_lock(&env_tlb(env)->c.lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
tlb_flush_page_locked(env, mmu_idx, addr);
}
}
- qemu_spin_unlock(&env->tlb_c.lock);
+ qemu_spin_unlock(&env_tlb(env)->c.lock);
tb_flush_jmp_cache(cpu, addr);
}
@@ -609,22 +612,22 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
int mmu_idx;
env = cpu->env_ptr;
- qemu_spin_lock(&env->tlb_c.lock);
+ qemu_spin_lock(&env_tlb(env)->c.lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
unsigned int i;
unsigned int n = tlb_n_entries(env, mmu_idx);
for (i = 0; i < n; i++) {
- tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], start1,
- length);
+ tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i],
+ start1, length);
}
for (i = 0; i < CPU_VTLB_SIZE; i++) {
- tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], start1,
- length);
+ tlb_reset_dirty_range_locked(&env_tlb(env)->d[mmu_idx].vtable[i],
+ start1, length);
}
}
- qemu_spin_unlock(&env->tlb_c.lock);
+ qemu_spin_unlock(&env_tlb(env)->c.lock);
}
/* Called with tlb_c.lock held */
@@ -646,7 +649,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
assert_cpu_is_self(cpu);
vaddr &= TARGET_PAGE_MASK;
- qemu_spin_lock(&env->tlb_c.lock);
+ qemu_spin_lock(&env_tlb(env)->c.lock);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr);
}
@@ -654,10 +657,10 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
int k;
for (k = 0; k < CPU_VTLB_SIZE; k++) {
- tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr);
+ tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], vaddr);
}
}
- qemu_spin_unlock(&env->tlb_c.lock);
+ qemu_spin_unlock(&env_tlb(env)->c.lock);
}
/* Our TLB does not support large pages, so remember the area covered by
@@ -665,7 +668,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
target_ulong vaddr, target_ulong size)
{
- target_ulong lp_addr = env->tlb_d[mmu_idx].large_page_addr;
+ target_ulong lp_addr = env_tlb(env)->d[mmu_idx].large_page_addr;
target_ulong lp_mask = ~(size - 1);
if (lp_addr == (target_ulong)-1) {
@@ -675,13 +678,13 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
/* Extend the existing region to include the new page.
This is a compromise between unnecessary flushes and
the cost of maintaining a full variable size TLB. */
- lp_mask &= env->tlb_d[mmu_idx].large_page_mask;
+ lp_mask &= env_tlb(env)->d[mmu_idx].large_page_mask;
while (((lp_addr ^ vaddr) & lp_mask) != 0) {
lp_mask <<= 1;
}
}
- env->tlb_d[mmu_idx].large_page_addr = lp_addr & lp_mask;
- env->tlb_d[mmu_idx].large_page_mask = lp_mask;
+ env_tlb(env)->d[mmu_idx].large_page_addr = lp_addr & lp_mask;
+ env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
}
/* Add a new TLB entry. At most one entry for a given virtual address
@@ -696,6 +699,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
int mmu_idx, target_ulong size)
{
CPUArchState *env = cpu->env_ptr;
+ CPUTLB *tlb = env_tlb(env);
+ CPUTLBDesc *desc = &tlb->d[mmu_idx];
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
@@ -757,10 +762,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
* a longer critical section, but this is not a concern since the TLB lock
* is unlikely to be contended.
*/
- qemu_spin_lock(&env->tlb_c.lock);
+ qemu_spin_lock(&tlb->c.lock);
/* Note that the tlb is no longer clean. */
- env->tlb_c.dirty |= 1 << mmu_idx;
+ tlb->c.dirty |= 1 << mmu_idx;
/* Make sure there's no cached translation for the new page. */
tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page);
@@ -770,12 +775,12 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
* different page; otherwise just overwrite the stale data.
*/
if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) {
- unsigned vidx = env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE;
- CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx];
+ unsigned vidx = desc->vindex++ % CPU_VTLB_SIZE;
+ CPUTLBEntry *tv = &desc->vtable[vidx];
/* Evict the old entry into the victim tlb. */
copy_tlb_helper_locked(tv, te);
- env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
+ desc->viotlb[vidx] = desc->iotlb[index];
tlb_n_used_entries_dec(env, mmu_idx);
}
@@ -792,8 +797,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
* subtract here is that of the page base, and not the same as the
* vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
*/
- env->iotlb[mmu_idx][index].addr = iotlb - vaddr_page;
- env->iotlb[mmu_idx][index].attrs = attrs;
+ desc->iotlb[index].addr = iotlb - vaddr_page;
+ desc->iotlb[index].attrs = attrs;
/* Now calculate the new entry */
tn.addend = addend - vaddr_page;
@@ -829,7 +834,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
copy_tlb_helper_locked(te, &tn);
tlb_n_used_entries_inc(env, mmu_idx);
- qemu_spin_unlock(&env->tlb_c.lock);
+ qemu_spin_unlock(&tlb->c.lock);
}
/* Add a new TLB entry, but without specifying the memory
@@ -997,7 +1002,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
assert_cpu_is_self(ENV_GET_CPU(env));
for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
- CPUTLBEntry *vtlb = &env->tlb_v_table[mmu_idx][vidx];
+ CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx];
target_ulong cmp;
/* elt_ofs might correspond to .addr_write, so use atomic_read */
@@ -1009,16 +1014,16 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
if (cmp == page) {
/* Found entry in victim tlb, swap tlb and iotlb. */
- CPUTLBEntry tmptlb, *tlb = &env->tlb_table[mmu_idx][index];
+ CPUTLBEntry tmptlb, *tlb = &env_tlb(env)->f[mmu_idx].table[index];
- qemu_spin_lock(&env->tlb_c.lock);
+ qemu_spin_lock(&env_tlb(env)->c.lock);
copy_tlb_helper_locked(&tmptlb, tlb);
copy_tlb_helper_locked(tlb, vtlb);
copy_tlb_helper_locked(vtlb, &tmptlb);
- qemu_spin_unlock(&env->tlb_c.lock);
+ qemu_spin_unlock(&env_tlb(env)->c.lock);
- CPUIOTLBEntry tmpio, *io = &env->iotlb[mmu_idx][index];
- CPUIOTLBEntry *vio = &env->iotlb_v[mmu_idx][vidx];
+ CPUIOTLBEntry tmpio, *io = &env_tlb(env)->d[mmu_idx].iotlb[index];
+ CPUIOTLBEntry *vio = &env_tlb(env)->d[mmu_idx].viotlb[vidx];
tmpio = *io; *io = *vio; *vio = tmpio;
return true;
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 9dcc5ff3a3..d0fefa798e 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14163,7 +14163,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
* table entry even for that case.
*/
return (tlb_hit(entry->addr_code, addr) &&
- env->iotlb[mmu_idx][index].attrs.target_tlb_bit0);
+ env_tlb(env)->d[mmu_idx].iotlb[index].attrs.target_tlb_bit0);
#endif
}
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index eefa929948..72cf4c5ff8 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1455,12 +1455,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
label->label_ptr[0] = label_ptr;
}
-/* We expect tlb_mask to be before tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
- offsetof(CPUArchState, tlb_mask));
-
/* We expect to use a 24-bit unsigned offset from ENV. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1])
+QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
> 0xffffff);
/* Load and compare a TLB entry, emitting the conditional jump to the
@@ -1471,8 +1467,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
tcg_insn_unit **label_ptr, int mem_index,
bool is_read)
{
- int mask_ofs = offsetof(CPUArchState, tlb_mask[mem_index]);
- int table_ofs = offsetof(CPUArchState, tlb_table[mem_index]);
+ int mask_ofs = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int table_ofs = offsetof(CPUArchState, tlb_.f[mem_index].table);
unsigned a_bits = get_alignment_bits(opc);
unsigned s_bits = opc & MO_SIZE;
unsigned a_mask = (1u << a_bits) - 1;
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index abf0c444b4..28b911e550 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1220,12 +1220,8 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
-/* We expect tlb_mask to be before tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
- offsetof(CPUArchState, tlb_mask));
-
/* We expect to use a 20-bit unsigned offset from ENV. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1])
+QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
> 0xfffff);
/* Load and compare a TLB entry, leaving the flags set. Returns the register
@@ -1236,8 +1232,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
{
int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
- int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
- int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
+ int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index d5ed9f1ffd..b2e11a4b7c 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -1655,10 +1655,10 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
- offsetof(CPUArchState, tlb_mask[mem_index]));
+ offsetof(CPUArchState, tlb_.f[mem_index].mask));
tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
- offsetof(CPUArchState, tlb_table[mem_index]));
+ offsetof(CPUArchState, tlb_.f[mem_index].table));
/* If the required alignment is at least as large as the access, simply
copy the address and mask. For lesser alignments, check that we don't
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 412cacdcb9..45b26e596f 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1201,14 +1201,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
return i;
}
-/* We expect tlb_mask to be before tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
- offsetof(CPUArchState, tlb_mask));
-
-/* We expect tlb_mask to be "near" tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) -
- offsetof(CPUArchState, tlb_mask) >= 0x8000);
-
/*
* Perform the tlb comparison operation.
* The complete host address is placed in BASE.
@@ -1222,8 +1214,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
int mem_index = get_mmuidx(oi);
- int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
- int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
+ int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int table_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
int add_off = offsetof(CPUTLBEntry, addend);
int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 36b4791707..a248603bc5 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -1497,10 +1497,6 @@ static void * const qemu_st_helpers[16] = {
[MO_BEQ] = helper_be_stq_mmu,
};
-/* We expect tlb_mask to be before tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
- offsetof(CPUArchState, tlb_mask));
-
/* Perform the TLB load and compare. Places the result of the comparison
in CR7, loads the addend of the TLB into R3, and returns the register
containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
@@ -1513,8 +1509,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
= (is_read
? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
- int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
- int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
+ int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 2932505094..85acbb9514 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -961,14 +961,6 @@ static void * const qemu_st_helpers[16] = {
/* We don't support oversize guests */
QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
-/* We expect tlb_mask to be before tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
- offsetof(CPUArchState, tlb_mask));
-
-/* We expect tlb_mask to be "near" tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) -
- offsetof(CPUArchState, tlb_mask) >= 0x800);
-
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
TCGReg addrh, TCGMemOpIdx oi,
tcg_insn_unit **label_ptr, bool is_load)
@@ -981,8 +973,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
int mask_off, table_off;
TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
- mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
- table_off = offsetof(CPUArchState, tlb_table[mem_index]);
+ mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
if (table_off > 0x7ff) {
int mask_hi = mask_off - sextreg(mask_off, 0, 12);
int table_hi = table_off - sextreg(table_off, 0, 12);
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 3d6150b10e..1f578ea980 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1538,9 +1538,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
#include "tcg-ldst.inc.c"
/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_mask[NB_MMU_MODES - 1])
- > 0x7ffff);
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1])
+QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
> 0x7ffff);
/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
@@ -1552,8 +1550,8 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
unsigned a_bits = get_alignment_bits(opc);
unsigned s_mask = (1 << s_bits) - 1;
unsigned a_mask = (1 << a_bits) - 1;
- int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
- int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
+ int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
int ofs, a_off;
uint64_t tlb_mask;
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 7a61839dc1..be10124e11 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1074,19 +1074,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
The result of the TLB comparison is in %[ix]cc. The sanitized address
is in the returned register, maybe %o0. The TLB addend is in %o1. */
-/* We expect tlb_mask to be before tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
- offsetof(CPUArchState, tlb_mask));
-
-/* We expect tlb_mask to be "near" tlb_table. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) -
- offsetof(CPUArchState, tlb_mask) >= (1 << 13));
-
static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
TCGMemOp opc, int which)
{
- int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
- int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
+ int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
TCGReg base = TCG_AREG0;
const TCGReg r0 = TCG_REG_O0;
const TCGReg r1 = TCG_REG_O1;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 04/39] cpu: Define CPUArchState with typedef
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (2 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 03/39] tcg: Create struct CPUTLB Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 05/39] cpu: Define ArchCPU Richard Henderson
` (34 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.h | 4 ++--
target/arm/cpu.h | 4 ++--
target/cris/cpu.h | 4 ++--
target/hppa/cpu.h | 4 ++--
target/i386/cpu.h | 5 ++---
target/lm32/cpu.h | 5 ++---
target/m68k/cpu.h | 4 ++--
target/microblaze/cpu.h | 5 ++---
target/mips/cpu.h | 6 ++----
target/moxie/cpu.h | 4 ++--
target/nios2/cpu.h | 5 ++---
target/openrisc/cpu.h | 4 ++--
target/ppc/cpu.h | 4 ++--
target/riscv/cpu.h | 4 ++--
target/s390x/cpu.h | 8 ++++----
target/sh4/cpu.h | 4 ++--
target/sparc/cpu.h | 4 ++--
target/tilegx/cpu.h | 4 ++--
target/tricore/cpu.h | 6 +-----
target/unicore32/cpu.h | 4 ++--
target/xtensa/cpu.h | 4 ++--
21 files changed, 43 insertions(+), 53 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 2ab468ffd6..56d1eade4f 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -26,8 +26,6 @@
#define ALIGNED_ONLY
-#define CPUArchState struct CPUAlphaState
-
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
@@ -301,6 +299,8 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
#define cpu_list alpha_cpu_list
#define cpu_signal_handler cpu_alpha_signal_handler
+typedef CPUAlphaState CPUArchState;
+
#include "exec/cpu-all.h"
enum {
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ca199d1afb..9b4874112f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -29,8 +29,6 @@
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
-#define CPUArchState struct CPUARMState
-
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
#define EXCP_PREFETCH_ABORT 3
@@ -3114,6 +3112,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
}
+typedef CPUARMState CPUArchState;
+
#include "exec/cpu-all.h"
/* Bit usage in the TB flags field: bit 31 indicates whether we are
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 3fbe1232ab..94e1a2aed7 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -25,8 +25,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define CPUArchState struct CPUCRISState
-
#define EXCP_NMI 1
#define EXCP_GURU 2
#define EXCP_BUSFAULT 3
@@ -285,6 +283,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
+typedef CPUCRISState CPUArchState;
+
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index f96c3a17e4..c9bb16af9b 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -31,8 +31,6 @@
basis. It's probably easier to fall back to a strong memory model. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-#define CPUArchState struct CPUHPPAState
-
#define ALIGNED_ONLY
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
@@ -232,6 +230,8 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e))
#define ENV_OFFSET offsetof(HPPACPU, env)
+typedef CPUHPPAState CPUArchState;
+
#include "exec/cpu-all.h"
static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e53dbdeee5..2ccd796e9b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1,4 +1,3 @@
-
/*
* i386 virtual CPU header
*
@@ -44,8 +43,6 @@
#define ELF_MACHINE_UNAME "i686"
#endif
-#define CPUArchState struct CPUX86State
-
enum {
R_EAX = 0,
R_ECX = 1,
@@ -1753,6 +1750,8 @@ static inline target_long lshift(target_long x, int n)
/* translate.c */
void tcg_x86_init(void);
+typedef CPUX86State CPUArchState;
+
#include "exec/cpu-all.h"
#include "svm.h"
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 79852dda5a..bd23c39d7a 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -24,9 +24,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define CPUArchState struct CPULM32State
-
-struct CPULM32State;
typedef struct CPULM32State CPULM32State;
static inline int cpu_mmu_index(CPULM32State *env, bool ifetch)
@@ -258,6 +255,8 @@ bool lm32_cpu_do_semihosting(CPUState *cs);
int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
int mmu_idx);
+typedef CPULM32State CPUArchState;
+
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index bad85174ca..2f92972dca 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -25,8 +25,6 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
-#define CPUArchState struct CPUM68KState
-
#define OS_BYTE 0
#define OS_WORD 1
#define OS_LONG 2
@@ -536,6 +534,8 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
bool is_write, bool is_exec, int is_asi,
unsigned size);
+typedef CPUM68KState CPUArchState;
+
#include "exec/cpu-all.h"
/* TB flags */
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 406dc0b5a3..ac3e785927 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -25,9 +25,6 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
-#define CPUArchState struct CPUMBState
-
-struct CPUMBState;
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
@@ -367,6 +364,8 @@ static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
int mmu_idx);
+typedef CPUMBState CPUArchState;
+
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b97b018399..522d2ebadc 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -3,8 +3,6 @@
#define ALIGNED_ONLY
-#define CPUArchState struct CPUMIPSState
-
#include "qemu-common.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
@@ -13,8 +11,6 @@
#define TCG_GUEST_DEFAULT_MO (0)
-struct CPUMIPSState;
-
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
/* MSA Context */
@@ -1094,6 +1090,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
+typedef CPUMIPSState CPUArchState;
+
#include "exec/cpu-all.h"
/* Memory access type :
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index fcb2ea76b7..dcc319adf6 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -23,8 +23,6 @@
#include "qemu-common.h"
#include "exec/cpu-defs.h"
-#define CPUArchState struct CPUMoxieState
-
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
#define MOXIE_EX_IRQ 2
@@ -119,6 +117,8 @@ static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch)
return 0;
}
+typedef CPUMoxieState CPUArchState;
+
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index b737b23fc5..915ddd386f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -24,9 +24,6 @@
#include "exec/cpu-defs.h"
#include "qom/cpu.h"
-#define CPUArchState struct CPUNios2State
-
-struct CPUNios2State;
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
@@ -247,6 +244,8 @@ static inline int cpu_interrupts_enabled(CPUNios2State *env)
return env->regs[CR_STATUS] & CR_STATUS_PIE;
}
+typedef CPUNios2State CPUArchState;
+
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index bf8a354307..e327c81703 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -24,8 +24,6 @@
#include "exec/cpu-defs.h"
#include "qom/cpu.h"
-#define CPUArchState struct CPUOpenRISCState
-
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
@@ -364,6 +362,8 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
+typedef CPUOpenRISCState CPUArchState;
+
#include "exec/cpu-all.h"
#define TB_FLAGS_SM SR_SM
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e86f1650d5..2bf526403e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -34,8 +34,6 @@
#define TARGET_PAGE_BITS_64K 16
#define TARGET_PAGE_BITS_16M 24
-#define CPUArchState struct CPUPPCState
-
#if defined(TARGET_PPC64)
#define PPC_ELF_MACHINE EM_PPC64
#else
@@ -1378,6 +1376,8 @@ void ppc_compat_add_property(Object *obj, const char *name,
Error **errp);
#endif /* defined(TARGET_PPC64) */
+typedef CPUPPCState CPUArchState;
+
#include "exec/cpu-all.h"
/*****************************************************************************/
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8f480de324..0f7124132e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -27,8 +27,6 @@
#define TCG_GUEST_DEFAULT_MO 0
-#define CPUArchState struct CPURISCVState
-
#define TYPE_RISCV_CPU "riscv-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
@@ -325,6 +323,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
+typedef CPURISCVState CPUArchState;
+
#include "exec/cpu-all.h"
#endif /* RISCV_CPU_H */
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 3a82ea53e1..5ca53f48f8 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,13 +28,9 @@
#define ELF_MACHINE_UNAME "S390X"
-#define CPUArchState struct CPUS390XState
-
/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-#include "exec/cpu-all.h"
-
#define TARGET_INSN_START_EXTRA_WORDS 1
#define MMU_MODE0_SUFFIX _primary
@@ -797,4 +793,8 @@ void s390_init_sigp(void);
/* outside of target/s390x/ */
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
+typedef CPUS390XState CPUArchState;
+
+#include "exec/cpu-all.h"
+
#endif
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 75d8e1b235..4df8cb0471 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -36,8 +36,6 @@
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
-#define CPUArchState struct CPUSH4State
-
#define SR_MD 30
#define SR_RB 29
#define SR_BL 28
@@ -281,6 +279,8 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
}
}
+typedef CPUSH4State CPUArchState;
+
#include "exec/cpu-all.h"
/* Memory access type */
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index b11a1bd3fa..620bb74329 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -14,8 +14,6 @@
#define TARGET_DPREGS 32
#endif
-#define CPUArchState struct CPUSPARCState
-
/*#define EXCP_INTERRUPT 0x100*/
/* trap definitions */
@@ -730,6 +728,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
#endif
}
+typedef CPUSPARCState CPUArchState;
+
#include "exec/cpu-all.h"
#ifdef TARGET_SPARC64
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 429a6c6b43..2fbf14d508 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -23,8 +23,6 @@
#include "qemu-common.h"
#include "exec/cpu-defs.h"
-#define CPUArchState struct CPUTLGState
-
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
@@ -152,6 +150,8 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
/* TILE-Gx memory attributes */
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
+typedef CPUTLGState CPUArchState;
+
#include "exec/cpu-all.h"
void tilegx_tcg_init(void);
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 79f5068c25..39376e4e1e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -25,10 +25,6 @@
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
-#define CPUArchState struct CPUTriCoreState
-
-struct CPUTriCoreState;
-
struct tricore_boot_info;
typedef struct tricore_def_t tricore_def_t;
@@ -382,7 +378,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
-
+typedef CPUTriCoreState CPUArchState;
#include "exec/cpu-all.h"
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index e15088eb91..6d7439b368 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -16,8 +16,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
-#define CPUArchState struct CPUUniCore32State
-
typedef struct CPUUniCore32State {
/* Regs for current mode. */
uint32_t regs[32];
@@ -153,6 +151,8 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
}
+typedef CPUUniCore32State CPUArchState;
+
#include "exec/cpu-all.h"
#define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 970c223cf7..979a5fde7e 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -38,8 +38,6 @@
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
-#define CPUArchState struct CPUXtensaState
-
enum {
/* Additional instructions */
XTENSA_OPTION_CODE_DENSITY,
@@ -788,6 +786,8 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
}
}
+typedef CPUXtensaState CPUArchState;
+
#include "exec/cpu-all.h"
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 05/39] cpu: Define ArchCPU
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (3 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 04/39] cpu: Define CPUArchState with typedef Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 06/39] cpu: Replace ENV_GET_CPU with env_cpu Richard Henderson
` (33 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
For all targets, do this just before including exec/cpu-all.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.h | 1 +
target/arm/cpu.h | 1 +
target/cris/cpu.h | 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/lm32/cpu.h | 1 +
target/m68k/cpu.h | 1 +
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 1 +
target/moxie/cpu.h | 1 +
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 1 +
target/ppc/cpu.h | 1 +
target/riscv/cpu.h | 1 +
target/s390x/cpu.h | 1 +
target/sh4/cpu.h | 1 +
target/sparc/cpu.h | 1 +
target/tilegx/cpu.h | 1 +
target/tricore/cpu.h | 1 +
target/unicore32/cpu.h | 1 +
target/xtensa/cpu.h | 1 +
21 files changed, 21 insertions(+)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 56d1eade4f..ce470b9089 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -300,6 +300,7 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
#define cpu_signal_handler cpu_alpha_signal_handler
typedef CPUAlphaState CPUArchState;
+typedef AlphaCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9b4874112f..d943bb0fed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3113,6 +3113,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
typedef CPUARMState CPUArchState;
+typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 94e1a2aed7..9f1fbd2f81 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -284,6 +284,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
typedef CPUCRISState CPUArchState;
+typedef CRISCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index c9bb16af9b..9038fa3c13 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -231,6 +231,7 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState;
+typedef HPPACPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2ccd796e9b..6bd01ebb83 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1751,6 +1751,7 @@ static inline target_long lshift(target_long x, int n)
void tcg_x86_init(void);
typedef CPUX86State CPUArchState;
+typedef X86CPU ArchCPU;
#include "exec/cpu-all.h"
#include "svm.h"
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index bd23c39d7a..9132397066 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -256,6 +256,7 @@ int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
int mmu_idx);
typedef CPULM32State CPUArchState;
+typedef LM32CPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 2f92972dca..ce0f93343b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -535,6 +535,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
unsigned size);
typedef CPUM68KState CPUArchState;
+typedef M68kCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index ac3e785927..161d18546d 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -365,6 +365,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
int mmu_idx);
typedef CPUMBState CPUArchState;
+typedef MicroBlazeCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 522d2ebadc..3fdd075f8e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1091,6 +1091,7 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
}
typedef CPUMIPSState CPUArchState;
+typedef MIPSCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index dcc319adf6..8691185162 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -118,6 +118,7 @@ static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch)
}
typedef CPUMoxieState CPUArchState;
+typedef MoxieCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 915ddd386f..fce08e3575 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -245,6 +245,7 @@ static inline int cpu_interrupts_enabled(CPUNios2State *env)
}
typedef CPUNios2State CPUArchState;
+typedef Nios2CPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index e327c81703..a6abcc7d2c 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -363,6 +363,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
typedef CPUOpenRISCState CPUArchState;
+typedef OpenRISCCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2bf526403e..a2134fe83a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1377,6 +1377,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#endif /* defined(TARGET_PPC64) */
typedef CPUPPCState CPUArchState;
+typedef PowerPCCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0f7124132e..4cf4516cc3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -324,6 +324,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
typedef CPURISCVState CPUArchState;
+typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5ca53f48f8..6d1b0f273a 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -794,6 +794,7 @@ void s390_init_sigp(void);
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
typedef CPUS390XState CPUArchState;
+typedef S390CPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 4df8cb0471..8b175c58b4 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -280,6 +280,7 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
}
typedef CPUSH4State CPUArchState;
+typedef SuperHCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 620bb74329..5a108b5532 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -729,6 +729,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
}
typedef CPUSPARCState CPUArchState;
+typedef SPARCCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 2fbf14d508..042a7a0c71 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -151,6 +151,7 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
typedef CPUTLGState CPUArchState;
+typedef TileGXCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 39376e4e1e..56164e42b5 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -379,6 +379,7 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
}
typedef CPUTriCoreState CPUArchState;
+typedef TriCoreCPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 6d7439b368..90aac6a38e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -152,6 +152,7 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
}
typedef CPUUniCore32State CPUArchState;
+typedef UniCore32CPU ArchCPU;
#include "exec/cpu-all.h"
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 979a5fde7e..56fc21c8bb 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -787,6 +787,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
}
typedef CPUXtensaState CPUArchState;
+typedef XtensaCPU ArchCPU;
#include "exec/cpu-all.h"
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 06/39] cpu: Replace ENV_GET_CPU with env_cpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (4 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 05/39] cpu: Define ArchCPU Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 07/39] cpu: Introduce env_archcpu Richard Henderson
` (32 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/atomic_template.h | 8 +--
accel/tcg/softmmu_template.h | 20 ++++----
include/exec/cpu-all.h | 12 +++++
include/exec/cpu_ldst_template.h | 6 +--
include/exec/cpu_ldst_useronly_template.h | 6 +--
include/exec/softmmu-semi.h | 16 +++---
linux-user/cpu_loop-common.h | 2 +-
target/alpha/cpu.h | 2 -
target/arm/cpu.h | 2 -
target/cris/cpu.h | 2 -
target/hppa/cpu.h | 1 -
target/i386/cpu.h | 2 -
target/lm32/cpu.h | 2 -
target/m68k/cpu.h | 2 -
target/microblaze/cpu.h | 2 -
target/mips/cpu.h | 2 -
target/moxie/cpu.h | 2 -
target/nios2/cpu.h | 2 -
target/openrisc/cpu.h | 2 -
target/ppc/cpu.h | 2 -
target/riscv/cpu.h | 1 -
target/s390x/cpu.h | 2 -
target/sh4/cpu.h | 2 -
target/sparc/cpu.h | 2 -
target/tilegx/cpu.h | 2 -
target/tricore/cpu.h | 2 -
target/unicore32/cpu.h | 2 -
target/xtensa/cpu.h | 2 -
accel/tcg/cputlb.c | 22 ++++-----
accel/tcg/tcg-runtime.c | 4 +-
accel/tcg/translate-all.c | 2 +-
accel/tcg/user-exec.c | 2 +-
bsd-user/syscall.c | 6 +--
linux-user/arm/cpu_loop.c | 2 +-
linux-user/cris/cpu_loop.c | 2 +-
linux-user/elfload.c | 6 +--
linux-user/m68k/cpu_loop.c | 2 +-
linux-user/main.c | 2 +-
linux-user/mips/cpu_loop.c | 2 +-
linux-user/nios2/cpu_loop.c | 2 +-
linux-user/riscv/cpu_loop.c | 2 +-
linux-user/signal.c | 8 +--
linux-user/syscall.c | 18 +++----
linux-user/uname.c | 2 +-
target/arm/helper.c | 42 ++++++++--------
target/hppa/op_helper.c | 2 +-
target/i386/hax-all.c | 6 +--
target/i386/hvf/x86_decode.c | 22 ++++-----
target/i386/hvf/x86_emu.c | 60 +++++++++++++----------
target/i386/mem_helper.c | 4 +-
target/m68k/op_helper.c | 2 +-
target/nios2/mmu.c | 4 +-
target/nios2/op_helper.c | 2 +-
target/ppc/mmu_helper.c | 2 +-
target/s390x/gdbstub.c | 24 ++++-----
target/s390x/mem_helper.c | 2 +-
target/sh4/op_helper.c | 2 +-
docs/devel/tracing.txt | 4 +-
scripts/tracetool/format/tcg_helper_c.py | 2 +-
59 files changed, 176 insertions(+), 198 deletions(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 685602b076..5aaf186253 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -62,21 +62,21 @@
#define ATOMIC_TRACE_RMW do { \
uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false); \
\
- trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \
- trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, \
+ trace_guest_mem_before_exec(env_cpu(env), addr, info); \
+ trace_guest_mem_before_exec(env_cpu(env), addr, \
info | TRACE_MEM_ST); \
} while (0)
#define ATOMIC_TRACE_LD do { \
uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false); \
\
- trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \
+ trace_guest_mem_before_exec(env_cpu(env), addr, info); \
} while (0)
# define ATOMIC_TRACE_ST do { \
uint8_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true); \
\
- trace_guest_mem_before_exec(ENV_GET_CPU(env), addr, info); \
+ trace_guest_mem_before_exec(env_cpu(env), addr, info); \
} while (0)
/* Define host-endian atomic operations. Note that END is used within
diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h
index fc6371aed1..efd4d4e743 100644
--- a/accel/tcg/softmmu_template.h
+++ b/accel/tcg/softmmu_template.h
@@ -120,14 +120,14 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
DATA_TYPE res;
if (addr & ((1 << a_bits) - 1)) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
+ cpu_unaligned_access(env_cpu(env), addr, READ_ACCESS_TYPE,
mmu_idx, retaddr);
}
/* If the TLB entry is for a different page, reload and try again. */
if (!tlb_hit(tlb_addr, addr)) {
if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
+ tlb_fill(env_cpu(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
mmu_idx, retaddr);
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
@@ -191,14 +191,14 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
DATA_TYPE res;
if (addr & ((1 << a_bits) - 1)) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
+ cpu_unaligned_access(env_cpu(env), addr, READ_ACCESS_TYPE,
mmu_idx, retaddr);
}
/* If the TLB entry is for a different page, reload and try again. */
if (!tlb_hit(tlb_addr, addr)) {
if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
+ tlb_fill(env_cpu(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
mmu_idx, retaddr);
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
@@ -289,14 +289,14 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
uintptr_t haddr;
if (addr & ((1 << a_bits) - 1)) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
}
/* If the TLB entry is for a different page, reload and try again. */
if (!tlb_hit(tlb_addr, addr)) {
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), addr, DATA_SIZE, MMU_DATA_STORE,
mmu_idx, retaddr);
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
@@ -333,7 +333,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
entry2 = tlb_entry(env, mmu_idx, page2);
if (!tlb_hit_page(tlb_addr_write(entry2), page2)
&& !VICTIM_TLB_HIT(addr_write, page2)) {
- tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), page2, DATA_SIZE, MMU_DATA_STORE,
mmu_idx, retaddr);
}
@@ -369,14 +369,14 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
uintptr_t haddr;
if (addr & ((1 << a_bits) - 1)) {
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
}
/* If the TLB entry is for a different page, reload and try again. */
if (!tlb_hit(tlb_addr, addr)) {
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), addr, DATA_SIZE, MMU_DATA_STORE,
mmu_idx, retaddr);
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
@@ -413,7 +413,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
entry2 = tlb_entry(env, mmu_idx, page2);
if (!tlb_hit_page(tlb_addr_write(entry2), page2)
&& !VICTIM_TLB_HIT(addr_write, page2)) {
- tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), page2, DATA_SIZE, MMU_DATA_STORE,
mmu_idx, retaddr);
}
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index da07ce311f..454f6d663f 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -371,4 +371,16 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
int cpu_exec(CPUState *cpu);
+/**
+ * env_cpu(env)
+ * @env: The architecture environment
+ *
+ * Return the CPUState associated with the environment.
+ */
+static inline CPUState *env_cpu(CPUArchState *env)
+{
+ ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
+ return &arch_cpu->parent_obj;
+}
+
#endif /* CPU_ALL_H */
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index 0f061d47ef..af7e0b49f2 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -89,7 +89,7 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
#if !defined(SOFTMMU_CODE_ACCESS)
trace_guest_mem_before_exec(
- ENV_GET_CPU(env), ptr,
+ env_cpu(env), ptr,
trace_mem_build_info(SHIFT, false, MO_TE, false));
#endif
@@ -128,7 +128,7 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
#if !defined(SOFTMMU_CODE_ACCESS)
trace_guest_mem_before_exec(
- ENV_GET_CPU(env), ptr,
+ env_cpu(env), ptr,
trace_mem_build_info(SHIFT, true, MO_TE, false));
#endif
@@ -170,7 +170,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
#if !defined(SOFTMMU_CODE_ACCESS)
trace_guest_mem_before_exec(
- ENV_GET_CPU(env), ptr,
+ env_cpu(env), ptr,
trace_mem_build_info(SHIFT, false, MO_TE, true));
#endif
diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h
index 0fd6019af0..bc45e2b8d4 100644
--- a/include/exec/cpu_ldst_useronly_template.h
+++ b/include/exec/cpu_ldst_useronly_template.h
@@ -66,7 +66,7 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
{
#if !defined(CODE_ACCESS)
trace_guest_mem_before_exec(
- ENV_GET_CPU(env), ptr,
+ env_cpu(env), ptr,
trace_mem_build_info(SHIFT, false, MO_TE, false));
#endif
return glue(glue(ld, USUFFIX), _p)(g2h(ptr));
@@ -90,7 +90,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
{
#if !defined(CODE_ACCESS)
trace_guest_mem_before_exec(
- ENV_GET_CPU(env), ptr,
+ env_cpu(env), ptr,
trace_mem_build_info(SHIFT, true, MO_TE, false));
#endif
return glue(glue(lds, SUFFIX), _p)(g2h(ptr));
@@ -116,7 +116,7 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr,
{
#if !defined(CODE_ACCESS)
trace_guest_mem_before_exec(
- ENV_GET_CPU(env), ptr,
+ env_cpu(env), ptr,
trace_mem_build_info(SHIFT, false, MO_TE, true));
#endif
glue(glue(st, SUFFIX), _p)(g2h(ptr), v);
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 7eefad8f39..970837992e 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -14,7 +14,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env, target_ulong addr)
{
uint64_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 0);
+ cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 0);
return tswap64(val);
}
@@ -22,7 +22,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env, target_ulong addr)
{
uint32_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 0);
+ cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 0);
return tswap32(val);
}
@@ -30,7 +30,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env, target_ulong addr)
{
uint8_t val;
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0);
+ cpu_memory_rw_debug(env_cpu(env), addr, &val, 1, 0);
return val;
}
@@ -43,14 +43,14 @@ static inline void softmmu_tput64(CPUArchState *env,
target_ulong addr, uint64_t val)
{
val = tswap64(val);
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 8, 1);
+ cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 8, 1);
}
static inline void softmmu_tput32(CPUArchState *env,
target_ulong addr, uint32_t val)
{
val = tswap32(val);
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, (uint8_t *)&val, 4, 1);
+ cpu_memory_rw_debug(env_cpu(env), addr, (uint8_t *)&val, 4, 1);
}
#define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; })
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
@@ -63,7 +63,7 @@ static void *softmmu_lock_user(CPUArchState *env,
/* TODO: Make this something that isn't fixed size. */
p = malloc(len);
if (p && copy) {
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0);
+ cpu_memory_rw_debug(env_cpu(env), addr, p, len, 0);
}
return p;
}
@@ -79,7 +79,7 @@ static char *softmmu_lock_user_string(CPUArchState *env, target_ulong addr)
return NULL;
}
do {
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0);
+ cpu_memory_rw_debug(env_cpu(env), addr, &c, 1, 0);
addr++;
*(p++) = c;
} while (c);
@@ -90,7 +90,7 @@ static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
target_ulong len)
{
if (len) {
- cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1);
+ cpu_memory_rw_debug(env_cpu(env), addr, p, len, 1);
}
free(p);
}
diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h
index c1d554a249..8828af28a4 100644
--- a/linux-user/cpu_loop-common.h
+++ b/linux-user/cpu_loop-common.h
@@ -24,7 +24,7 @@
#define EXCP_DUMP(env, fmt, ...) \
do { \
- CPUState *cs = ENV_GET_CPU(env); \
+ CPUState *cs = env_cpu(env); \
fprintf(stderr, fmt , ## __VA_ARGS__); \
cpu_dump_state(cs, stderr, 0); \
if (qemu_log_separate()) { \
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index ce470b9089..2c7f75f584 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -278,8 +278,6 @@ static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
return container_of(env, AlphaCPU, env);
}
-#define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d943bb0fed..a633a233cc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -920,8 +920,6 @@ void arm_cpu_post_init(Object *obj);
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
-#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(ARMCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 9f1fbd2f81..883799b463 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -188,8 +188,6 @@ static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
return container_of(env, CRISCPU, env);
}
-#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 9038fa3c13..887e10398a 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -227,7 +227,6 @@ static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
return container_of(env, HPPACPU, env);
}
-#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e))
#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6bd01ebb83..2546ffa4d4 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1484,8 +1484,6 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
return container_of(env, X86CPU, env);
}
-#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(X86CPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 9132397066..c6b252f90a 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -200,8 +200,6 @@ static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
return container_of(env, LM32CPU, env);
}
-#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(LM32CPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index ce0f93343b..43ef30b7cb 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -168,8 +168,6 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
return container_of(env, M68kCPU, env);
}
-#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 161d18546d..c5af1c6076 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -315,8 +315,6 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
return container_of(env, MicroBlazeCPU, env);
}
-#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3fdd075f8e..31e15834ca 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1056,8 +1056,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
return container_of(env, MIPSCPU, env);
}
-#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list(void);
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 8691185162..5b9aae95d2 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -95,8 +95,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
return container_of(env, MoxieCPU, env);
}
-#define ENV_GET_CPU(e) CPU(moxie_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(MoxieCPU, env)
void moxie_cpu_do_interrupt(CPUState *cs);
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index fce08e3575..b14095b8dc 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -198,8 +198,6 @@ static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
return NIOS2_CPU(container_of(env, Nios2CPU, env));
}
-#define ENV_GET_CPU(e) CPU(nios2_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index a6abcc7d2c..0ba4ae3356 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -322,8 +322,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
return container_of(env, OpenRISCCPU, env);
}
-#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(OpenRISCCPU, env)
void cpu_openrisc_list(void);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a2134fe83a..3449b0b085 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1208,8 +1208,6 @@ static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
return container_of(env, PowerPCCPU, env);
}
-#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4cf4516cc3..cd4f2de798 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -234,7 +234,6 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
-#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e))
#define ENV_OFFSET offsetof(RISCVCPU, env)
void riscv_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 6d1b0f273a..9cdd831a77 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -168,8 +168,6 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
return container_of(env, S390CPU, env);
}
-#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 8b175c58b4..c1a9e4f981 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -212,8 +212,6 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
return container_of(env, SuperHCPU, env);
}
-#define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5a108b5532..5a10680d8f 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -537,8 +537,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
return container_of(env, SPARCCPU, env);
}
-#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 042a7a0c71..135df63523 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -143,8 +143,6 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
return container_of(env, TileGXCPU, env);
}
-#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 56164e42b5..4c997b6d30 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -213,8 +213,6 @@ static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env)
return TRICORE_CPU(container_of(env, TriCoreCPU, env));
}
-#define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(TriCoreCPU, env)
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 90aac6a38e..22e22345dc 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -81,8 +81,6 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
return container_of(env, UniCore32CPU, env);
}
-#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 56fc21c8bb..a20541b5d6 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -534,8 +534,6 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
return container_of(env, XtensaCPU, env);
}
-#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
-
#define ENV_OFFSET offsetof(XtensaCPU, env)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2225640fc1..1fed0eebdb 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -415,7 +415,7 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx,
CPUTLBDesc *d = &env_tlb(env)->d[mmu_idx];
int k;
- assert_cpu_is_self(ENV_GET_CPU(env));
+ assert_cpu_is_self(env_cpu(env));
for (k = 0; k < CPU_VTLB_SIZE; k++) {
if (tlb_flush_entry_locked(&d->vtable[k], page)) {
tlb_n_used_entries_dec(env, mmu_idx);
@@ -865,7 +865,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
target_ulong addr, uintptr_t retaddr,
bool recheck, MMUAccessType access_type, int size)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
hwaddr mr_offset;
MemoryRegionSection *section;
MemoryRegion *mr;
@@ -934,7 +934,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
uint64_t val, target_ulong addr,
uintptr_t retaddr, bool recheck, int size)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
hwaddr mr_offset;
MemoryRegionSection *section;
MemoryRegion *mr;
@@ -1000,7 +1000,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
{
size_t vidx;
- assert_cpu_is_self(ENV_GET_CPU(env));
+ assert_cpu_is_self(env_cpu(env));
for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) {
CPUTLBEntry *vtlb = &env_tlb(env)->d[mmu_idx].vtable[vidx];
target_ulong cmp;
@@ -1050,7 +1050,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
if (unlikely(!tlb_hit(entry->addr_code, addr))) {
if (!VICTIM_TLB_HIT(addr_code, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
+ tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
index = tlb_index(env, mmu_idx, addr);
entry = tlb_entry(env, mmu_idx, addr);
}
@@ -1088,7 +1088,7 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
if (!tlb_hit(tlb_addr_write(entry), addr)) {
/* TLB entry is for a different page */
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
mmu_idx, retaddr);
}
}
@@ -1115,7 +1115,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
/* Enforce guest required alignment. */
if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) {
/* ??? Maybe indicate atomic op to cpu_unaligned_access */
- cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
mmu_idx, retaddr);
}
@@ -1131,7 +1131,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
/* Check TLB entry and enforce page permissions. */
if (!tlb_hit(tlb_addr, addr)) {
if (!VICTIM_TLB_HIT(addr_write, addr)) {
- tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_STORE,
mmu_idx, retaddr);
index = tlb_index(env, mmu_idx, addr);
tlbe = tlb_entry(env, mmu_idx, addr);
@@ -1148,7 +1148,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
/* Let the guest notice RMW on a write-only page. */
if (unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) {
- tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD,
+ tlb_fill(env_cpu(env), addr, 1 << s_bits, MMU_DATA_LOAD,
mmu_idx, retaddr);
/* Since we don't support reads and writes to different addresses,
and we do have the proper page loaded for write, this shouldn't
@@ -1161,7 +1161,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
ndi->active = false;
if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
ndi->active = true;
- memory_notdirty_write_prepare(ndi, ENV_GET_CPU(env), addr,
+ memory_notdirty_write_prepare(ndi, env_cpu(env), addr,
qemu_ram_addr_from_host_nofail(hostaddr),
1 << s_bits);
}
@@ -1169,7 +1169,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
return hostaddr;
stop_the_world:
- cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
+ cpu_loop_exit_atomic(env_cpu(env), retaddr);
}
#ifdef TARGET_WORDS_BIGENDIAN
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index d0d4484406..8a1e408e31 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -146,7 +146,7 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg)
void *HELPER(lookup_tb_ptr)(CPUArchState *env)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
@@ -165,5 +165,5 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env)
void HELPER(exit_atomic)(CPUArchState *env)
{
- cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC());
+ cpu_loop_exit_atomic(env_cpu(env), GETPC());
}
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 20b59f93f4..52d94facf0 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1732,7 +1732,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(tcg_ctx);
- tcg_ctx->cpu = ENV_GET_CPU(env);
+ tcg_ctx->cpu = env_cpu(env);
gen_intermediate_code(cpu, tb, max_insns);
tcg_ctx->cpu = NULL;
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 0789984fe6..a6d6b06f30 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -698,7 +698,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
{
/* Enforce qemu required alignment. */
if (unlikely(addr & (size - 1))) {
- cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
+ cpu_loop_exit_atomic(env_cpu(env), retaddr);
}
helper_retaddr = retaddr;
return g2h(addr);
diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
index 66492aaf5d..1ee6195d9f 100644
--- a/bsd-user/syscall.c
+++ b/bsd-user/syscall.c
@@ -315,7 +315,7 @@ abi_long do_freebsd_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg5, abi_long arg6, abi_long arg7,
abi_long arg8)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
abi_long ret;
void *p;
@@ -413,7 +413,7 @@ abi_long do_netbsd_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
abi_long ret;
void *p;
@@ -488,7 +488,7 @@ abi_long do_openbsd_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
abi_long ret;
void *p;
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index ee68aa60bf..b7e7a6323c 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -423,7 +423,7 @@ void cpu_loop(CPUARMState *env)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
struct image_info *info = ts->info;
int i;
diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c
index af8c128bf8..7ec36cb0b5 100644
--- a/linux-user/cris/cpu_loop.c
+++ b/linux-user/cris/cpu_loop.c
@@ -83,7 +83,7 @@ void cpu_loop(CPUCRISState *env)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
struct image_info *info = ts->info;
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index c1a26021f8..a8a89997b1 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -3335,7 +3335,7 @@ static int write_note(struct memelfnote *men, int fd)
static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env)
{
- CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ CPUState *cpu = env_cpu((CPUArchState *)env);
TaskState *ts = (TaskState *)cpu->opaque;
struct elf_thread_status *ets;
@@ -3365,7 +3365,7 @@ static int fill_note_info(struct elf_note_info *info,
long signr, const CPUArchState *env)
{
#define NUMNOTES 3
- CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ CPUState *cpu = env_cpu((CPUArchState *)env);
TaskState *ts = (TaskState *)cpu->opaque;
int i;
@@ -3489,7 +3489,7 @@ static int write_note_info(struct elf_note_info *info, int fd)
*/
static int elf_core_dump(int signr, const CPUArchState *env)
{
- const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ const CPUState *cpu = env_cpu((CPUArchState *)env);
const TaskState *ts = (const TaskState *)cpu->opaque;
struct vm_area_struct *vma = NULL;
char corefile[PATH_MAX];
diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
index bfb41bbcc5..42d8d841ea 100644
--- a/linux-user/m68k/cpu_loop.c
+++ b/linux-user/m68k/cpu_loop.c
@@ -130,7 +130,7 @@ void cpu_loop(CPUM68KState *env)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
struct image_info *info = ts->info;
diff --git a/linux-user/main.c b/linux-user/main.c
index 3d2230320b..e66e9d5d34 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -177,7 +177,7 @@ void init_task_state(TaskState *ts)
CPUArchState *cpu_copy(CPUArchState *env)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
CPUState *new_cpu = cpu_create(cpu_type);
CPUArchState *new_env = new_cpu->env_ptr;
CPUBreakpoint *bp;
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 61dc90d51c..828137cd84 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -654,7 +654,7 @@ error:
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
struct image_info *info = ts->info;
int i;
diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c
index 5aa1eca740..9869083fa1 100644
--- a/linux-user/nios2/cpu_loop.c
+++ b/linux-user/nios2/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUNios2State *env)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
Nios2CPU *cpu = NIOS2_CPU(cs);
target_siginfo_t info;
int trapnr, ret;
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index a9bac4ca79..31700f75d0 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -116,7 +116,7 @@ void cpu_loop(CPURISCVState *env)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
struct image_info *info = ts->info;
diff --git a/linux-user/signal.c b/linux-user/signal.c
index e2c0b37173..1b0ae7fce1 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -621,7 +621,7 @@ static void QEMU_NORETURN dump_core_and_abort(int target_sig)
int queue_signal(CPUArchState *env, int sig, int si_type,
target_siginfo_t *info)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
trace_user_queue_signal(env, sig);
@@ -646,7 +646,7 @@ static void host_signal_handler(int host_signum, siginfo_t *info,
void *puc)
{
CPUArchState *env = thread_cpu->env_ptr;
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
int sig;
@@ -837,7 +837,7 @@ int do_sigaction(int sig, const struct target_sigaction *act,
static void handle_pending_signal(CPUArchState *cpu_env, int sig,
struct emulated_sigtable *k)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
abi_ulong handler;
sigset_t set;
target_sigset_t target_old_set;
@@ -922,7 +922,7 @@ static void handle_pending_signal(CPUArchState *cpu_env, int sig,
void process_pending_signals(CPUArchState *cpu_env)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
int sig;
TaskState *ts = cpu->opaque;
sigset_t set;
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 96cd4bf86d..9f110a7581 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -5432,7 +5432,7 @@ static void *clone_func(void *arg)
rcu_register_thread();
tcg_register_thread();
env = info->env;
- cpu = ENV_GET_CPU(env);
+ cpu = env_cpu(env);
thread_cpu = cpu;
ts = (TaskState *)cpu->opaque;
info->tid = sys_gettid();
@@ -5461,7 +5461,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
abi_ulong parent_tidptr, target_ulong newtls,
abi_ulong child_tidptr)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
int ret;
TaskState *ts;
CPUState *new_cpu;
@@ -5494,7 +5494,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
new_env = cpu_copy(env);
/* Init regs that differ from the parent. */
cpu_clone_regs(new_env, newsp);
- new_cpu = ENV_GET_CPU(new_env);
+ new_cpu = env_cpu(new_env);
new_cpu->opaque = ts;
ts->bprm = parent_ts->bprm;
ts->info = parent_ts->info;
@@ -6590,7 +6590,7 @@ int host_to_target_waitstatus(int status)
static int open_self_cmdline(void *cpu_env, int fd)
{
- CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ CPUState *cpu = env_cpu((CPUArchState *)cpu_env);
struct linux_binprm *bprm = ((TaskState *)cpu->opaque)->bprm;
int i;
@@ -6607,7 +6607,7 @@ static int open_self_cmdline(void *cpu_env, int fd)
static int open_self_maps(void *cpu_env, int fd)
{
- CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ CPUState *cpu = env_cpu((CPUArchState *)cpu_env);
TaskState *ts = cpu->opaque;
FILE *fp;
char *line = NULL;
@@ -6656,7 +6656,7 @@ static int open_self_maps(void *cpu_env, int fd)
static int open_self_stat(void *cpu_env, int fd)
{
- CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ CPUState *cpu = env_cpu((CPUArchState *)cpu_env);
TaskState *ts = cpu->opaque;
abi_ulong start_stack = ts->info->start_stack;
int i;
@@ -6693,7 +6693,7 @@ static int open_self_stat(void *cpu_env, int fd)
static int open_self_auxv(void *cpu_env, int fd)
{
- CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ CPUState *cpu = env_cpu((CPUArchState *)cpu_env);
TaskState *ts = cpu->opaque;
abi_ulong auxv = ts->info->saved_auxv;
abi_ulong len = ts->info->auxv_len;
@@ -6953,7 +6953,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
abi_long arg5, abi_long arg6, abi_long arg7,
abi_long arg8)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
abi_long ret;
#if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \
|| defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \
@@ -11592,7 +11592,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg5, abi_long arg6, abi_long arg7,
abi_long arg8)
{
- CPUState *cpu = ENV_GET_CPU(cpu_env);
+ CPUState *cpu = env_cpu(cpu_env);
abi_long ret;
#ifdef DEBUG_ERESTARTSYS
diff --git a/linux-user/uname.c b/linux-user/uname.c
index 313b79dbad..54bb7e9278 100644
--- a/linux-user/uname.c
+++ b/linux-user/uname.c
@@ -54,7 +54,7 @@ const char *cpu_to_uname_machine(void *cpu_env)
return "armv5te" utsname_suffix;
#elif defined(TARGET_I386) && !defined(TARGET_X86_64)
/* see arch/x86/kernel/cpu/bugs.c: check_bugs(), 386, 486, 586, 686 */
- CPUState *cpu = ENV_GET_CPU((CPUX86State *)cpu_env);
+ CPUState *cpu = env_cpu((CPUX86State *)cpu_env);
int family = object_property_get_int(OBJECT(cpu), "family", NULL);
if (family == 4) {
return "i486";
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 81a92ab491..4c57c0ddd4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -561,7 +561,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_all_cpus_synced(cs);
}
@@ -569,7 +569,7 @@ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_all_cpus_synced(cs);
}
@@ -577,7 +577,7 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
}
@@ -585,7 +585,7 @@ static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
}
@@ -660,7 +660,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx(cs,
ARMMMUIdxBit_S12NSE1 |
@@ -671,7 +671,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs,
ARMMMUIdxBit_S12NSE1 |
@@ -688,7 +688,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
* translation information.
* This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
*/
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr;
if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
@@ -703,7 +703,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr;
if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
@@ -719,7 +719,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
}
@@ -727,7 +727,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
}
@@ -735,7 +735,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
@@ -744,7 +744,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
@@ -1895,7 +1895,7 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
uint64_t ret = 0;
@@ -3747,7 +3747,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
bool sec = arm_is_secure_below_el3(env);
if (sec) {
@@ -3764,7 +3764,7 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
if (tlb_force_broadcast(env)) {
tlbi_aa64_vmalle1is_write(env, NULL, value);
@@ -3835,7 +3835,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
* stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations.
*/
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
bool sec = arm_is_secure_below_el3(env);
bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
@@ -3858,7 +3858,7 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
}
@@ -3866,7 +3866,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
}
@@ -3949,7 +3949,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
@@ -3959,7 +3959,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
@@ -3991,7 +3991,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
uint64_t pageaddr;
if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index a55a5dfc02..952e97a7d7 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -77,7 +77,7 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr, uint32_t val,
}
#else
/* FIXME -- we can do better. */
- cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
+ cpu_loop_exit_atomic(env_cpu(env), ra);
#endif
}
diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c
index 44b89c1d74..64fd51ad4a 100644
--- a/target/i386/hax-all.c
+++ b/target/i386/hax-all.c
@@ -67,7 +67,7 @@ int valid_hax_tunnel_size(uint16_t size)
hax_fd hax_vcpu_get_fd(CPUArchState *env)
{
- struct hax_vcpu_state *vcpu = ENV_GET_CPU(env)->hax_vcpu;
+ struct hax_vcpu_state *vcpu = env_cpu(env)->hax_vcpu;
if (!vcpu) {
return HAX_INVALID_FD;
}
@@ -409,7 +409,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port,
static int hax_vcpu_interrupt(CPUArchState *env)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
struct hax_vcpu_state *vcpu = cpu->hax_vcpu;
struct hax_tunnel *ht = vcpu->tunnel;
@@ -461,7 +461,7 @@ void hax_raise_event(CPUState *cpu)
static int hax_vcpu_hax_exec(CPUArchState *env)
{
int ret = 0;
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUState *cpu = env_cpu(env);
X86CPU *x86_cpu = X86_CPU(cpu);
struct hax_vcpu_state *vcpu = cpu->hax_vcpu;
struct hax_tunnel *ht = vcpu->tunnel;
diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c
index 9ef7d7513f..822fa1866e 100644
--- a/target/i386/hvf/x86_decode.c
+++ b/target/i386/hvf/x86_decode.c
@@ -75,8 +75,8 @@ static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
VM_PANIC_EX("%s invalid size %d\n", __func__, size);
break;
}
- target_ulong va = linear_rip(ENV_GET_CPU(env), RIP(env)) + decode->len;
- vmx_read_mem(ENV_GET_CPU(env), &val, va, size);
+ target_ulong va = linear_rip(env_cpu(env), RIP(env)) + decode->len;
+ vmx_read_mem(env_cpu(env), &val, va, size);
decode->len += size;
return val;
@@ -1772,7 +1772,7 @@ void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode,
if (4 == decode->modrm.rm) {
ptr += get_sib_val(env, decode, &seg);
} else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
- if (x86_is_long_mode(ENV_GET_CPU(env))) {
+ if (x86_is_long_mode(env_cpu(env))) {
ptr += RIP(env) + decode->len;
} else {
ptr = decode->displacement;
@@ -1877,7 +1877,7 @@ static void decode_prefix(CPUX86State *env, struct x86_decode *decode)
decode->addr_size_override = byte;
break;
case PREFIX_REX ... (PREFIX_REX + 0xf):
- if (x86_is_long_mode(ENV_GET_CPU(env))) {
+ if (x86_is_long_mode(env_cpu(env))) {
decode->rex.rex = byte;
break;
}
@@ -1892,16 +1892,16 @@ static void decode_prefix(CPUX86State *env, struct x86_decode *decode)
void set_addressing_size(CPUX86State *env, struct x86_decode *decode)
{
decode->addressing_size = -1;
- if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) {
+ if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) {
if (decode->addr_size_override) {
decode->addressing_size = 4;
} else {
decode->addressing_size = 2;
}
- } else if (!x86_is_long_mode(ENV_GET_CPU(env))) {
+ } else if (!x86_is_long_mode(env_cpu(env))) {
/* protected */
struct vmx_segment cs;
- vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS);
+ vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS);
/* check db */
if ((cs.ar >> 14) & 1) {
if (decode->addr_size_override) {
@@ -1929,16 +1929,16 @@ void set_addressing_size(CPUX86State *env, struct x86_decode *decode)
void set_operand_size(CPUX86State *env, struct x86_decode *decode)
{
decode->operand_size = -1;
- if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) {
+ if (x86_is_real(env_cpu(env)) || x86_is_v8086(env_cpu(env))) {
if (decode->op_size_override) {
decode->operand_size = 4;
} else {
decode->operand_size = 2;
}
- } else if (!x86_is_long_mode(ENV_GET_CPU(env))) {
+ } else if (!x86_is_long_mode(env_cpu(env))) {
/* protected */
struct vmx_segment cs;
- vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, R_CS);
+ vmx_read_segment_descriptor(env_cpu(env), &cs, R_CS);
/* check db */
if ((cs.ar >> 14) & 1) {
if (decode->op_size_override) {
@@ -2188,5 +2188,5 @@ target_ulong decode_linear_addr(CPUX86State *env, struct x86_decode *decode,
default:
break;
}
- return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_size, seg);
+ return linear_addr_size(env_cpu(env), addr, decode->addressing_size, seg);
}
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index 3ea18edc68..1b04bd7e94 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -182,12 +182,12 @@ void write_val_ext(struct CPUX86State *env, target_ulong ptr, target_ulong val,
write_val_to_reg(ptr, val, size);
return;
}
- vmx_write_mem(ENV_GET_CPU(env), ptr, &val, size);
+ vmx_write_mem(env_cpu(env), ptr, &val, size);
}
uint8_t *read_mmio(struct CPUX86State *env, target_ulong ptr, int bytes)
{
- vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, ptr, bytes);
+ vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, ptr, bytes);
return env->hvf_emul->mmio_buf;
}
@@ -399,17 +399,18 @@ static void exec_out(struct CPUX86State *env, struct x86_decode *decode)
{
switch (decode->opcode[0]) {
case 0xe6:
- hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 1, 1, 1);
+ hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 1, 1, 1);
break;
case 0xe7:
- hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &RAX(env), 1,
+ hvf_handle_io(env_cpu(env), decode->op[0].val, &RAX(env), 1,
decode->operand_size, 1);
break;
case 0xee:
- hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 1, 1, 1);
+ hvf_handle_io(env_cpu(env), DX(env), &AL(env), 1, 1, 1);
break;
case 0xef:
- hvf_handle_io(ENV_GET_CPU(env), DX(env), &RAX(env), 1, decode->operand_size, 1);
+ hvf_handle_io(env_cpu(env), DX(env), &RAX(env), 1,
+ decode->operand_size, 1);
break;
default:
VM_PANIC("Bad out opcode\n");
@@ -423,10 +424,11 @@ static void exec_in(struct CPUX86State *env, struct x86_decode *decode)
target_ulong val = 0;
switch (decode->opcode[0]) {
case 0xe4:
- hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 0, 1, 1);
+ hvf_handle_io(env_cpu(env), decode->op[0].val, &AL(env), 0, 1, 1);
break;
case 0xe5:
- hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &val, 0, decode->operand_size, 1);
+ hvf_handle_io(env_cpu(env), decode->op[0].val, &val, 0,
+ decode->operand_size, 1);
if (decode->operand_size == 2) {
AX(env) = val;
} else {
@@ -434,10 +436,10 @@ static void exec_in(struct CPUX86State *env, struct x86_decode *decode)
}
break;
case 0xec:
- hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 0, 1, 1);
+ hvf_handle_io(env_cpu(env), DX(env), &AL(env), 0, 1, 1);
break;
case 0xed:
- hvf_handle_io(ENV_GET_CPU(env), DX(env), &val, 0, decode->operand_size, 1);
+ hvf_handle_io(env_cpu(env), DX(env), &val, 0, decode->operand_size, 1);
if (decode->operand_size == 2) {
AX(env) = val;
} else {
@@ -484,12 +486,13 @@ static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode
static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode)
{
- target_ulong addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
- R_ES);
+ target_ulong addr = linear_addr_size(env_cpu(env), RDI(env),
+ decode->addressing_size, R_ES);
- hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 0,
+ hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 0,
decode->operand_size, 1);
- vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode->operand_size);
+ vmx_write_mem(env_cpu(env), addr, env->hvf_emul->mmio_buf,
+ decode->operand_size);
string_increment_reg(env, R_EDI, decode);
}
@@ -509,8 +512,9 @@ static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr = decode_linear_addr(env, decode, RSI(env), R_DS);
- vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->operand_size);
- hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 1,
+ vmx_read_mem(env_cpu(env), env->hvf_emul->mmio_buf, addr,
+ decode->operand_size);
+ hvf_handle_io(env_cpu(env), DX(env), env->hvf_emul->mmio_buf, 1,
decode->operand_size, 1);
string_increment_reg(env, R_ESI, decode);
@@ -534,8 +538,8 @@ static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode)
target_ulong val;
src_addr = decode_linear_addr(env, decode, RSI(env), R_DS);
- dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
- R_ES);
+ dst_addr = linear_addr_size(env_cpu(env), RDI(env),
+ decode->addressing_size, R_ES);
val = read_val_ext(env, src_addr, decode->operand_size);
write_val_ext(env, dst_addr, val, decode->operand_size);
@@ -561,8 +565,8 @@ static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode)
target_ulong dst_addr;
src_addr = decode_linear_addr(env, decode, RSI(env), R_DS);
- dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
- R_ES);
+ dst_addr = linear_addr_size(env_cpu(env), RDI(env),
+ decode->addressing_size, R_ES);
decode->op[0].type = X86_VAR_IMMEDIATE;
decode->op[0].val = read_val_ext(env, src_addr, decode->operand_size);
@@ -591,9 +595,10 @@ static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode)
target_ulong addr;
target_ulong val;
- addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, R_ES);
+ addr = linear_addr_size(env_cpu(env), RDI(env),
+ decode->addressing_size, R_ES);
val = read_reg(env, R_EAX, decode->operand_size);
- vmx_write_mem(ENV_GET_CPU(env), addr, &val, decode->operand_size);
+ vmx_write_mem(env_cpu(env), addr, &val, decode->operand_size);
string_increment_reg(env, R_EDI, decode);
}
@@ -614,9 +619,10 @@ static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode)
{
target_ulong addr;
- addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, R_ES);
+ addr = linear_addr_size(env_cpu(env), RDI(env),
+ decode->addressing_size, R_ES);
decode->op[1].type = X86_VAR_IMMEDIATE;
- vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->operand_size);
+ vmx_read_mem(env_cpu(env), &decode->op[1].val, addr, decode->operand_size);
EXEC_2OP_FLAGS_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
string_increment_reg(env, R_EDI, decode);
@@ -641,7 +647,7 @@ static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode)
target_ulong val = 0;
addr = decode_linear_addr(env, decode, RSI(env), R_DS);
- vmx_read_mem(ENV_GET_CPU(env), &val, addr, decode->operand_size);
+ vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size);
write_reg(env, R_EAX, val, decode->operand_size);
string_increment_reg(env, R_ESI, decode);
@@ -753,7 +759,7 @@ void simulate_rdmsr(struct CPUState *cpu)
static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode)
{
- simulate_rdmsr(ENV_GET_CPU(env));
+ simulate_rdmsr(env_cpu(env));
RIP(env) += decode->len;
}
@@ -851,7 +857,7 @@ void simulate_wrmsr(struct CPUState *cpu)
static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode)
{
- simulate_wrmsr(ENV_GET_CPU(env));
+ simulate_wrmsr(env_cpu(env));
RIP(env) += decode->len;
}
diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c
index 6cc53bcb40..ae2b2fb4f4 100644
--- a/target/i386/mem_helper.c
+++ b/target/i386/mem_helper.c
@@ -89,7 +89,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
}
CC_SRC = eflags;
#else
- cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC());
+ cpu_loop_exit_atomic(env_cpu(env), GETPC());
#endif /* CONFIG_ATOMIC64 */
}
@@ -158,7 +158,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
}
CC_SRC = eflags;
} else {
- cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
+ cpu_loop_exit_atomic(env_cpu(env), ra);
}
}
#endif
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 76f439985a..13fcaa74ef 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -800,7 +800,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
#endif
{
/* Tell the main loop we need to serialize this insn. */
- cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
+ cpu_loop_exit_atomic(env_cpu(env), ra);
}
} else {
/* We're executing in a serial context -- no need to be atomic. */
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 5acf442d8b..33382bad1b 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -114,7 +114,7 @@ unsigned int mmu_translate(CPUNios2State *env,
static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
Nios2CPU *cpu = nios2_env_get_cpu(env);
int idx;
MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
@@ -138,7 +138,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
Nios2CPU *cpu = nios2_env_get_cpu(env);
MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 529ec6ac0e..a60730faac 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -46,7 +46,7 @@ void helper_check_interrupts(CPUNios2State *env)
void helper_raise_exception(CPUNios2State *env, uint32_t index)
{
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 1dbc9acb75..b32693f24e 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -522,7 +522,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
#if defined(DUMP_PAGE_TABLES)
if (qemu_loglevel_mask(CPU_LOG_MMU)) {
- CPUState *cs = ENV_GET_CPU(env);
+ CPUState *cs = env_cpu(env);
hwaddr curaddr;
uint32_t a0, a1, a2, a3;
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
index df147596ce..1e6d99287b 100644
--- a/target/s390x/gdbstub.c
+++ b/target/s390x/gdbstub.c
@@ -96,7 +96,7 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
switch (n) {
case S390_A0_REGNUM ... S390_A15_REGNUM:
env->aregs[n] = ldl_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 4;
default:
return 0;
@@ -201,9 +201,9 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
case S390_C0_REGNUM ... S390_C15_REGNUM:
env->cregs[n] = ldtul_p(mem_buf);
if (tcg_enabled()) {
- tlb_flush(ENV_GET_CPU(env));
+ tlb_flush(env_cpu(env));
}
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
default:
return 0;
@@ -251,35 +251,35 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
switch (n) {
case S390_VIRT_CKC_REGNUM:
env->ckc = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_CPUTM_REGNUM:
env->cputm = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_BEA_REGNUM:
env->gbea = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_PREFIX_REGNUM:
env->psa = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_PP_REGNUM:
env->pp = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_PFT_REGNUM:
env->pfault_token = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_PFS_REGNUM:
env->pfault_select = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
case S390_VIRT_PFC_REGNUM:
env->pfault_compare = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
default:
return 0;
@@ -303,7 +303,7 @@ static int cpu_read_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
{
env->gscb[n] = ldtul_p(mem_buf);
- cpu_synchronize_post_init(ENV_GET_CPU(env));
+ cpu_synchronize_post_init(env_cpu(env));
return 8;
}
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 3f76a8abfd..e2992deb2f 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1477,7 +1477,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
#endif
if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) ||
(HAVE_ATOMIC128 ? 0 : sc > max)) {
- cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
+ cpu_loop_exit_atomic(env_cpu(env), ra);
}
}
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 4f825bae5a..12fba6fc78 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -119,7 +119,7 @@ void helper_trapa(CPUSH4State *env, uint32_t tra)
void helper_exclusive(CPUSH4State *env)
{
/* We do not want cpu_restore_state to run. */
- cpu_loop_exit_atomic(ENV_GET_CPU(env), 0);
+ cpu_loop_exit_atomic(env_cpu(env), 0);
}
void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
diff --git a/docs/devel/tracing.txt b/docs/devel/tracing.txt
index 056aa56496..76e492a489 100644
--- a/docs/devel/tracing.txt
+++ b/docs/devel/tracing.txt
@@ -434,9 +434,9 @@ Can be used as:
/* trace emitted at this point */
trace_foo(0xd1);
/* trace emitted at this point */
- trace_bar(ENV_GET_CPU(env), 0xd2);
+ trace_bar(env_cpu(env), 0xd2);
/* trace emitted at this point (env) and when guest code is executed (cpu_env) */
- trace_baz_tcg(ENV_GET_CPU(env), cpu_env, 0xd3);
+ trace_baz_tcg(env_cpu(env), cpu_env, 0xd3);
}
If the translating vCPU has address 0xc1 and code is later executed by vCPU
diff --git a/scripts/tracetool/format/tcg_helper_c.py b/scripts/tracetool/format/tcg_helper_c.py
index bbbd6ad0f4..79aa63eada 100644
--- a/scripts/tracetool/format/tcg_helper_c.py
+++ b/scripts/tracetool/format/tcg_helper_c.py
@@ -25,7 +25,7 @@ def vcpu_transform_args(args, mode):
if mode == "code":
return Arguments([
# Does cast from helper requirements to tracing types
- ("CPUState *", "ENV_GET_CPU(%s)" % args.names()[0]),
+ ("CPUState *", "env_cpu(%s)" % args.names()[0]),
])
else:
args = Arguments([
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 07/39] cpu: Introduce env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (5 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 06/39] cpu: Replace ENV_GET_CPU with env_cpu Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 17:52 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 08/39] target/alpha: Use env_cpu, env_archcpu Richard Henderson
` (31 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
This will replace foo_env_get_cpu with a generic definition.
No changes to the target specific code so far.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 454f6d663f..c62f07b354 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
int cpu_exec(CPUState *cpu);
+/**
+ * env_archcpu(env)
+ * @env: The architecture environment
+ *
+ * Return the ArchCPU associated with the environment.
+ */
+static inline ArchCPU *env_archcpu(CPUArchState *env)
+{
+ return container_of(env, ArchCPU, env);
+}
+
/**
* env_cpu(env)
* @env: The architecture environment
@@ -379,8 +390,7 @@ int cpu_exec(CPUState *cpu);
*/
static inline CPUState *env_cpu(CPUArchState *env)
{
- ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
- return &arch_cpu->parent_obj;
+ return &env_archcpu(env)->parent_obj;
}
#endif /* CPU_ALL_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 08/39] target/alpha: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (6 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 07/39] cpu: Introduce env_archcpu Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 17:56 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 09/39] target/arm: " Richard Henderson
` (30 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
With exactly one exception, most uses of alpha_env_get_cpu
were failures to use the more proper, ENV_GET_CPU macro,
now replaced by env_cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.h | 5 -----
linux-user/alpha/cpu_loop.c | 2 +-
target/alpha/helper.c | 8 +++-----
target/alpha/sys_helper.c | 8 ++++----
4 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 2c7f75f584..53c085f691 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -273,11 +273,6 @@ struct AlphaCPU {
QEMUTimer *alarm_timer;
};
-static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
-{
- return container_of(env, AlphaCPU, env);
-}
-
#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c
index 61992571e1..7a94eee84c 100644
--- a/linux-user/alpha/cpu_loop.c
+++ b/linux-user/alpha/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUAlphaState *env)
{
- CPUState *cs = CPU(alpha_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
target_siginfo_t info;
abi_long sysret;
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 7201576aae..08dfb834a5 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -119,7 +119,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
int prot_need, int mmu_idx,
target_ulong *pphys, int *pprot)
{
- CPUState *cs = CPU(alpha_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_long saddr = addr;
target_ulong phys = 0;
target_ulong L1pte, L2pte, L3pte;
@@ -463,8 +463,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
We expect that ENV->PC has already been updated. */
void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
env->error_code = error;
@@ -475,8 +474,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
int excp, int error)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
env->error_code = error;
diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c
index ac22323191..f9c34b1144 100644
--- a/target/alpha/sys_helper.c
+++ b/target/alpha/sys_helper.c
@@ -44,17 +44,17 @@ uint64_t helper_load_pcc(CPUAlphaState *env)
#ifndef CONFIG_USER_ONLY
void helper_tbia(CPUAlphaState *env)
{
- tlb_flush(CPU(alpha_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
}
void helper_tbis(CPUAlphaState *env, uint64_t p)
{
- tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);
+ tlb_flush_page(env_cpu(env), p);
}
void helper_tb_flush(CPUAlphaState *env)
{
- tb_flush(CPU(alpha_env_get_cpu(env)));
+ tb_flush(env_cpu(env));
}
void helper_halt(uint64_t restart)
@@ -78,7 +78,7 @@ uint64_t helper_get_walltime(void)
void helper_set_alarm(CPUAlphaState *env, uint64_t expire)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
+ AlphaCPU *cpu = env_archcpu(env);
if (expire) {
env->alarm_expire = expire;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 09/39] target/arm: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (7 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 08/39] target/alpha: Use env_cpu, env_archcpu Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 17:57 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c Richard Henderson
` (29 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Combined uses of CPU(arm_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 5 --
linux-user/aarch64/cpu_loop.c | 6 +-
linux-user/aarch64/signal.c | 4 +-
linux-user/arm/cpu_loop.c | 2 +-
linux-user/syscall.c | 8 +--
target/arm/arm-semi.c | 4 +-
target/arm/cpu64.c | 2 +-
target/arm/helper-a64.c | 4 +-
target/arm/helper.c | 120 +++++++++++++++++-----------------
target/arm/op_helper.c | 21 +++---
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
target/arm/vfp_helper.c | 2 +-
13 files changed, 88 insertions(+), 94 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a633a233cc..c54c67fde4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -911,11 +911,6 @@ struct ARMCPU {
uint32_t sve_max_vq;
};
-static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
-{
- return container_of(env, ARMCPU, env);
-}
-
void arm_cpu_post_init(Object *obj);
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index d75fd9d3e2..97f355ee23 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -72,7 +72,7 @@
/* AArch64 main loop */
void cpu_loop(CPUARMState *env)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
abi_long ret;
target_siginfo_t info;
@@ -167,8 +167,8 @@ void arm_init_pauth_key(ARMPACKey *key)
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ ARMCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
struct image_info *info = ts->info;
int i;
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index f84a9cf28a..cd521ee42d 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env,
break;
case TARGET_SVE_MAGIC:
- if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) {
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
vq = (env->vfp.zcr_el[1] & 0xf) + 1;
sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
if (!sve && size == sve_size) {
@@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
&layout);
/* SVE state needs saving only if it exists. */
- if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) {
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
vq = (env->vfp.zcr_el[1] & 0xf) + 1;
sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
sve_ofs = alloc_sigframe_space(sve_size, &layout);
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index b7e7a6323c..ece4cf335e 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -206,7 +206,7 @@ do_kernel_trap(CPUARMState *env)
void cpu_loop(CPUARMState *env)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
unsigned int n, insn;
target_siginfo_t info;
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 9f110a7581..eb7fd9a1bf 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9683,10 +9683,10 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
* even though the current architectural maximum is VQ=16.
*/
ret = -TARGET_EINVAL;
- if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env))
+ if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env))
&& arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
CPUARMState *env = cpu_env;
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint32_t vq, old_vq;
old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
@@ -9703,7 +9703,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
case TARGET_PR_SVE_GET_VL:
ret = -TARGET_EINVAL;
{
- ARMCPU *cpu = arm_env_get_cpu(cpu_env);
+ ARMCPU *cpu = env_archcpu(cpu_env);
if (cpu_isar_feature(aa64_sve, cpu)) {
ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
}
@@ -9712,7 +9712,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
case TARGET_PR_PAC_RESET_KEYS:
{
CPUARMState *env = cpu_env;
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (arg3 || arg4 || arg5) {
return -TARGET_EINVAL;
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index 8b5fd7bc6e..e998b014be 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -242,8 +242,8 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb,
target_ulong do_arm_semihosting(CPUARMState *env)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ ARMCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
char * s;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 228906f267..1150cec22d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -44,7 +44,7 @@ static inline void unset_feature(CPUARMState *env, int feature)
#ifndef CONFIG_USER_ONLY
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
/* Number of cores is in [25:24]; otherwise we RAZ */
return (cpu->core_count - 1) << 24;
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 796ef34b55..44e45a8037 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
}
qemu_mutex_lock_iothread();
- arm_call_pre_el_change_hook(arm_env_get_cpu(env));
+ arm_call_pre_el_change_hook(env_archcpu(env));
qemu_mutex_unlock_iothread();
if (!return_to_aa64) {
@@ -1047,7 +1047,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
qemu_mutex_lock_iothread();
- arm_call_el_change_hook(arm_env_get_cpu(env));
+ arm_call_el_change_hook(env_archcpu(env));
qemu_mutex_unlock_iothread();
return;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4c57c0ddd4..082ce89dcf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -224,7 +224,7 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
const ARMCPRegInfo *ri;
uint32_t key;
@@ -522,7 +522,7 @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
raw_write(env, ri, value);
tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
@@ -530,7 +530,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (raw_read(env, ri) != value) {
/* Unlike real hardware the qemu TLB uses virtual addresses,
@@ -544,7 +544,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
&& !extended_addresses_enabled(env)) {
@@ -605,7 +605,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate all (TLBIALL) */
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (tlb_force_broadcast(env)) {
tlbiall_is_write(env, NULL, value);
@@ -619,7 +619,7 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (tlb_force_broadcast(env)) {
tlbimva_is_write(env, NULL, value);
@@ -633,7 +633,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (TLBIASID) */
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (tlb_force_broadcast(env)) {
tlbiasid_is_write(env, NULL, value);
@@ -647,7 +647,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (tlb_force_broadcast(env)) {
tlbimvaa_is_write(env, NULL, value);
@@ -1327,7 +1327,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
static void pmu_update_irq(CPUARMState *env)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
(env->cp15.c9_pminten & env->cp15.c9_pmovsr));
}
@@ -1382,7 +1382,7 @@ static void pmccntr_op_finish(CPUARMState *env)
if (overflow_in > 0) {
int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
overflow_in;
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
}
#endif
@@ -1431,7 +1431,7 @@ static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
if (overflow_in > 0) {
int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
overflow_in;
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
}
#endif
@@ -1839,7 +1839,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
/* Begin with base v8.0 state. */
uint32_t valid_mask = 0x3fff;
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (arm_el_is_aa64(env, 3)) {
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
@@ -1876,7 +1876,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
/* Acquire the CSSELR index from the bank corresponding to the CCSIDR
* bank
@@ -2426,7 +2426,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
timer_del(cpu->gt_timer[timeridx]);
}
@@ -2447,7 +2447,7 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
trace_arm_gt_cval_write(timeridx, value);
env->cp15.c14_timer[timeridx].cval = value;
- gt_recalc_timer(arm_env_get_cpu(env), timeridx);
+ gt_recalc_timer(env_archcpu(env), timeridx);
}
static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -2468,14 +2468,14 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
trace_arm_gt_tval_write(timeridx, value);
env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
sextract64(value, 0, 32);
- gt_recalc_timer(arm_env_get_cpu(env), timeridx);
+ gt_recalc_timer(env_archcpu(env), timeridx);
}
static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
int timeridx,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
trace_arm_gt_ctl_write(timeridx, value);
@@ -2553,7 +2553,7 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
trace_arm_gt_cntvoff_write(value);
raw_write(env, ri, value);
@@ -3186,7 +3186,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
if (!u32p) {
@@ -3201,7 +3201,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint32_t nrgs = cpu->pmsav7_dregion;
if (value >= nrgs) {
@@ -3329,7 +3329,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
TCR *tcr = raw_ptr(env, ri);
if (arm_feature(env, ARM_FEATURE_LPAE)) {
@@ -3358,7 +3358,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
TCR *tcr = raw_ptr(env, ri);
/* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
@@ -3372,7 +3372,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* If the ASID changes (with a 64-bit write), we must flush the TLB. */
if (cpreg_field_is_64bit(ri) &&
extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
tlb_flush(CPU(cpu));
}
raw_write(env, ri, value);
@@ -3381,7 +3381,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
/* Accesses to VTTBR may change the VMID so we must flush the TLB. */
@@ -3471,7 +3471,7 @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Wait-for-interrupt (deprecated) */
- cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
}
static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3624,7 +3624,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
@@ -3636,7 +3636,7 @@ static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static uint64_t mpidr_read_val(CPUARMState *env)
{
- ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
+ ARMCPU *cpu = env_archcpu(env);
uint64_t mpidr = cpu->mp_affinity;
if (arm_feature(env, ARM_FEATURE_V7MP)) {
@@ -3789,7 +3789,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
* stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
if (arm_is_secure_below_el3(env)) {
@@ -3813,7 +3813,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
@@ -3822,7 +3822,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
@@ -3878,7 +3878,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
@@ -3892,7 +3892,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
* Currently handles both VAE3 and VALE3, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
@@ -3902,7 +3902,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
bool sec = arm_is_secure_below_el3(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
@@ -3926,7 +3926,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
* since we don't support flush-for-specific-ASID-only or
* flush-last-level-only.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
@@ -3975,7 +3975,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
* translation information.
* This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
uint64_t pageaddr;
@@ -4018,7 +4018,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int dzp_bit = 1 << 4;
/* DZP indicates whether DC ZVA access is allowed */
@@ -4053,7 +4053,7 @@ static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (raw_read(env, ri) == value) {
/* Skip the TLB flush if nothing actually changed; Linux likes
@@ -4545,7 +4545,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint64_t valid_mask = HCR_MASK;
if (arm_feature(env, ARM_FEATURE_EL3)) {
@@ -5212,7 +5212,7 @@ int sve_exception_el(CPUARMState *env, int el)
*/
uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint32_t zcr_len = cpu->sve_max_vq - 1;
if (el <= 1) {
@@ -5380,7 +5380,7 @@ void hw_watchpoint_update_all(ARMCPU *cpu)
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int i = ri->crm;
/* Bits [63:49] are hardwired to the value of bit [48]; that is, the
@@ -5396,7 +5396,7 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int i = ri->crm;
raw_write(env, ri, value);
@@ -5498,7 +5498,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu)
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int i = ri->crm;
raw_write(env, ri, value);
@@ -5508,7 +5508,7 @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int i = ri->crm;
/* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
@@ -5604,7 +5604,7 @@ static void define_debug_regs(ARMCPU *cpu)
*/
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint64_t pfr1 = cpu->id_pfr1;
if (env->gicv3state) {
@@ -5615,7 +5615,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint64_t pfr0 = cpu->isar.id_aa64pfr0;
if (env->gicv3state) {
@@ -7353,14 +7353,14 @@ uint32_t HELPER(rbit)(uint32_t x)
/* These should probably raise undefined insn exceptions. */
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
}
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
return 0;
@@ -7420,7 +7420,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
static void switch_mode(CPUARMState *env, int mode)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (mode != ARM_CPU_MODE_USR) {
cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
@@ -7763,7 +7763,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
* PreserveFPState() pseudocode.
* We may throw an exception if the stacking fails.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK);
bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK);
@@ -10865,7 +10865,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
target_ulong *page_size,
ARMMMUFaultInfo *fi)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int level = 1;
uint32_t table;
uint32_t desc;
@@ -10986,7 +10986,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
target_ulong *page_size, ARMMMUFaultInfo *fi)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int level = 1;
uint32_t table;
uint32_t desc;
@@ -11371,7 +11371,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
target_ulong *page_size_ptr,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
/* Read an LPAE long-descriptor translation table. */
ARMFaultType fault_type = ARMFault_Translation;
@@ -11729,7 +11729,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
target_ulong *page_size,
ARMMMUFaultInfo *fi)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int n;
bool is_user = regime_is_user(env, mmu_idx);
@@ -11933,7 +11933,7 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
* pseudocode SecurityCheck() function.
* We assume the caller has zero-initialized *sattrs.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int r;
bool idau_exempt = false, idau_ns = true, idau_nsc = true;
int idau_region = IREGION_NOTVALID;
@@ -12046,7 +12046,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
* We set is_subpage to true if the region hit doesn't cover the
* entire TARGET_PAGE the address is within.
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
bool is_user = regime_is_user(env, mmu_idx);
uint32_t secure = regime_is_secure(env, mmu_idx);
int n;
@@ -12860,7 +12860,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
if (val < limit) {
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cpu_restore_state(cs, GETPC(), true);
raise_exception(env, EXCP_STKOF, 0, 1);
@@ -13088,7 +13088,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
* alignment faults or any memory attribute handling).
*/
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint64_t blocklen = 4 << cpu->dcz_blocksize;
uint64_t vaddr = vaddr_in & ~(blocklen - 1);
@@ -13585,7 +13585,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
uint32_t flags = 0;
if (is_a64(env)) {
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint64_t sctlr;
*pc = env->pc;
@@ -13758,7 +13758,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
uint64_t pmask;
assert(vq >= 1 && vq <= ARM_MAX_VQ);
- assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
+ assert(vq <= env_archcpu(env)->sve_max_vq);
/* Zap the high bits of the zregs. */
for (i = 0; i < 32; i++) {
@@ -13784,7 +13784,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int old_len, new_len;
bool old_a64, new_a64;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 8698b4dc83..5af8a1f408 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -31,7 +31,7 @@
static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp,
uint32_t syndrome, uint32_t target_el)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
/*
@@ -245,7 +245,7 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue)
* raising an exception if the limit is breached.
*/
if (newvalue < v7m_sp_limit(env)) {
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/*
* Stack limit exceptions are a rare case, so rather than syncing
@@ -448,7 +448,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int target_el = check_wfx_trap(env, false);
if (cpu_has_work(cs)) {
@@ -483,8 +483,7 @@ void HELPER(wfe)(CPUARMState *env)
void HELPER(yield)(CPUARMState *env)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
/* This is a non-trappable hint instruction that generally indicates
* that the guest is currently busy-looping. Yield control back to the
@@ -502,7 +501,7 @@ void HELPER(yield)(CPUARMState *env)
*/
void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
{
- CPUState *cs = CPU(arm_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
assert(excp_is_internal(excp));
cs->exception_index = excp;
@@ -545,7 +544,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
{
qemu_mutex_lock_iothread();
- arm_call_pre_el_change_hook(arm_env_get_cpu(env));
+ arm_call_pre_el_change_hook(env_archcpu(env));
qemu_mutex_unlock_iothread();
cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
@@ -558,7 +557,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
env->regs[15] &= (env->thumb ? ~1 : ~3);
qemu_mutex_lock_iothread();
- arm_call_el_change_hook(arm_env_get_cpu(env));
+ arm_call_el_change_hook(env_archcpu(env));
qemu_mutex_unlock_iothread();
}
@@ -863,7 +862,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
void HELPER(pre_hvc)(CPUARMState *env)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int cur_el = arm_current_el(env);
/* FIXME: Use actual secure state. */
bool secure = false;
@@ -903,7 +902,7 @@ void HELPER(pre_hvc)(CPUARMState *env)
void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
@@ -1177,7 +1176,7 @@ static bool check_breakpoints(ARMCPU *cpu)
void HELPER(check_breakpoints)(CPUARMState *env)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
if (check_breakpoints(cpu)) {
HELPER(exception_internal(env, EXCP_DEBUG));
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d0fefa798e..f998f1c629 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14318,7 +14318,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cpu->env_ptr;
- ARMCPU *arm_cpu = arm_env_get_cpu(env);
+ ARMCPU *arm_cpu = env_archcpu(env);
uint32_t tb_flags = dc->base.tb->flags;
int bound, core_mmu_idx;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 10bc53f91c..2170f0f3cc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -13380,7 +13380,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
- ARMCPU *cpu = arm_env_get_cpu(env);
+ ARMCPU *cpu = env_archcpu(env);
uint32_t tb_flags = dc->base.tb->flags;
uint32_t condexec, core_mmu_idx;
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 7a46d99148..d3e83b627b 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -101,7 +101,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
- if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
+ if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
val &= ~FPCR_FZ16;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (8 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 09/39] target/arm: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 6:26 ` Philippe Mathieu-Daudé
2019-05-09 18:01 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c Richard Henderson
` (28 subsequent siblings)
38 siblings, 2 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Fix all of the coding style errors in this file at once.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/mmu.c | 479 +++++++++++++++++++++++-----------------------
1 file changed, 237 insertions(+), 242 deletions(-)
diff --git a/target/cris/mmu.c b/target/cris/mmu.c
index b8db908823..9cb73bbfec 100644
--- a/target/cris/mmu.c
+++ b/target/cris/mmu.c
@@ -33,96 +33,99 @@
void cris_mmu_init(CPUCRISState *env)
{
- env->mmu_rand_lfsr = 0xcccc;
+ env->mmu_rand_lfsr = 0xcccc;
}
#define SR_POLYNOM 0x8805
static inline unsigned int compute_polynom(unsigned int sr)
{
- unsigned int i;
- unsigned int f;
+ unsigned int i;
+ unsigned int f;
- f = 0;
- for (i = 0; i < 16; i++)
- f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
+ f = 0;
+ for (i = 0; i < 16; i++) {
+ f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
+ }
- return f;
+ return f;
}
static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
{
- unsigned int f;
+ unsigned int f;
- /* Update lfsr at every fault. */
- f = compute_polynom(env->mmu_rand_lfsr);
- env->mmu_rand_lfsr >>= 1;
- env->mmu_rand_lfsr |= (f << 15);
- env->mmu_rand_lfsr &= 0xffff;
+ /* Update lfsr at every fault. */
+ f = compute_polynom(env->mmu_rand_lfsr);
+ env->mmu_rand_lfsr >>= 1;
+ env->mmu_rand_lfsr |= (f << 15);
+ env->mmu_rand_lfsr &= 0xffff;
}
static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
- return (rw_gc_cfg & 12) != 0;
+ return (rw_gc_cfg & 12) != 0;
}
static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
- return (1 << seg) & rw_mm_cfg;
+ return (1 << seg) & rw_mm_cfg;
}
static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
{
- uint32_t base;
- int i;
+ uint32_t base;
+ int i;
- if (seg < 8)
- base = env->sregs[SFR_RW_MM_KBASE_LO];
- else
- base = env->sregs[SFR_RW_MM_KBASE_HI];
+ if (seg < 8) {
+ base = env->sregs[SFR_RW_MM_KBASE_LO];
+ } else {
+ base = env->sregs[SFR_RW_MM_KBASE_HI];
+ }
- i = seg & 7;
- base >>= i * 4;
- base &= 15;
+ i = seg & 7;
+ base >>= i * 4;
+ base &= 15;
- base <<= 28;
- return base;
+ base <<= 28;
+ return base;
}
-/* Used by the tlb decoder. */
-#define EXTRACT_FIELD(src, start, end) \
- (((src) >> start) & ((1 << (end - start + 1)) - 1))
-static inline void set_field(uint32_t *dst, unsigned int val,
+/* Used by the tlb decoder. */
+#define EXTRACT_FIELD(src, start, end) \
+ (((src) >> start) & ((1 << (end - start + 1)) - 1))
+
+static inline void set_field(uint32_t *dst, unsigned int val,
unsigned int offset, unsigned int width)
{
- uint32_t mask;
+ uint32_t mask;
- mask = (1 << width) - 1;
- mask <<= offset;
- val <<= offset;
+ mask = (1 << width) - 1;
+ mask <<= offset;
+ val <<= offset;
- val &= mask;
- *dst &= ~(mask);
- *dst |= val;
+ val &= mask;
+ *dst &= ~(mask);
+ *dst |= val;
}
#ifdef DEBUG
static void dump_tlb(CPUCRISState *env, int mmu)
{
- int set;
- int idx;
- uint32_t hi, lo, tlb_vpn, tlb_pfn;
+ int set;
+ int idx;
+ uint32_t hi, lo, tlb_vpn, tlb_pfn;
- for (set = 0; set < 4; set++) {
- for (idx = 0; idx < 16; idx++) {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
- tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
- tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
+ for (set = 0; set < 4; set++) {
+ for (idx = 0; idx < 16; idx++) {
+ lo = env->tlbsets[mmu][set][idx].lo;
+ hi = env->tlbsets[mmu][set][idx].hi;
+ tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
+ tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
- printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
- set, idx, hi, lo, tlb_vpn, tlb_pfn);
- }
- }
+ printf("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
+ set, idx, hi, lo, tlb_vpn, tlb_pfn);
+ }
+ }
}
#endif
@@ -131,232 +134,224 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
CPUCRISState *env, uint32_t vaddr,
int rw, int usermode, int debug)
{
- unsigned int vpage;
- unsigned int idx;
- uint32_t pid, lo, hi;
- uint32_t tlb_vpn, tlb_pfn = 0;
- int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
- int cfg_v, cfg_k, cfg_w, cfg_x;
- int set, match = 0;
- uint32_t r_cause;
- uint32_t r_cfg;
- int rwcause;
- int mmu = 1; /* Data mmu is default. */
- int vect_base;
+ unsigned int vpage;
+ unsigned int idx;
+ uint32_t pid, lo, hi;
+ uint32_t tlb_vpn, tlb_pfn = 0;
+ int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
+ int cfg_v, cfg_k, cfg_w, cfg_x;
+ int set, match = 0;
+ uint32_t r_cause;
+ uint32_t r_cfg;
+ int rwcause;
+ int mmu = 1; /* Data mmu is default. */
+ int vect_base;
- r_cause = env->sregs[SFR_R_MM_CAUSE];
- r_cfg = env->sregs[SFR_RW_MM_CFG];
- pid = env->pregs[PR_PID] & 0xff;
+ r_cause = env->sregs[SFR_R_MM_CAUSE];
+ r_cfg = env->sregs[SFR_RW_MM_CFG];
+ pid = env->pregs[PR_PID] & 0xff;
- switch (rw) {
- case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
- case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
- default:
- case 0: rwcause = CRIS_MMU_ERR_READ; break;
- }
+ switch (rw) {
+ case 2:
+ rwcause = CRIS_MMU_ERR_EXEC;
+ mmu = 0;
+ break;
+ case 1:
+ rwcause = CRIS_MMU_ERR_WRITE;
+ break;
+ default:
+ case 0:
+ rwcause = CRIS_MMU_ERR_READ;
+ break;
+ }
- /* I exception vectors 4 - 7, D 8 - 11. */
- vect_base = (mmu + 1) * 4;
+ /* I exception vectors 4 - 7, D 8 - 11. */
+ vect_base = (mmu + 1) * 4;
- vpage = vaddr >> 13;
+ vpage = vaddr >> 13;
- /* We know the index which to check on each set.
- Scan both I and D. */
-#if 0
- for (set = 0; set < 4; set++) {
- for (idx = 0; idx < 16; idx++) {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
- tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
- tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
+ /*
+ * We know the index which to check on each set.
+ * Scan both I and D.
+ */
+ idx = vpage & 15;
+ for (set = 0; set < 4; set++) {
+ lo = env->tlbsets[mmu][set][idx].lo;
+ hi = env->tlbsets[mmu][set][idx].hi;
- printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
- set, idx, hi, lo, tlb_vpn, tlb_pfn);
- }
- }
-#endif
+ tlb_vpn = hi >> 13;
+ tlb_pid = EXTRACT_FIELD(hi, 0, 7);
+ tlb_g = EXTRACT_FIELD(lo, 4, 4);
- idx = vpage & 15;
- for (set = 0; set < 4; set++)
- {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
+ D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
+ mmu, set, idx, tlb_vpn, vpage, lo, hi);
+ if ((tlb_g || (tlb_pid == pid)) && tlb_vpn == vpage) {
+ match = 1;
+ break;
+ }
+ }
- tlb_vpn = hi >> 13;
- tlb_pid = EXTRACT_FIELD(hi, 0, 7);
- tlb_g = EXTRACT_FIELD(lo, 4, 4);
+ res->bf_vec = vect_base;
+ if (match) {
+ cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
+ cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
+ cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
+ cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
- D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
- mmu, set, idx, tlb_vpn, vpage, lo, hi);
- if ((tlb_g || (tlb_pid == pid))
- && tlb_vpn == vpage) {
- match = 1;
- break;
- }
- }
+ tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
+ tlb_v = EXTRACT_FIELD(lo, 3, 3);
+ tlb_k = EXTRACT_FIELD(lo, 2, 2);
+ tlb_w = EXTRACT_FIELD(lo, 1, 1);
+ tlb_x = EXTRACT_FIELD(lo, 0, 0);
- res->bf_vec = vect_base;
- if (match) {
- cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
- cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
- cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
- cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
+ /*
+ * set_exception_vector(0x04, i_mmu_refill);
+ * set_exception_vector(0x05, i_mmu_invalid);
+ * set_exception_vector(0x06, i_mmu_access);
+ * set_exception_vector(0x07, i_mmu_execute);
+ * set_exception_vector(0x08, d_mmu_refill);
+ * set_exception_vector(0x09, d_mmu_invalid);
+ * set_exception_vector(0x0a, d_mmu_access);
+ * set_exception_vector(0x0b, d_mmu_write);
+ */
+ if (cfg_k && tlb_k && usermode) {
+ D(printf("tlb: kernel protected %x lo=%x pc=%x\n",
+ vaddr, lo, env->pc));
+ match = 0;
+ res->bf_vec = vect_base + 2;
+ } else if (rw == 1 && cfg_w && !tlb_w) {
+ D(printf("tlb: write protected %x lo=%x pc=%x\n",
+ vaddr, lo, env->pc));
+ match = 0;
+ /* write accesses never go through the I mmu. */
+ res->bf_vec = vect_base + 3;
+ } else if (rw == 2 && cfg_x && !tlb_x) {
+ D(printf("tlb: exec protected %x lo=%x pc=%x\n",
+ vaddr, lo, env->pc));
+ match = 0;
+ res->bf_vec = vect_base + 3;
+ } else if (cfg_v && !tlb_v) {
+ D(printf("tlb: invalid %x\n", vaddr));
+ match = 0;
+ res->bf_vec = vect_base + 1;
+ }
- tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
- tlb_v = EXTRACT_FIELD(lo, 3, 3);
- tlb_k = EXTRACT_FIELD(lo, 2, 2);
- tlb_w = EXTRACT_FIELD(lo, 1, 1);
- tlb_x = EXTRACT_FIELD(lo, 0, 0);
+ res->prot = 0;
+ if (match) {
+ res->prot |= PAGE_READ;
+ if (tlb_w) {
+ res->prot |= PAGE_WRITE;
+ }
+ if (mmu == 0 && (cfg_x || tlb_x)) {
+ res->prot |= PAGE_EXEC;
+ }
+ } else {
+ D(dump_tlb(env, mmu));
+ }
+ } else {
+ /* If refill, provide a randomized set. */
+ set = env->mmu_rand_lfsr & 3;
+ }
- /*
- set_exception_vector(0x04, i_mmu_refill);
- set_exception_vector(0x05, i_mmu_invalid);
- set_exception_vector(0x06, i_mmu_access);
- set_exception_vector(0x07, i_mmu_execute);
- set_exception_vector(0x08, d_mmu_refill);
- set_exception_vector(0x09, d_mmu_invalid);
- set_exception_vector(0x0a, d_mmu_access);
- set_exception_vector(0x0b, d_mmu_write);
- */
- if (cfg_k && tlb_k && usermode) {
- D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
- vaddr, lo, env->pc));
- match = 0;
- res->bf_vec = vect_base + 2;
- } else if (rw == 1 && cfg_w && !tlb_w) {
- D(printf ("tlb: write protected %x lo=%x pc=%x\n",
- vaddr, lo, env->pc));
- match = 0;
- /* write accesses never go through the I mmu. */
- res->bf_vec = vect_base + 3;
- } else if (rw == 2 && cfg_x && !tlb_x) {
- D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
- vaddr, lo, env->pc));
- match = 0;
- res->bf_vec = vect_base + 3;
- } else if (cfg_v && !tlb_v) {
- D(printf ("tlb: invalid %x\n", vaddr));
- match = 0;
- res->bf_vec = vect_base + 1;
- }
+ if (!match && !debug) {
+ cris_mmu_update_rand_lfsr(env);
- res->prot = 0;
- if (match) {
- res->prot |= PAGE_READ;
- if (tlb_w)
- res->prot |= PAGE_WRITE;
- if (mmu == 0 && (cfg_x || tlb_x))
- res->prot |= PAGE_EXEC;
- }
- else
- D(dump_tlb(env, mmu));
- } else {
- /* If refill, provide a randomized set. */
- set = env->mmu_rand_lfsr & 3;
- }
+ /* Compute index. */
+ idx = vpage & 15;
- if (!match && !debug) {
- cris_mmu_update_rand_lfsr(env);
+ /* Update RW_MM_TLB_SEL. */
+ env->sregs[SFR_RW_MM_TLB_SEL] = 0;
+ set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
+ set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
- /* Compute index. */
- idx = vpage & 15;
+ /* Update RW_MM_CAUSE. */
+ set_field(&r_cause, rwcause, 8, 2);
+ set_field(&r_cause, vpage, 13, 19);
+ set_field(&r_cause, pid, 0, 8);
+ env->sregs[SFR_R_MM_CAUSE] = r_cause;
+ D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
+ }
- /* Update RW_MM_TLB_SEL. */
- env->sregs[SFR_RW_MM_TLB_SEL] = 0;
- set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
- set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
+ D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
+ " %x cause=%x sel=%x sp=%x %x %x\n",
+ __func__, rw, match, env->pc,
+ vaddr, vpage,
+ tlb_vpn, tlb_pfn, tlb_pid,
+ pid,
+ r_cause,
+ env->sregs[SFR_RW_MM_TLB_SEL],
+ env->regs[R_SP], env->pregs[PR_USP], env->ksp));
- /* Update RW_MM_CAUSE. */
- set_field(&r_cause, rwcause, 8, 2);
- set_field(&r_cause, vpage, 13, 19);
- set_field(&r_cause, pid, 0, 8);
- env->sregs[SFR_R_MM_CAUSE] = r_cause;
- D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
- }
-
- D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
- " %x cause=%x sel=%x sp=%x %x %x\n",
- __func__, rw, match, env->pc,
- vaddr, vpage,
- tlb_vpn, tlb_pfn, tlb_pid,
- pid,
- r_cause,
- env->sregs[SFR_RW_MM_TLB_SEL],
- env->regs[R_SP], env->pregs[PR_USP], env->ksp));
-
- res->phy = tlb_pfn << TARGET_PAGE_BITS;
- return !match;
+ res->phy = tlb_pfn << TARGET_PAGE_BITS;
+ return !match;
}
void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
CRISCPU *cpu = cris_env_get_cpu(env);
- target_ulong vaddr;
- unsigned int idx;
- uint32_t lo, hi;
- uint32_t tlb_vpn;
- int tlb_pid, tlb_g, tlb_v;
- unsigned int set;
- unsigned int mmu;
+ target_ulong vaddr;
+ unsigned int idx;
+ uint32_t lo, hi;
+ uint32_t tlb_vpn;
+ int tlb_pid, tlb_g, tlb_v;
+ unsigned int set;
+ unsigned int mmu;
- pid &= 0xff;
- for (mmu = 0; mmu < 2; mmu++) {
- for (set = 0; set < 4; set++)
- {
- for (idx = 0; idx < 16; idx++) {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
-
- tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
- tlb_pid = EXTRACT_FIELD(hi, 0, 7);
- tlb_g = EXTRACT_FIELD(lo, 4, 4);
- tlb_v = EXTRACT_FIELD(lo, 3, 3);
+ pid &= 0xff;
+ for (mmu = 0; mmu < 2; mmu++) {
+ for (set = 0; set < 4; set++) {
+ for (idx = 0; idx < 16; idx++) {
+ lo = env->tlbsets[mmu][set][idx].lo;
+ hi = env->tlbsets[mmu][set][idx].hi;
- if (tlb_v && !tlb_g && (tlb_pid == pid)) {
- vaddr = tlb_vpn << TARGET_PAGE_BITS;
- D_LOG("flush pid=%x vaddr=%x\n",
- pid, vaddr);
+ tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
+ tlb_pid = EXTRACT_FIELD(hi, 0, 7);
+ tlb_g = EXTRACT_FIELD(lo, 4, 4);
+ tlb_v = EXTRACT_FIELD(lo, 3, 3);
+
+ if (tlb_v && !tlb_g && (tlb_pid == pid)) {
+ vaddr = tlb_vpn << TARGET_PAGE_BITS;
+ D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
tlb_flush_page(CPU(cpu), vaddr);
- }
- }
- }
- }
+ }
+ }
+ }
+ }
}
int cris_mmu_translate(struct cris_mmu_result *res,
CPUCRISState *env, uint32_t vaddr,
int rw, int mmu_idx, int debug)
{
- int seg;
- int miss = 0;
- int is_user = mmu_idx == MMU_USER_IDX;
- uint32_t old_srs;
+ int seg;
+ int miss = 0;
+ int is_user = mmu_idx == MMU_USER_IDX;
+ uint32_t old_srs;
- old_srs= env->pregs[PR_SRS];
+ old_srs = env->pregs[PR_SRS];
- /* rw == 2 means exec, map the access to the insn mmu. */
- env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
+ /* rw == 2 means exec, map the access to the insn mmu. */
+ env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
- if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
- res->phy = vaddr;
- res->prot = PAGE_BITS;
- goto done;
- }
+ if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
+ res->phy = vaddr;
+ res->prot = PAGE_BITS;
+ goto done;
+ }
- seg = vaddr >> 28;
- if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
- {
- uint32_t base;
+ seg = vaddr >> 28;
+ if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
+ uint32_t base;
- miss = 0;
- base = cris_mmu_translate_seg(env, seg);
- res->phy = base | (0x0fffffff & vaddr);
- res->prot = PAGE_BITS;
- } else {
- miss = cris_mmu_translate_page(res, env, vaddr, rw,
- is_user, debug);
- }
- done:
- env->pregs[PR_SRS] = old_srs;
- return miss;
+ miss = 0;
+ base = cris_mmu_translate_seg(env, seg);
+ res->phy = base | (0x0fffffff & vaddr);
+ res->prot = PAGE_BITS;
+ } else {
+ miss = cris_mmu_translate_page(res, env, vaddr, rw,
+ is_user, debug);
+ }
+ done:
+ env->pregs[PR_SRS] = old_srs;
+ return miss;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (9 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 6:28 ` Philippe Mathieu-Daudé
2019-05-09 18:03 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 12/39] target/cris: Use env_cpu, env_archcpu Richard Henderson
` (27 subsequent siblings)
38 siblings, 2 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Fix all of the coding style errors in this file at once.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/op_helper.c | 817 +++++++++++++++++++---------------------
1 file changed, 398 insertions(+), 419 deletions(-)
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 0ee3a3117b..d4479167a5 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -76,9 +76,10 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index)
void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
- pid &= 0xff;
- if (pid != (env->pregs[PR_PID] & 0xff))
- cris_mmu_flush_pid(env, env->pregs[PR_PID]);
+ pid &= 0xff;
+ if (pid != (env->pregs[PR_PID] & 0xff)) {
+ cris_mmu_flush_pid(env, env->pregs[PR_PID]);
+ }
#endif
}
@@ -94,541 +95,519 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
}
/* Used by the tlb decoder. */
-#define EXTRACT_FIELD(src, start, end) \
- (((src) >> start) & ((1 << (end - start + 1)) - 1))
+#define EXTRACT_FIELD(src, start, end) \
+ (((src) >> start) & ((1 << (end - start + 1)) - 1))
void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
#if !defined(CONFIG_USER_ONLY)
CRISCPU *cpu = cris_env_get_cpu(env);
#endif
- uint32_t srs;
- srs = env->pregs[PR_SRS];
- srs &= 3;
- env->sregs[srs][sreg] = env->regs[reg];
+ uint32_t srs;
+ srs = env->pregs[PR_SRS];
+ srs &= 3;
+ env->sregs[srs][sreg] = env->regs[reg];
#if !defined(CONFIG_USER_ONLY)
- if (srs == 1 || srs == 2) {
- if (sreg == 6) {
- /* Writes to tlb-hi write to mm_cause as a side
- effect. */
- env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
- env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
- }
- else if (sreg == 5) {
- uint32_t set;
- uint32_t idx;
- uint32_t lo, hi;
- uint32_t vaddr;
- int tlb_v;
+ if (srs == 1 || srs == 2) {
+ if (sreg == 6) {
+ /* Writes to tlb-hi write to mm_cause as a side effect. */
+ env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
+ env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
+ } else if (sreg == 5) {
+ uint32_t set;
+ uint32_t idx;
+ uint32_t lo, hi;
+ uint32_t vaddr;
+ int tlb_v;
- idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
- set >>= 4;
- set &= 3;
+ idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
+ set >>= 4;
+ set &= 3;
- idx &= 15;
- /* We've just made a write to tlb_lo. */
- lo = env->sregs[SFR_RW_MM_TLB_LO];
- /* Writes are done via r_mm_cause. */
- hi = env->sregs[SFR_R_MM_CAUSE];
+ idx &= 15;
+ /* We've just made a write to tlb_lo. */
+ lo = env->sregs[SFR_RW_MM_TLB_LO];
+ /* Writes are done via r_mm_cause. */
+ hi = env->sregs[SFR_R_MM_CAUSE];
- vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
- 13, 31);
- vaddr <<= TARGET_PAGE_BITS;
- tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
- 3, 3);
- env->tlbsets[srs - 1][set][idx].lo = lo;
- env->tlbsets[srs - 1][set][idx].hi = hi;
+ vaddr = EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].hi, 13, 31);
+ vaddr <<= TARGET_PAGE_BITS;
+ tlb_v = EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].lo, 3, 3);
+ env->tlbsets[srs - 1][set][idx].lo = lo;
+ env->tlbsets[srs - 1][set][idx].hi = hi;
- D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
- vaddr, tlb_v, env->pc);
- if (tlb_v) {
+ D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
+ vaddr, tlb_v, env->pc);
+ if (tlb_v) {
tlb_flush_page(CPU(cpu), vaddr);
- }
- }
- }
+ }
+ }
+ }
#endif
}
void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
{
- uint32_t srs;
- env->pregs[PR_SRS] &= 3;
- srs = env->pregs[PR_SRS];
-
+ uint32_t srs;
+ env->pregs[PR_SRS] &= 3;
+ srs = env->pregs[PR_SRS];
+
#if !defined(CONFIG_USER_ONLY)
- if (srs == 1 || srs == 2)
- {
- uint32_t set;
- uint32_t idx;
- uint32_t lo, hi;
+ if (srs == 1 || srs == 2) {
+ uint32_t set;
+ uint32_t idx;
+ uint32_t lo, hi;
- idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
- set >>= 4;
- set &= 3;
- idx &= 15;
+ idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
+ set >>= 4;
+ set &= 3;
+ idx &= 15;
- /* Update the mirror regs. */
- hi = env->tlbsets[srs - 1][set][idx].hi;
- lo = env->tlbsets[srs - 1][set][idx].lo;
- env->sregs[SFR_RW_MM_TLB_HI] = hi;
- env->sregs[SFR_RW_MM_TLB_LO] = lo;
- }
+ /* Update the mirror regs. */
+ hi = env->tlbsets[srs - 1][set][idx].hi;
+ lo = env->tlbsets[srs - 1][set][idx].lo;
+ env->sregs[SFR_RW_MM_TLB_HI] = hi;
+ env->sregs[SFR_RW_MM_TLB_LO] = lo;
+ }
#endif
- env->regs[reg] = env->sregs[srs][sreg];
+ env->regs[reg] = env->sregs[srs][sreg];
}
static void cris_ccs_rshift(CPUCRISState *env)
{
- uint32_t ccs;
+ uint32_t ccs;
- /* Apply the ccs shift. */
- ccs = env->pregs[PR_CCS];
- ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
- if (ccs & U_FLAG)
- {
- /* Enter user mode. */
- env->ksp = env->regs[R_SP];
- env->regs[R_SP] = env->pregs[PR_USP];
- }
+ /* Apply the ccs shift. */
+ ccs = env->pregs[PR_CCS];
+ ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
+ if (ccs & U_FLAG) {
+ /* Enter user mode. */
+ env->ksp = env->regs[R_SP];
+ env->regs[R_SP] = env->pregs[PR_USP];
+ }
- env->pregs[PR_CCS] = ccs;
+ env->pregs[PR_CCS] = ccs;
}
void helper_rfe(CPUCRISState *env)
{
- int rflag = env->pregs[PR_CCS] & R_FLAG;
+ int rflag = env->pregs[PR_CCS] & R_FLAG;
- D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
- env->pregs[PR_ERP], env->pregs[PR_PID],
- env->pregs[PR_CCS],
- env->btarget);
+ D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
+ env->pregs[PR_ERP], env->pregs[PR_PID],
+ env->pregs[PR_CCS],
+ env->btarget);
- cris_ccs_rshift(env);
+ cris_ccs_rshift(env);
- /* RFE sets the P_FLAG only if the R_FLAG is not set. */
- if (!rflag)
- env->pregs[PR_CCS] |= P_FLAG;
+ /* RFE sets the P_FLAG only if the R_FLAG is not set. */
+ if (!rflag) {
+ env->pregs[PR_CCS] |= P_FLAG;
+ }
}
void helper_rfn(CPUCRISState *env)
{
- int rflag = env->pregs[PR_CCS] & R_FLAG;
+ int rflag = env->pregs[PR_CCS] & R_FLAG;
- D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
- env->pregs[PR_ERP], env->pregs[PR_PID],
- env->pregs[PR_CCS],
- env->btarget);
+ D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
+ env->pregs[PR_ERP], env->pregs[PR_PID],
+ env->pregs[PR_CCS],
+ env->btarget);
- cris_ccs_rshift(env);
+ cris_ccs_rshift(env);
- /* Set the P_FLAG only if the R_FLAG is not set. */
- if (!rflag)
- env->pregs[PR_CCS] |= P_FLAG;
+ /* Set the P_FLAG only if the R_FLAG is not set. */
+ if (!rflag) {
+ env->pregs[PR_CCS] |= P_FLAG;
+ }
- /* Always set the M flag. */
- env->pregs[PR_CCS] |= M_FLAG_V32;
+ /* Always set the M flag. */
+ env->pregs[PR_CCS] |= M_FLAG_V32;
}
uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
{
- /* FIXME: clean this up. */
+ /* FIXME: clean this up. */
- /* des ref:
- The N flag is set according to the selected bit in the dest reg.
- The Z flag is set if the selected bit and all bits to the right are
- zero.
- The X flag is cleared.
- Other flags are left untouched.
- The destination reg is not affected.*/
- unsigned int fz, sbit, bset, mask, masked_t0;
+ /*
+ * des ref:
+ * The N flag is set according to the selected bit in the dest reg.
+ * The Z flag is set if the selected bit and all bits to the right are
+ * zero.
+ * The X flag is cleared.
+ * Other flags are left untouched.
+ * The destination reg is not affected.
+ */
+ unsigned int fz, sbit, bset, mask, masked_t0;
- sbit = t1 & 31;
- bset = !!(t0 & (1 << sbit));
- mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
- masked_t0 = t0 & mask;
- fz = !(masked_t0 | bset);
+ sbit = t1 & 31;
+ bset = !!(t0 & (1 << sbit));
+ mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
+ masked_t0 = t0 & mask;
+ fz = !(masked_t0 | bset);
- /* Clear the X, N and Z flags. */
- ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
- if (env->pregs[PR_VR] < 32)
- ccs &= ~(V_FLAG | C_FLAG);
- /* Set the N and Z flags accordingly. */
- ccs |= (bset << 3) | (fz << 2);
- return ccs;
+ /* Clear the X, N and Z flags. */
+ ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
+ if (env->pregs[PR_VR] < 32) {
+ ccs &= ~(V_FLAG | C_FLAG);
+ }
+ /* Set the N and Z flags accordingly. */
+ ccs |= (bset << 3) | (fz << 2);
+ return ccs;
}
static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
uint32_t flags, uint32_t ccs)
{
- unsigned int x, z, mask;
+ unsigned int x, z, mask;
- /* Extended arithmetics, leave the z flag alone. */
- x = env->cc_x;
- mask = env->cc_mask | X_FLAG;
- if (x) {
- z = flags & Z_FLAG;
- mask = mask & ~z;
- }
- flags &= mask;
+ /* Extended arithmetics, leave the z flag alone. */
+ x = env->cc_x;
+ mask = env->cc_mask | X_FLAG;
+ if (x) {
+ z = flags & Z_FLAG;
+ mask = mask & ~z;
+ }
+ flags &= mask;
- /* all insn clear the x-flag except setf or clrf. */
- ccs &= ~mask;
- ccs |= flags;
- return ccs;
+ /* all insn clear the x-flag except setf or clrf. */
+ ccs &= ~mask;
+ ccs |= flags;
+ return ccs;
}
uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
uint32_t ccs, uint32_t res, uint32_t mof)
{
- uint32_t flags = 0;
- int64_t tmp;
- int dneg;
+ uint32_t flags = 0;
+ int64_t tmp;
+ int dneg;
- dneg = ((int32_t)res) < 0;
+ dneg = ((int32_t)res) < 0;
- tmp = mof;
- tmp <<= 32;
- tmp |= res;
- if (tmp == 0)
- flags |= Z_FLAG;
- else if (tmp < 0)
- flags |= N_FLAG;
- if ((dneg && mof != -1)
- || (!dneg && mof != 0))
- flags |= V_FLAG;
- return evaluate_flags_writeback(env, flags, ccs);
+ tmp = mof;
+ tmp <<= 32;
+ tmp |= res;
+ if (tmp == 0) {
+ flags |= Z_FLAG;
+ } else if (tmp < 0) {
+ flags |= N_FLAG;
+ }
+ if ((dneg && mof != -1) || (!dneg && mof != 0)) {
+ flags |= V_FLAG;
+ }
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
uint32_t ccs, uint32_t res, uint32_t mof)
{
- uint32_t flags = 0;
- uint64_t tmp;
+ uint32_t flags = 0;
+ uint64_t tmp;
- tmp = mof;
- tmp <<= 32;
- tmp |= res;
- if (tmp == 0)
- flags |= Z_FLAG;
- else if (tmp >> 63)
- flags |= N_FLAG;
- if (mof)
- flags |= V_FLAG;
+ tmp = mof;
+ tmp <<= 32;
+ tmp |= res;
+ if (tmp == 0) {
+ flags |= Z_FLAG;
+ } else if (tmp >> 63) {
+ flags |= N_FLAG;
+ }
+ if (mof) {
+ flags |= V_FLAG;
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- src = src & 0x80000000;
- dst = dst & 0x80000000;
+ src = src & 0x80000000;
+ dst = dst & 0x80000000;
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (!src && !dst)
- flags |= V_FLAG;
- else if (src & dst)
- flags |= R_FLAG;
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (src & dst)
- flags |= V_FLAG;
- if (dst | src)
- flags |= R_FLAG;
- }
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (!src && !dst) {
+ flags |= V_FLAG;
+ } else if (src & dst) {
+ flags |= R_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (src & dst) {
+ flags |= V_FLAG;
+ }
+ if (dst | src) {
+ flags |= R_FLAG;
+ }
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- src = src & 0x80000000;
- dst = dst & 0x80000000;
+ src = src & 0x80000000;
+ dst = dst & 0x80000000;
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (!src && !dst)
- flags |= V_FLAG;
- else if (src & dst)
- flags |= C_FLAG;
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (src & dst)
- flags |= V_FLAG;
- if (dst | src)
- flags |= C_FLAG;
- }
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (!src && !dst) {
+ flags |= V_FLAG;
+ } else if (src & dst) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (src & dst) {
+ flags |= V_FLAG;
+ }
+ if (dst | src) {
+ flags |= C_FLAG;
+ }
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- src = (~src) & 0x80000000;
- dst = dst & 0x80000000;
+ src = (~src) & 0x80000000;
+ dst = dst & 0x80000000;
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (!src && !dst)
- flags |= V_FLAG;
- else if (src & dst)
- flags |= C_FLAG;
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (src & dst)
- flags |= V_FLAG;
- if (dst | src)
- flags |= C_FLAG;
- }
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (!src && !dst) {
+ flags |= V_FLAG;
+ } else if (src & dst) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (src & dst) {
+ flags |= V_FLAG;
+ }
+ if (dst | src) {
+ flags |= C_FLAG;
+ }
+ }
- flags ^= C_FLAG;
- return evaluate_flags_writeback(env, flags, ccs);
+ flags ^= C_FLAG;
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
uint32_t ccs, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- if ((int32_t)res < 0)
- flags |= N_FLAG;
- else if (res == 0L)
- flags |= Z_FLAG;
+ if ((int32_t)res < 0) {
+ flags |= N_FLAG;
+ } else if (res == 0L) {
+ flags |= Z_FLAG;
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
+
uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
uint32_t ccs, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- if ((int16_t)res < 0L)
- flags |= N_FLAG;
- else if (res == 0)
- flags |= Z_FLAG;
+ if ((int16_t)res < 0L) {
+ flags |= N_FLAG;
+ } else if (res == 0) {
+ flags |= Z_FLAG;
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-/* TODO: This is expensive. We could split things up and only evaluate part of
- CCR on a need to know basis. For now, we simply re-evaluate everything. */
+/*
+ * TODO: This is expensive. We could split things up and only evaluate part of
+ * CCR on a need to know basis. For now, we simply re-evaluate everything.
+ */
void helper_evaluate_flags(CPUCRISState *env)
{
- uint32_t src, dst, res;
- uint32_t flags = 0;
+ uint32_t src, dst, res;
+ uint32_t flags = 0;
- src = env->cc_src;
- dst = env->cc_dest;
- res = env->cc_result;
+ src = env->cc_src;
+ dst = env->cc_dest;
+ res = env->cc_result;
- if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
- src = ~src;
+ if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) {
+ src = ~src;
+ }
- /* Now, evaluate the flags. This stuff is based on
- Per Zander's CRISv10 simulator. */
- switch (env->cc_size)
- {
- case 1:
- if ((res & 0x80L) != 0L)
- {
- flags |= N_FLAG;
- if (((src & 0x80L) == 0L)
- && ((dst & 0x80L) == 0L))
- {
- flags |= V_FLAG;
- }
- else if (((src & 0x80L) != 0L)
- && ((dst & 0x80L) != 0L))
- {
- flags |= C_FLAG;
- }
- }
- else
- {
- if ((res & 0xFFL) == 0L)
- {
- flags |= Z_FLAG;
- }
- if (((src & 0x80L) != 0L)
- && ((dst & 0x80L) != 0L))
- {
- flags |= V_FLAG;
- }
- if ((dst & 0x80L) != 0L
- || (src & 0x80L) != 0L)
- {
- flags |= C_FLAG;
- }
- }
- break;
- case 2:
- if ((res & 0x8000L) != 0L)
- {
- flags |= N_FLAG;
- if (((src & 0x8000L) == 0L)
- && ((dst & 0x8000L) == 0L))
- {
- flags |= V_FLAG;
- }
- else if (((src & 0x8000L) != 0L)
- && ((dst & 0x8000L) != 0L))
- {
- flags |= C_FLAG;
- }
- }
- else
- {
- if ((res & 0xFFFFL) == 0L)
- {
- flags |= Z_FLAG;
- }
- if (((src & 0x8000L) != 0L)
- && ((dst & 0x8000L) != 0L))
- {
- flags |= V_FLAG;
- }
- if ((dst & 0x8000L) != 0L
- || (src & 0x8000L) != 0L)
- {
- flags |= C_FLAG;
- }
- }
- break;
- case 4:
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (((src & 0x80000000L) == 0L)
- && ((dst & 0x80000000L) == 0L))
- {
- flags |= V_FLAG;
- }
- else if (((src & 0x80000000L) != 0L) &&
- ((dst & 0x80000000L) != 0L))
- {
- flags |= C_FLAG;
- }
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (((src & 0x80000000L) != 0L)
- && ((dst & 0x80000000L) != 0L))
- flags |= V_FLAG;
- if ((dst & 0x80000000L) != 0L
- || (src & 0x80000000L) != 0L)
- flags |= C_FLAG;
- }
- break;
- default:
- break;
- }
+ /*
+ * Now, evaluate the flags. This stuff is based on
+ * Per Zander's CRISv10 simulator.
+ */
+ switch (env->cc_size) {
+ case 1:
+ if ((res & 0x80L) != 0L) {
+ flags |= N_FLAG;
+ if (((src & 0x80L) == 0L) && ((dst & 0x80L) == 0L)) {
+ flags |= V_FLAG;
+ } else if (((src & 0x80L) != 0L) && ((dst & 0x80L) != 0L)) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if ((res & 0xFFL) == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (((src & 0x80L) != 0L) && ((dst & 0x80L) != 0L)) {
+ flags |= V_FLAG;
+ }
+ if ((dst & 0x80L) != 0L || (src & 0x80L) != 0L) {
+ flags |= C_FLAG;
+ }
+ }
+ break;
+ case 2:
+ if ((res & 0x8000L) != 0L) {
+ flags |= N_FLAG;
+ if (((src & 0x8000L) == 0L) && ((dst & 0x8000L) == 0L)) {
+ flags |= V_FLAG;
+ } else if (((src & 0x8000L) != 0L) && ((dst & 0x8000L) != 0L)) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if ((res & 0xFFFFL) == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (((src & 0x8000L) != 0L) && ((dst & 0x8000L) != 0L)) {
+ flags |= V_FLAG;
+ }
+ if ((dst & 0x8000L) != 0L || (src & 0x8000L) != 0L) {
+ flags |= C_FLAG;
+ }
+ }
+ break;
+ case 4:
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (((src & 0x80000000L) == 0L) && ((dst & 0x80000000L) == 0L)) {
+ flags |= V_FLAG;
+ } else if (((src & 0x80000000L) != 0L) &&
+ ((dst & 0x80000000L) != 0L)) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (((src & 0x80000000L) != 0L) && ((dst & 0x80000000L) != 0L)) {
+ flags |= V_FLAG;
+ }
+ if ((dst & 0x80000000L) != 0L || (src & 0x80000000L) != 0L) {
+ flags |= C_FLAG;
+ }
+ }
+ break;
+ default:
+ break;
+ }
- if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
- flags ^= C_FLAG;
+ if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) {
+ flags ^= C_FLAG;
+ }
- env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
- env->pregs[PR_CCS]);
+ env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
+ env->pregs[PR_CCS]);
}
void helper_top_evaluate_flags(CPUCRISState *env)
{
- switch (env->cc_op)
- {
- case CC_OP_MCP:
- env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
- env->pregs[PR_CCS], env->cc_src,
- env->cc_dest, env->cc_result);
- break;
- case CC_OP_MULS:
- env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
- env->pregs[PR_CCS], env->cc_result,
- env->pregs[PR_MOF]);
- break;
- case CC_OP_MULU:
- env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
- env->pregs[PR_CCS], env->cc_result,
- env->pregs[PR_MOF]);
- break;
- case CC_OP_MOVE:
- case CC_OP_AND:
- case CC_OP_OR:
- case CC_OP_XOR:
- case CC_OP_ASR:
- case CC_OP_LSR:
- case CC_OP_LSL:
- switch (env->cc_size)
- {
- case 4:
- env->pregs[PR_CCS] =
- helper_evaluate_flags_move_4(env,
- env->pregs[PR_CCS],
- env->cc_result);
- break;
- case 2:
- env->pregs[PR_CCS] =
- helper_evaluate_flags_move_2(env,
- env->pregs[PR_CCS],
- env->cc_result);
- break;
- default:
- helper_evaluate_flags(env);
- break;
- }
- break;
- case CC_OP_FLAGS:
- /* live. */
- break;
- case CC_OP_SUB:
- case CC_OP_CMP:
- if (env->cc_size == 4)
- env->pregs[PR_CCS] =
- helper_evaluate_flags_sub_4(env,
- env->pregs[PR_CCS],
- env->cc_src, env->cc_dest,
- env->cc_result);
- else
- helper_evaluate_flags(env);
- break;
- default:
- {
- switch (env->cc_size)
- {
- case 4:
- env->pregs[PR_CCS] =
- helper_evaluate_flags_alu_4(env,
- env->pregs[PR_CCS],
- env->cc_src, env->cc_dest,
- env->cc_result);
- break;
- default:
- helper_evaluate_flags(env);
- break;
- }
- }
- break;
- }
+ switch (env->cc_op) {
+ case CC_OP_MCP:
+ env->pregs[PR_CCS]
+ = helper_evaluate_flags_mcp(env, env->pregs[PR_CCS],
+ env->cc_src, env->cc_dest,
+ env->cc_result);
+ break;
+ case CC_OP_MULS:
+ env->pregs[PR_CCS]
+ = helper_evaluate_flags_muls(env, env->pregs[PR_CCS],
+ env->cc_result, env->pregs[PR_MOF]);
+ break;
+ case CC_OP_MULU:
+ env->pregs[PR_CCS]
+ = helper_evaluate_flags_mulu(env, env->pregs[PR_CCS],
+ env->cc_result, env->pregs[PR_MOF]);
+ break;
+ case CC_OP_MOVE:
+ case CC_OP_AND:
+ case CC_OP_OR:
+ case CC_OP_XOR:
+ case CC_OP_ASR:
+ case CC_OP_LSR:
+ case CC_OP_LSL:
+ switch (env->cc_size) {
+ case 4:
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_move_4(env,
+ env->pregs[PR_CCS],
+ env->cc_result);
+ break;
+ case 2:
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_move_2(env,
+ env->pregs[PR_CCS],
+ env->cc_result);
+ break;
+ default:
+ helper_evaluate_flags(env);
+ break;
+ }
+ break;
+ case CC_OP_FLAGS:
+ /* live. */
+ break;
+ case CC_OP_SUB:
+ case CC_OP_CMP:
+ if (env->cc_size == 4) {
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_sub_4(env,
+ env->pregs[PR_CCS],
+ env->cc_src, env->cc_dest,
+ env->cc_result);
+ } else {
+ helper_evaluate_flags(env);
+ }
+ break;
+ default:
+ switch (env->cc_size) {
+ case 4:
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_alu_4(env,
+ env->pregs[PR_CCS],
+ env->cc_src, env->cc_dest,
+ env->cc_result);
+ break;
+ default:
+ helper_evaluate_flags(env);
+ break;
+ }
+ break;
+ }
}
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 12/39] target/cris: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (10 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:04 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 13/39] target/hppa: " Richard Henderson
` (26 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/cpu.h | 5 -----
linux-user/cris/cpu_loop.c | 2 +-
target/cris/mmu.c | 3 +--
target/cris/op_helper.c | 10 +++-------
target/cris/translate.c | 2 +-
5 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 883799b463..7f244ad545 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -183,11 +183,6 @@ struct CRISCPU {
CPUCRISState env;
};
-static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
-{
- return container_of(env, CRISCPU, env);
-}
-
#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c
index 7ec36cb0b5..86e711108d 100644
--- a/linux-user/cris/cpu_loop.c
+++ b/linux-user/cris/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUCRISState *env)
{
- CPUState *cs = CPU(cris_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;
diff --git a/target/cris/mmu.c b/target/cris/mmu.c
index 9cb73bbfec..2acbcfd1c7 100644
--- a/target/cris/mmu.c
+++ b/target/cris/mmu.c
@@ -288,7 +288,6 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
target_ulong vaddr;
unsigned int idx;
uint32_t lo, hi;
@@ -312,7 +311,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
if (tlb_v && !tlb_g && (tlb_pid == pid)) {
vaddr = tlb_vpn << TARGET_PAGE_BITS;
D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
- tlb_flush_page(CPU(cpu), vaddr);
+ tlb_flush_page(env_cpu(env), vaddr);
}
}
}
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index d4479167a5..0e323c1dd7 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
- CPUState *cs = CPU(cris_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);
@@ -86,8 +86,7 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
- CRISCPU *cpu = cris_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
tlb_flush_page(cs, env->pregs[PR_SPC]);
tlb_flush_page(cs, new_spc);
@@ -100,9 +99,6 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
-#if !defined(CONFIG_USER_ONLY)
- CRISCPU *cpu = cris_env_get_cpu(env);
-#endif
uint32_t srs;
srs = env->pregs[PR_SRS];
srs &= 3;
@@ -140,7 +136,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc);
if (tlb_v) {
- tlb_flush_page(CPU(cpu), vaddr);
+ tlb_flush_page(env_cpu(env), vaddr);
}
}
}
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b005a5c20e..c0af9665fc 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3104,7 +3104,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
- dc->cpu = cris_env_get_cpu(env);
+ dc->cpu = env_archcpu(env);
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 13/39] target/hppa: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (11 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 12/39] target/cris: Use env_cpu, env_archcpu Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:05 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 14/39] target/i386: " Richard Henderson
` (25 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Combined uses of CPU(hppa_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 5 -----
linux-user/hppa/cpu_loop.c | 2 +-
target/hppa/helper.c | 3 +--
target/hppa/int_helper.c | 4 ++--
target/hppa/mem_helper.c | 10 ++++------
target/hppa/op_helper.c | 8 +++-----
6 files changed, 11 insertions(+), 21 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 887e10398a..a5ddc53bf1 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -222,11 +222,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
-static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
-{
- return container_of(env, HPPACPU, env);
-}
-
#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState;
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index 880955fdef..9915456a1d 100644
--- a/linux-user/hppa/cpu_loop.c
+++ b/linux-user/hppa/cpu_loop.c
@@ -105,7 +105,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env)
void cpu_loop(CPUHPPAState *env)
{
- CPUState *cs = CPU(hppa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_siginfo_t info;
abi_ulong ret;
int trapnr;
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 11c61b3ca2..0dcd105b88 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -71,8 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
/* If PSW_P changes, it affects how we translate addresses. */
if ((psw ^ old_psw) & PSW_P) {
#ifndef CONFIG_USER_ONLY
- CPUState *src = CPU(hppa_env_get_cpu(env));
- tlb_flush_by_mmuidx(src, 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), 0xf);
#endif
}
}
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index 8d5edd3a20..89241c31e7 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -77,7 +77,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
{
env->cr[CR_EIRR] &= ~val;
qemu_mutex_lock_iothread();
- eval_interrupt(hppa_env_get_cpu(env));
+ eval_interrupt(env_archcpu(env));
qemu_mutex_unlock_iothread();
}
@@ -85,7 +85,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
{
env->cr[CR_EIEM] = val;
qemu_mutex_lock_iothread();
- eval_interrupt(hppa_env_get_cpu(env));
+ eval_interrupt(env_archcpu(env));
qemu_mutex_unlock_iothread();
}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 77fb544838..e2f464c78c 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -55,7 +55,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
{
- CPUState *cs = CPU(hppa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
unsigned i, n = 1 << (2 * ent->page_size);
uint64_t addr = ent->va_b;
@@ -323,7 +323,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
{
- CPUState *src = CPU(hppa_env_get_cpu(env));
+ CPUState *src = env_cpu(env);
CPUState *cpu;
trace_hppa_tlb_ptlb(env);
run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr);
@@ -340,17 +340,15 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
number of pages/entries (we choose all), and is local to the cpu. */
void HELPER(ptlbe)(CPUHPPAState *env)
{
- CPUState *src = CPU(hppa_env_get_cpu(env));
trace_hppa_tlb_ptlbe(env);
memset(env->tlb, 0, sizeof(env->tlb));
- tlb_flush_by_mmuidx(src, 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), 0xf);
}
void cpu_hppa_change_prot_id(CPUHPPAState *env)
{
if (env->psw & PSW_P) {
- CPUState *src = CPU(hppa_env_get_cpu(env));
- tlb_flush_by_mmuidx(src, 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), 0xf);
}
}
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 952e97a7d7..04d23c1b22 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -29,8 +29,7 @@
void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
{
- HPPACPU *cpu = hppa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
cpu_loop_exit(cs);
@@ -38,8 +37,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
{
- HPPACPU *cpu = hppa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
cpu_loop_exit_restore(cs, ra);
@@ -630,7 +628,7 @@ target_ureg HELPER(read_interval_timer)(void)
#ifndef CONFIG_USER_ONLY
void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
{
- HPPACPU *cpu = hppa_env_get_cpu(env);
+ HPPACPU *cpu = env_archcpu(env);
uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
uint64_t timeout;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 14/39] target/i386: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (12 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 13/39] target/hppa: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:07 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 15/39] target/lm32: " Richard Henderson
` (24 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Combined uses of CPU(x86_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/cpu.h | 5 -----
bsd-user/main.c | 3 +--
hw/i386/kvmvapic.c | 4 ++--
hw/i386/pc.c | 2 +-
linux-user/i386/cpu_loop.c | 2 +-
linux-user/i386/signal.c | 2 +-
linux-user/vm86.c | 18 +++++++++---------
target/i386/bpt_helper.c | 4 ++--
target/i386/cpu.c | 4 ++--
target/i386/excp_helper.c | 2 +-
target/i386/fpu_helper.c | 2 +-
target/i386/helper.c | 16 ++++++----------
target/i386/misc_helper.c | 24 +++++++++++-------------
target/i386/seg_helper.c | 14 +++++++-------
target/i386/smm_helper.c | 4 ++--
target/i386/svm_helper.c | 22 +++++++++++-----------
16 files changed, 58 insertions(+), 70 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2546ffa4d4..e7f94437b1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1479,11 +1479,6 @@ struct X86CPU {
int32_t hv_max_vps;
};
-static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
-{
- return container_of(env, X86CPU, env);
-}
-
#define ENV_OFFSET offsetof(X86CPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 6192e9d91e..bfdcae4269 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -140,8 +140,7 @@ static void set_idt(int n, unsigned int dpl)
void cpu_loop(CPUX86State *env)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(cpu);
int trapnr;
abi_ulong pc;
//target_siginfo_t info;
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 70f6f26a94..fe5b12ef6e 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -152,7 +152,7 @@ static void update_guest_rom_state(VAPICROMState *s)
static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
hwaddr paddr;
target_ulong addr;
@@ -279,7 +279,7 @@ instruction_ok:
static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
hwaddr paddr;
uint32_t rom_state_vaddr;
uint32_t pos, patch, offset;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index d98b737b8f..6a3a0678fc 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -408,7 +408,7 @@ uint64_t cpu_get_tsc(CPUX86State *env)
/* IRQ handling */
int cpu_get_pic_interrupt(CPUX86State *env)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
int intno;
if (!kvm_irqchip_in_kernel()) {
diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
index 51cfa006c9..71da24384f 100644
--- a/linux-user/i386/cpu_loop.c
+++ b/linux-user/i386/cpu_loop.c
@@ -82,7 +82,7 @@ static void set_idt(int n, unsigned int dpl)
void cpu_loop(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
abi_ulong pc;
abi_ulong ret;
diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c
index fecb4c99c3..97a39204cc 100644
--- a/linux-user/i386/signal.c
+++ b/linux-user/i386/signal.c
@@ -198,7 +198,7 @@ static void setup_sigcontext(struct target_sigcontext *sc,
struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask,
abi_ulong fpstate_addr)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
#ifndef TARGET_X86_64
uint16_t magic;
diff --git a/linux-user/vm86.c b/linux-user/vm86.c
index 9c393df424..2fa7a89edc 100644
--- a/linux-user/vm86.c
+++ b/linux-user/vm86.c
@@ -72,7 +72,7 @@ static inline unsigned int vm_getl(CPUX86State *env,
void save_v86_state(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
struct target_vm86plus_struct * target_v86;
@@ -132,7 +132,7 @@ static inline void return_to_32bit(CPUX86State *env, int retval)
static inline int set_IF(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
ts->v86flags |= VIF_MASK;
@@ -145,7 +145,7 @@ static inline int set_IF(CPUX86State *env)
static inline void clear_IF(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
ts->v86flags &= ~VIF_MASK;
@@ -163,7 +163,7 @@ static inline void clear_AC(CPUX86State *env)
static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
set_flags(ts->v86flags, eflags, ts->v86mask);
@@ -177,7 +177,7 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
@@ -191,7 +191,7 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
static inline unsigned int get_vflags(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
unsigned int flags;
@@ -208,7 +208,7 @@ static inline unsigned int get_vflags(CPUX86State *env)
support TSS interrupt revectoring, so this code is always executed) */
static void do_int(CPUX86State *env, int intno)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
uint32_t int_addr, segoffs, ssp;
unsigned int sp;
@@ -267,7 +267,7 @@ void handle_vm86_trap(CPUX86State *env, int trapno)
void handle_vm86_fault(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
uint32_t csp, ssp;
unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
@@ -392,7 +392,7 @@ void handle_vm86_fault(CPUX86State *env)
int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
struct target_vm86plus_struct * target_v86;
int ret;
diff --git a/target/i386/bpt_helper.c b/target/i386/bpt_helper.c
index b3efdc77ec..c3a8ea73c9 100644
--- a/target/i386/bpt_helper.c
+++ b/target/i386/bpt_helper.c
@@ -53,7 +53,7 @@ static inline int hw_breakpoint_len(unsigned long dr7, int index)
static int hw_breakpoint_insert(CPUX86State *env, int index)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong dr7 = env->dr[7];
target_ulong drN = env->dr[index];
int err = 0;
@@ -97,7 +97,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int index)
static void hw_breakpoint_remove(CPUX86State *env, int index)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
switch (hw_breakpoint_type(env->dr[7], index)) {
case DR7_TYPE_BP_INST:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 722c5514d4..5b84629f91 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4221,8 +4221,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ X86CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
uint32_t pkg_offset;
uint32_t limit;
uint32_t signature[3];
diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c
index 49231f6b69..371792ce8b 100644
--- a/target/i386/excp_helper.c
+++ b/target/i386/excp_helper.c
@@ -90,7 +90,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
int next_eip_addend,
uintptr_t retaddr)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (!is_int) {
cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c
index ea5a0c4861..005f1f68f8 100644
--- a/target/i386/fpu_helper.c
+++ b/target/i386/fpu_helper.c
@@ -1477,7 +1477,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
env->pkru = 0;
}
if (env->pkru != old_pkru) {
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
tlb_flush(cs);
}
}
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 96336055f3..ff3a60c7cf 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -622,7 +622,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
int pe_state;
qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
@@ -664,19 +664,16 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
the PDPT */
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
{
- X86CPU *cpu = x86_env_get_cpu(env);
-
env->cr[3] = new_cr3;
if (env->cr[0] & CR0_PG_MASK) {
qemu_log_mask(CPU_LOG_MMU,
"CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
{
- X86CPU *cpu = x86_env_get_cpu(env);
uint32_t hflags;
#if defined(DEBUG_MMU)
@@ -685,7 +682,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
if ((new_cr4 ^ env->cr[4]) &
(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
/* Clear bits we're going to recompute. */
@@ -977,8 +974,8 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ X86CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
if (kvm_enabled() || whpx_enabled()) {
env->tpr_access_type = access;
@@ -996,8 +993,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
target_ulong *base, unsigned int *limit,
unsigned int *flags)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
SegmentCache *dt;
target_ulong ptr;
uint32_t e1, e2;
diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
index 78f2020ef2..3eff6885f8 100644
--- a/target/i386/misc_helper.c
+++ b/target/i386/misc_helper.c
@@ -133,7 +133,7 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
break;
case 8:
if (!(env->hflags2 & HF2_VINTR_MASK)) {
- val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
+ val = cpu_get_apic_tpr(env_archcpu(env)->apic_state);
} else {
val = env->v_tpr;
}
@@ -158,7 +158,7 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
case 8:
if (!(env->hflags2 & HF2_VINTR_MASK)) {
qemu_mutex_lock_iothread();
- cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
+ cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0);
qemu_mutex_unlock_iothread();
}
env->v_tpr = t0 & 0x0f;
@@ -180,7 +180,7 @@ void helper_lmsw(CPUX86State *env, target_ulong t0)
void helper_invlpg(CPUX86State *env, target_ulong addr)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
tlb_flush_page(CPU(cpu), addr);
@@ -247,7 +247,7 @@ void helper_wrmsr(CPUX86State *env)
env->sysenter_eip = val;
break;
case MSR_IA32_APICBASE:
- cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
+ cpu_set_apic_base(env_archcpu(env)->apic_state, val);
break;
case MSR_EFER:
{
@@ -404,7 +404,7 @@ void helper_rdmsr(CPUX86State *env)
val = env->sysenter_eip;
break;
case MSR_IA32_APICBASE:
- val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
+ val = cpu_get_apic_base(env_archcpu(env)->apic_state);
break;
case MSR_EFER:
val = env->efer;
@@ -561,7 +561,7 @@ static void do_hlt(X86CPU *cpu)
void helper_hlt(CPUX86State *env, int next_eip_addend)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
env->eip += next_eip_addend;
@@ -580,8 +580,8 @@ void helper_monitor(CPUX86State *env, target_ulong ptr)
void helper_mwait(CPUX86State *env, int next_eip_addend)
{
- CPUState *cs;
- X86CPU *cpu;
+ CPUState *cs = env_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
if ((uint32_t)env->regs[R_ECX] != 0) {
raise_exception_ra(env, EXCP0D_GPF, GETPC());
@@ -589,8 +589,6 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
env->eip += next_eip_addend;
- cpu = x86_env_get_cpu(env);
- cs = CPU(cpu);
/* XXX: not complete but not completely erroneous */
if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
do_pause(cpu);
@@ -601,7 +599,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
void helper_pause(CPUX86State *env, int next_eip_addend)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC());
env->eip += next_eip_addend;
@@ -611,7 +609,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend)
void helper_debug(CPUX86State *env)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_DEBUG;
cpu_loop_exit(cs);
@@ -631,7 +629,7 @@ uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if ((env->cr[4] & CR4_PKE_MASK) == 0) {
raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c
index 63e265cb38..87a627f9dc 100644
--- a/target/i386/seg_helper.c
+++ b/target/i386/seg_helper.c
@@ -137,7 +137,7 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
uint32_t *esp_ptr, int dpl,
uintptr_t retaddr)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
int type, index, shift;
#if 0
@@ -830,7 +830,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
int index;
#if 0
@@ -972,7 +972,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
#if defined(CONFIG_USER_ONLY)
void helper_syscall(CPUX86State *env, int next_eip_addend)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_SYSCALL;
env->exception_next_eip = env->eip + next_eip_addend;
@@ -1172,7 +1172,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
static void handle_even_inj(CPUX86State *env, int intno, int is_int,
int error_code, int is_hw, int rm)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
control.event_inj));
@@ -1312,7 +1312,7 @@ void x86_cpu_do_interrupt(CPUState *cs)
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
{
- do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
+ do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
}
bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
@@ -1763,7 +1763,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
target_ulong ssp, old_ssp, offset, sp;
LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=%d\n", new_cs, new_eip, shift);
- LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
+ LOG_PCALL_STATE(env_cpu(env));
if ((new_cs & 0xfffc) == 0) {
raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
}
@@ -2167,7 +2167,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,
}
LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
new_cs, new_eip, shift, addend);
- LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
+ LOG_PCALL_STATE(env_cpu(env));
if ((new_cs & 0xfffc) == 0) {
raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
}
diff --git a/target/i386/smm_helper.c b/target/i386/smm_helper.c
index c1c34a75db..eb5aa6eb3d 100644
--- a/target/i386/smm_helper.c
+++ b/target/i386/smm_helper.c
@@ -204,8 +204,8 @@ void do_smm_enter(X86CPU *cpu)
void helper_rsm(CPUX86State *env)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ X86CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
target_ulong sm_state;
int i, offset;
uint32_t val;
diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c
index 9fd22a883b..7b8105a1c3 100644
--- a/target/i386/svm_helper.c
+++ b/target/i386/svm_helper.c
@@ -84,7 +84,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
const SegmentCache *sc)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector),
sc->selector);
@@ -99,7 +99,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
SegmentCache *sc)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
unsigned int flags;
sc->selector = x86_lduw_phys(cs,
@@ -122,7 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong addr;
uint64_t nested_ctl;
uint32_t event_inj;
@@ -314,7 +314,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->hflags2 |= HF2_GIF_MASK;
if (int_ctl & V_IRQ_MASK) {
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
}
@@ -379,7 +379,7 @@ void helper_vmmcall(CPUX86State *env)
void helper_vmload(CPUX86State *env, int aflag)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong addr;
cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC());
@@ -419,7 +419,7 @@ void helper_vmload(CPUX86State *env, int aflag)
void helper_vmsave(CPUX86State *env, int aflag)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong addr;
cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC());
@@ -482,7 +482,7 @@ void helper_skinit(CPUX86State *env)
void helper_invlpga(CPUX86State *env, int aflag)
{
- X86CPU *cpu = x86_env_get_cpu(env);
+ X86CPU *cpu = env_archcpu(env);
target_ulong addr;
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC());
@@ -501,7 +501,7 @@ void helper_invlpga(CPUX86State *env, int aflag)
void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
uint64_t param, uintptr_t retaddr)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (likely(!(env->hflags & HF_GUEST_MASK))) {
return;
@@ -583,7 +583,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
uint32_t next_eip_addend)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */
@@ -604,7 +604,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1,
uintptr_t retaddr)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cpu_restore_state(cs, retaddr, true);
@@ -625,7 +625,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1,
void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
{
- CPUState *cs = CPU(x86_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t int_ctl;
if (env->hflags & HF_INHIBIT_IRQ_MASK) {
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 15/39] target/lm32: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (13 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 14/39] target/i386: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:08 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 16/39] target/m68k: " Richard Henderson
` (23 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/lm32/cpu.h | 5 -----
target/lm32/helper.c | 19 ++++++-------------
target/lm32/op_helper.c | 6 +++---
target/lm32/translate.c | 2 +-
4 files changed, 10 insertions(+), 22 deletions(-)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index c6b252f90a..8e7b70a275 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -195,11 +195,6 @@ struct LM32CPU {
uint32_t features;
};
-static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
-{
- return container_of(env, LM32CPU, env);
-}
-
#define ENV_OFFSET offsetof(LM32CPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/lm32/helper.c b/target/lm32/helper.c
index a039a993ff..674cbd7fe4 100644
--- a/target/lm32/helper.c
+++ b/target/lm32/helper.c
@@ -58,28 +58,23 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
-
- cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
+ cpu_breakpoint_insert(env_cpu(env), address, BP_CPU,
&env->cpu_breakpoint[idx]);
}
void lm32_breakpoint_remove(CPULM32State *env, int idx)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
-
if (!env->cpu_breakpoint[idx]) {
return;
}
- cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
+ cpu_breakpoint_remove_by_ref(env_cpu(env), env->cpu_breakpoint[idx]);
env->cpu_breakpoint[idx] = NULL;
}
void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
lm32_wp_t wp_type)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
int flags = 0;
switch (wp_type) {
@@ -98,26 +93,24 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
}
if (flags != 0) {
- cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
- &env->cpu_watchpoint[idx]);
+ cpu_watchpoint_insert(env_cpu(env), address, 1, flags,
+ &env->cpu_watchpoint[idx]);
}
}
void lm32_watchpoint_remove(CPULM32State *env, int idx)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
-
if (!env->cpu_watchpoint[idx]) {
return;
}
- cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
+ cpu_watchpoint_remove_by_ref(env_cpu(env), env->cpu_watchpoint[idx]);
env->cpu_watchpoint[idx] = NULL;
}
static bool check_watchpoints(CPULM32State *env)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
+ LM32CPU *cpu = env_archcpu(env);
int i;
for (i = 0; i < cpu->num_watchpoints; i++) {
diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c
index 234d55e056..ebff4c4518 100644
--- a/target/lm32/op_helper.c
+++ b/target/lm32/op_helper.c
@@ -16,7 +16,7 @@
#if !defined(CONFIG_USER_ONLY)
void raise_exception(CPULM32State *env, int index)
{
- CPUState *cs = CPU(lm32_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);
@@ -29,7 +29,7 @@ void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
void HELPER(hlt)(CPULM32State *env)
{
- CPUState *cs = CPU(lm32_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->halted = 1;
cs->exception_index = EXCP_HLT;
@@ -39,7 +39,7 @@ void HELPER(hlt)(CPULM32State *env)
void HELPER(ill)(CPULM32State *env)
{
#ifndef CONFIG_USER_ONLY
- CPUState *cs = CPU(lm32_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
fprintf(stderr, "VM paused due to illegal instruction. "
"Connect a debugger or switch to the monitor console "
"to find out more.\n");
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index f0e0e7058e..b9f2f2c4a7 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1053,7 +1053,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
CPULM32State *env = cs->env_ptr;
- LM32CPU *cpu = lm32_env_get_cpu(env);
+ LM32CPU *cpu = env_archcpu(env);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t page_start;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 16/39] target/m68k: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (14 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 15/39] target/lm32: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:16 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 17/39] target/microblaze: " Richard Henderson
` (22 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/m68k/target_cpu.h | 2 +-
target/m68k/cpu.h | 5 -----
linux-user/m68k-sim.c | 3 +--
linux-user/m68k/cpu_loop.c | 2 +-
target/m68k/helper.c | 33 ++++++++++++---------------------
target/m68k/m68k-semi.c | 4 ++--
target/m68k/op_helper.c | 12 ++++++------
target/m68k/translate.c | 4 +---
8 files changed, 24 insertions(+), 41 deletions(-)
diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h
index 7a26f3c3fc..bc7446fbaf 100644
--- a/linux-user/m68k/target_cpu.h
+++ b/linux-user/m68k/target_cpu.h
@@ -31,7 +31,7 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp)
static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
ts->tp_value = newtls;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 43ef30b7cb..f8d5a0819b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -163,11 +163,6 @@ struct M68kCPU {
CPUM68KState env;
};
-static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
-{
- return container_of(env, M68kCPU, env);
-}
-
#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu);
diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c
index 34d332d8b1..9bc6ff3d3a 100644
--- a/linux-user/m68k-sim.c
+++ b/linux-user/m68k-sim.c
@@ -91,7 +91,6 @@ static int translate_openflags(int flags)
#define ARG(x) tswap32(args[x])
void do_m68k_simcall(CPUM68KState *env, int nr)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
uint32_t *args;
args = (uint32_t *)(unsigned long)(env->aregs[7] + 4);
@@ -159,6 +158,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr)
check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2)));
break;
default:
- cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr);
+ cpu_abort(env_cpu(env), "Unsupported m68k sim syscall %d\n", nr);
}
}
diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
index 42d8d841ea..f2c33057b3 100644
--- a/linux-user/m68k/cpu_loop.c
+++ b/linux-user/m68k/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUM68KState *env)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
unsigned int n;
target_siginfo_t info;
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index d958a34959..6699f056a4 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -168,8 +168,6 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
switch (reg) {
case M68K_CR_CACR:
env->cacr = val;
@@ -186,7 +184,7 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
break;
/* TODO: Implement control registers. */
default:
- cpu_abort(CPU(cpu),
+ cpu_abort(env_cpu(env),
"Unimplemented control register write 0x%x = 0x%x\n",
reg, val);
}
@@ -194,8 +192,6 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
switch (reg) {
/* MC680[1234]0 */
case M68K_CR_SFC:
@@ -248,14 +244,13 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
env->mmu.ttr[M68K_DTTR1] = val;
return;
}
- cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n",
+ cpu_abort(env_cpu(env),
+ "Unimplemented control register write 0x%x = 0x%x\n",
reg, val);
}
uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
switch (reg) {
/* MC680[1234]0 */
case M68K_CR_SFC:
@@ -292,7 +287,7 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
case M68K_CR_DTT1:
return env->mmu.ttr[M68K_DTTR1];
}
- cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n",
+ cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
reg);
}
@@ -401,8 +396,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
uint32_t last_logical, last_physical;
int32_t size;
int last_attr = -1, attr = -1;
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
/* 8k page */
@@ -635,8 +629,7 @@ static int get_physical_address(CPUM68KState *env, hwaddr *physical,
int *prot, target_ulong address,
int access_type, target_ulong *page_size)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
uint32_t entry;
uint32_t next;
target_ulong page_mask;
@@ -1128,7 +1121,7 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc)
z = n; \
break; \
default: \
- cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); \
+ cpu_abort(env_cpu(env), "Bad CC_OP %d", op); \
} \
} while (0)
@@ -1311,8 +1304,6 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc)
#if defined(CONFIG_SOFTMMU)
void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
hwaddr physical;
int access_type;
int prot;
@@ -1337,7 +1328,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
if (ret == 0) {
addr &= TARGET_PAGE_MASK;
physical += addr & (page_size - 1);
- tlb_set_page(cs, addr, physical,
+ tlb_set_page(env_cpu(env), addr, physical,
prot, access_type & ACCESS_SUPER ?
MMU_KERNEL_IDX : MMU_USER_IDX, page_size);
}
@@ -1345,18 +1336,18 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
+ CPUState *cs = env_cpu(env);
switch (opmode) {
case 0: /* Flush page entry if not global */
case 1: /* Flush page entry */
- tlb_flush_page(CPU(cpu), addr);
+ tlb_flush_page(cs, addr);
break;
case 2: /* Flush all except global entries */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
case 3: /* Flush all entries */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
}
}
diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c
index 1402145c8f..6716b93b5a 100644
--- a/target/m68k/m68k-semi.c
+++ b/target/m68k/m68k-semi.c
@@ -421,7 +421,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
case HOSTED_INIT_SIM:
#if defined(CONFIG_USER_ONLY)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
TaskState *ts = cs->opaque;
/* Allocate the heap using sbrk. */
if (!ts->heap_limit) {
@@ -454,7 +454,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
#endif
return;
default:
- cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr);
+ cpu_abort(env_cpu(env), "Unsupported semihosting syscall %d\n", nr);
result = 0;
}
failed:
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 13fcaa74ef..39aa9310e1 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -211,7 +211,7 @@ static const char *m68k_exception_name(int index)
static void cf_interrupt_all(CPUM68KState *env, int is_hw)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t sp;
uint32_t sr;
uint32_t fmt;
@@ -289,7 +289,7 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
{
if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) {
/* all except 68000 */
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
switch (format) {
case 4:
*sp -= 4;
@@ -314,7 +314,7 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t sp;
uint32_t retaddr;
uint32_t vector;
@@ -526,7 +526,7 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = tt;
cpu_loop_exit_restore(cs, raddr);
@@ -1056,7 +1056,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub)
env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0;
if (val < 0 || val > ub) {
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* Recover PC and CC_OP for the beginning of the insn. */
cpu_restore_state(cs, GETPC(), true);
@@ -1087,7 +1087,7 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub)
env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb;
if (env->cc_c) {
- CPUState *cs = CPU(m68k_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* Recover PC and CC_OP for the beginning of the insn. */
cpu_restore_state(cs, GETPC(), true);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 58596278c2..e206b5e78a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4778,14 +4778,12 @@ DISAS_INSN(wddata)
DISAS_INSN(wdebug)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
-
if (IS_USER(s)) {
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
/* TODO: Implement wdebug. */
- cpu_abort(CPU(cpu), "WDEBUG not implemented");
+ cpu_abort(env_cpu(env), "WDEBUG not implemented");
}
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 17/39] target/microblaze: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (15 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 16/39] target/m68k: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 18/39] target/mips: " Richard Henderson
` (21 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is available.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.h | 35 ++++++++++++++------------------
linux-user/microblaze/cpu_loop.c | 2 +-
target/microblaze/mmu.c | 5 ++---
target/microblaze/op_helper.c | 2 +-
target/microblaze/translate.c | 2 +-
5 files changed, 20 insertions(+), 26 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index c5af1c6076..7b85beb556 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -310,11 +310,6 @@ struct MicroBlazeCPU {
CPUMBState env;
};
-static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
-{
- return container_of(env, MicroBlazeCPU, env);
-}
-
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
@@ -344,21 +339,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
-{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
-
- /* Are we in nommu mode?. */
- if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
- return MMU_NOMMU_IDX;
- }
-
- if (env->sregs[SR_MSR] & MSR_UM) {
- return MMU_USER_IDX;
- }
- return MMU_KERNEL_IDX;
-}
-
int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
int mmu_idx);
@@ -383,4 +363,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
MemTxResult response, uintptr_t retaddr);
#endif
+static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
+{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
+ /* Are we in nommu mode?. */
+ if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
+ return MMU_NOMMU_IDX;
+ }
+
+ if (env->sregs[SR_MSR] & MSR_UM) {
+ return MMU_USER_IDX;
+ }
+ return MMU_KERNEL_IDX;
+}
+
#endif
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
index 076bdb9a61..a6ea71401d 100644
--- a/linux-user/microblaze/cpu_loop.c
+++ b/linux-user/microblaze/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUMBState *env)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index fcf86b12d5..6763421ba2 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -34,7 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)
static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
uint32_t tlb_tag, end, t;
@@ -228,7 +228,6 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
uint64_t tmp64;
unsigned int i;
qemu_log_mask(CPU_LOG_MMU,
@@ -269,7 +268,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
/* Changes to the zone protection reg flush the QEMU TLB.
Fortunately, these are very uncommon. */
if (v != env->mmu.regs[rn]) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
env->mmu.regs[rn] = v;
break;
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index e23dcfdc20..aa91d3a257 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -84,7 +84,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
void helper_raise_exception(CPUMBState *env, uint32_t index)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 885fc44b51..9ce65f3bcf 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1604,7 +1604,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
CPUMBState *env = cs->env_ptr;
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+ MicroBlazeCPU *cpu = env_archcpu(env);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (16 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 17/39] target/microblaze: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 8:15 ` Aleksandar Markovic
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 19/39] target/moxie: " Richard Henderson
` (20 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/cpu.h | 5 -----
hw/intc/mips_gic.c | 2 +-
hw/mips/mips_int.c | 2 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/helper.c | 15 +++++----------
target/mips/op_helper.c | 25 +++++++++++--------------
target/mips/translate.c | 3 +--
target/mips/translate_init.inc.c | 4 +---
8 files changed, 21 insertions(+), 37 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 31e15834ca..e0645eb1d1 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1051,11 +1051,6 @@ struct MIPSCPU {
CPUMIPSState env;
};
-static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
-{
- return container_of(env, MIPSCPU, env);
-}
-
#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list(void);
diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c
index 15e6e40f9f..8f509493ea 100644
--- a/hw/intc/mips_gic.c
+++ b/hw/intc/mips_gic.c
@@ -44,7 +44,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin)
GIC_VP_MASK_CMP_SHF;
}
if (kvm_enabled()) {
- kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env),
+ kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env),
pin + GIC_CPU_PIN_OFFSET,
ored_level);
} else {
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 5ddeb15848..f899f6ceb3 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -76,7 +76,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
qemu_irq *qi;
int i;
- qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
+ qi = qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 828137cd84..ac6c6d1504 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -425,7 +425,7 @@ static int do_break(CPUMIPSState *env, target_siginfo_t *info,
void cpu_loop(CPUMIPSState *env)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_siginfo_t info;
int trapnr;
abi_long ret;
diff --git a/target/mips/helper.c b/target/mips/helper.c
index c44cdca3b5..1fc0a4ce4b 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -336,10 +336,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
void cpu_mips_tlb_flush(CPUMIPSState *env)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
-
/* Flush qemu's TLB and discard all shadowed entries. */
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
@@ -401,7 +399,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
#if defined(TARGET_MIPS64)
if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
/* Access to at least one of the 64-bit segments has been disabled */
- tlb_flush(CPU(mips_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
}
#endif
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
@@ -446,7 +444,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int exception = 0, error_code = 0;
if (rw == MMU_INST_FETCH) {
@@ -1400,8 +1398,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs;
+ CPUState *cs = env_cpu(env);
r4k_tlb_t *tlb;
target_ulong addr;
target_ulong end;
@@ -1427,7 +1424,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
if (tlb->V0) {
- cs = CPU(cpu);
addr = tlb->VPN & ~mask;
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@@ -1441,7 +1437,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
}
}
if (tlb->V1) {
- cs = CPU(cpu);
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@@ -1462,7 +1457,7 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
int error_code,
uintptr_t pc)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
__func__, exception, error_code);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0f272a5b93..0705e8c686 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -350,7 +350,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
int rw, uintptr_t retaddr)
{
hwaddr paddr;
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
paddr = cpu_mips_translate_address(env, address, rw);
@@ -699,7 +699,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
return env;
}
- cs = CPU(mips_env_get_cpu(env));
+ cs = env_cpu(env);
vpe_idx = tc_idx / cs->nr_threads;
*tc = tc_idx % cs->nr_threads;
other_cs = qemu_get_cpu(vpe_idx);
@@ -1298,7 +1298,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
+ MIPSCPU *cpu = env_archcpu(env);
env->active_tc.CP0_TCHalt = arg1 & 0x1;
@@ -1314,7 +1314,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- MIPSCPU *other_cpu = mips_env_get_cpu(other);
+ MIPSCPU *other_cpu = env_archcpu(other);
// TODO: Halt TC / Restart (if allocated+active) TC.
@@ -1427,7 +1427,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
tlb_flush(cs);
@@ -1435,7 +1435,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
tlb_flush(cs);
@@ -1443,7 +1443,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
tlb_flush(cs);
@@ -1666,7 +1666,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
/* If the ASID changes, flush qemu's TLB. */
if ((old & env->CP0_EntryHi_ASID_mask) !=
(val & env->CP0_EntryHi_ASID_mask)) {
- tlb_flush(CPU(mips_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
}
}
@@ -1686,7 +1686,6 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
uint32_t val, old;
old = env->CP0_Status;
@@ -1706,7 +1705,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
default:
- cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
+ cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
}
}
@@ -2485,8 +2484,6 @@ static void debug_pre_eret(CPUMIPSState *env)
static void debug_post_eret(CPUMIPSState *env)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
-
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
@@ -2502,7 +2499,7 @@ static void debug_post_eret(CPUMIPSState *env)
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
default:
- cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
+ cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
}
}
@@ -2633,7 +2630,7 @@ void helper_pmon(CPUMIPSState *env, int function)
void helper_wait(CPUMIPSState *env)
{
- CPUState *cs = CPU(mips_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f96c0d01ef..8043e8d398 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29912,8 +29912,7 @@ void cpu_set_exception_base(int vp_index, target_ulong address)
void cpu_state_reset(CPUMIPSState *env)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 1c2d017d36..6d145a905a 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -871,8 +871,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
-
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
switch (def->mmu_type) {
@@ -889,7 +887,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
case MMU_TYPE_R6000:
case MMU_TYPE_R8000:
default:
- cpu_abort(CPU(cpu), "MMU type not supported\n");
+ cpu_abort(env_cpu(env), "MMU type not supported\n");
}
}
#endif /* CONFIG_USER_ONLY */
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 19/39] target/moxie: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (17 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 18/39] target/mips: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:19 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 20/39] target/nios2: " Richard Henderson
` (19 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/moxie/cpu.h | 5 -----
target/moxie/helper.c | 6 +++---
target/moxie/translate.c | 2 +-
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 5b9aae95d2..a481a92833 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -90,11 +90,6 @@ typedef struct MoxieCPU {
CPUMoxieState env;
} MoxieCPU;
-static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
-{
- return container_of(env, MoxieCPU, env);
-}
-
#define ENV_OFFSET offsetof(MoxieCPU, env)
void moxie_cpu_do_interrupt(CPUState *cs);
diff --git a/target/moxie/helper.c b/target/moxie/helper.c
index 287a45232c..a18b21c4c0 100644
--- a/target/moxie/helper.c
+++ b/target/moxie/helper.c
@@ -42,7 +42,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
void helper_raise_exception(CPUMoxieState *env, int ex)
{
- CPUState *cs = CPU(moxie_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = ex;
/* Stash the exception type. */
@@ -79,7 +79,7 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
void helper_debug(CPUMoxieState *env)
{
- CPUState *cs = CPU(moxie_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_DEBUG;
cpu_loop_exit(cs);
@@ -89,7 +89,7 @@ void helper_debug(CPUMoxieState *env)
void moxie_cpu_do_interrupt(CPUState *cs)
{
- CPUState *cs = CPU(moxie_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = -1;
}
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index c668178f2c..c87e9ec2b1 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -816,7 +816,7 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
CPUMoxieState *env = cs->env_ptr;
- MoxieCPU *cpu = moxie_env_get_cpu(env);
+ MoxieCPU *cpu = env_archcpu(env);
DisasContext ctx;
target_ulong pc_start;
int num_insns;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 20/39] target/nios2: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (18 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 19/39] target/moxie: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:20 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 21/39] target/openrisc: " Richard Henderson
` (18 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 5 -----
hw/nios2/cpu_pic.c | 5 +----
target/nios2/mmu.c | 10 +++++-----
3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index b14095b8dc..f2ffc1469f 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -193,11 +193,6 @@ typedef struct Nios2CPU {
uint32_t fast_tlb_miss_addr;
} Nios2CPU;
-static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
-{
- return NIOS2_CPU(container_of(env, Nios2CPU, env));
-}
-
#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c
index 6bccce2f32..9e39955bd1 100644
--- a/hw/nios2/cpu_pic.c
+++ b/hw/nios2/cpu_pic.c
@@ -54,12 +54,9 @@ static void nios2_pic_cpu_handler(void *opaque, int irq, int level)
void nios2_check_interrupts(CPUNios2State *env)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
-
if (env->irq_pending) {
env->irq_pending = 0;
- cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
}
}
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 33382bad1b..61eaa06b3e 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -73,7 +73,7 @@ unsigned int mmu_translate(CPUNios2State *env,
Nios2MMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
int vpn = vaddr >> 12;
@@ -115,7 +115,7 @@ unsigned int mmu_translate(CPUNios2State *env,
static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
{
CPUState *cs = env_cpu(env);
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
int idx;
MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
@@ -139,7 +139,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
{
CPUState *cs = env_cpu(env);
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
@@ -256,7 +256,7 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
void mmu_init(CPUNios2State *env)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
Nios2MMU *mmu = &env->mmu;
MMU_LOG(qemu_log("mmu_init\n"));
@@ -267,7 +267,7 @@ void mmu_init(CPUNios2State *env)
void dump_mmu(CPUNios2State *env)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
+ Nios2CPU *cpu = env_archcpu(env);
int i;
qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 21/39] target/openrisc: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (19 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 20/39] target/nios2: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:20 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 22/39] target/ppc: " Richard Henderson
` (17 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/cpu.h | 5 -----
linux-user/openrisc/cpu_loop.c | 2 +-
target/openrisc/exception_helper.c | 5 ++---
target/openrisc/sys_helper.c | 8 ++++----
4 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 0ba4ae3356..91ba667139 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -317,11 +317,6 @@ typedef struct OpenRISCCPU {
} OpenRISCCPU;
-static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
-{
- return container_of(env, OpenRISCCPU, env);
-}
-
#define ENV_OFFSET offsetof(OpenRISCCPU, env)
void cpu_openrisc_list(void);
diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c
index f496e4b48a..4b8165b261 100644
--- a/linux-user/openrisc/cpu_loop.c
+++ b/linux-user/openrisc/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUOpenRISCState *env)
{
- CPUState *cs = CPU(openrisc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
abi_long ret;
target_siginfo_t info;
diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception_helper.c
index 6073a5b21c..dd639ba5f2 100644
--- a/target/openrisc/exception_helper.c
+++ b/target/openrisc/exception_helper.c
@@ -25,15 +25,14 @@
void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ OpenRISCCPU *cpu = env_archcpu(env);
raise_exception(cpu, excp);
}
static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_RANGE;
cpu_loop_exit_restore(cs, pc);
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 05f66c455b..8f11cb8202 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -30,8 +30,8 @@
void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
{
#ifndef CONFIG_USER_ONLY
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ OpenRISCCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
target_ulong mr;
int idx;
@@ -194,8 +194,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
{
#ifndef CONFIG_USER_ONLY
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ OpenRISCCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
int idx;
switch (spr) {
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 22/39] target/ppc: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (20 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 21/39] target/openrisc: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:28 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 23/39] target/riscv: " Richard Henderson
` (16 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 7 +-
target/ppc/helper_regs.h | 4 +-
hw/ppc/ppc.c | 18 ++---
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc_booke.c | 4 +-
linux-user/ppc/cpu_loop.c | 2 +-
target/ppc/excp_helper.c | 14 ++--
target/ppc/fpu_helper.c | 14 ++--
target/ppc/kvm.c | 5 +-
target/ppc/misc_helper.c | 22 ++----
target/ppc/mmu-hash64.c | 14 ++--
target/ppc/mmu_helper.c | 115 +++++++++++++-------------------
target/ppc/translate_init.inc.c | 85 ++++++++++++-----------
13 files changed, 134 insertions(+), 172 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3449b0b085..ef00a3415d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1203,11 +1203,6 @@ struct PowerPCCPU {
int32_t mig_slb_nr;
};
-static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
-{
- return container_of(env, PowerPCCPU, env);
-}
-
#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
@@ -2451,7 +2446,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
}
}
- cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
+ cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
return 0;
}
diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
index 922da76c6c..85dfe7687f 100644
--- a/target/ppc/helper_regs.h
+++ b/target/ppc/helper_regs.h
@@ -116,7 +116,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
{
int excp;
#if !defined(CONFIG_USER_ONLY)
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
#endif
excp = 0;
@@ -175,7 +175,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
#if !defined(CONFIG_USER_ONLY)
static inline void check_tlb_flush(CPUPPCState *env, bool global)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* Handle global flushes first */
if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index ad20584f26..debcdab993 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -385,7 +385,7 @@ void ppc40x_system_reset(PowerPCCPU *cpu)
void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
switch ((val >> 28) & 0x3) {
case 0x0:
@@ -785,7 +785,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env)
target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
ppc_tb_t *tb_env = env->tb_env;
uint64_t hdecr;
@@ -923,7 +923,7 @@ static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr,
void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
int nr_bits = 32;
@@ -955,7 +955,7 @@ static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr,
void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
_cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value,
@@ -980,7 +980,7 @@ static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
CPUPPCState *env = opaque;
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_tb_t *tb_env = env->tb_env;
tb_env->tb_freq = freq;
@@ -1095,7 +1095,7 @@ const VMStateDescription vmstate_ppc_timebase = {
/* Set up (once) timebase frequency (in Hz) */
clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_tb_t *tb_env;
tb_env = g_malloc0(sizeof(ppc_tb_t));
@@ -1165,7 +1165,7 @@ static void cpu_4xx_fit_cb (void *opaque)
uint64_t now, next;
env = opaque;
- cpu = ppc_env_get_cpu(env);
+ cpu = env_archcpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -1235,7 +1235,7 @@ static void cpu_4xx_pit_cb (void *opaque)
ppc40x_timer_t *ppc40x_timer;
env = opaque;
- cpu = ppc_env_get_cpu(env);
+ cpu = env_archcpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
env->spr[SPR_40x_TSR] |= 1 << 27;
@@ -1261,7 +1261,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
uint64_t now, next;
env = opaque;
- cpu = ppc_env_get_cpu(env);
+ cpu = env_archcpu(env);
tb_env = env->tb_env;
ppc40x_timer = tb_env->opaque;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3ae7f6d4df..018dcca888 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -49,7 +49,7 @@
ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
ram_addr_t bdloc;
int i, n;
diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c
index 4f11e00a17..323413e074 100644
--- a/hw/ppc/ppc_booke.c
+++ b/hw/ppc/ppc_booke.c
@@ -249,7 +249,7 @@ static void booke_wdt_cb(void *opaque)
void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_tb_t *tb_env = env->tb_env;
booke_timer_t *booke_timer = tb_env->opaque;
@@ -277,7 +277,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val)
void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_tb_t *tb_env = env->tb_env;
booke_timer_t *booke_timer = tb_env->opaque;
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index 801f5ace29..24dfdba854 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -67,7 +67,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
void cpu_loop(CPUPPCState *env)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_siginfo_t info;
int trapnr;
target_ulong ret;
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index ec2c177091..50b004d00d 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -49,7 +49,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
static void ppc_hw_interrupt(CPUPPCState *env)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
@@ -792,7 +792,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
static void ppc_hw_interrupt(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
bool async_deliver;
/* External reset */
@@ -931,7 +931,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
* It generally means a discrepancy between the wakup conditions in the
* processor has_work implementation and the logic in this function.
*/
- cpu_abort(CPU(ppc_env_get_cpu(env)),
+ cpu_abort(env_cpu(env),
"Wakeup from PM state but interrupt Undelivered");
}
}
@@ -974,7 +974,7 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
uint32_t error_code, uintptr_t raddr)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = exception;
env->error_code = error_code;
@@ -1015,7 +1015,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)
uint32_t excp = hreg_store_msr(env, val, 0);
if (excp != 0) {
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cpu_interrupt_exittb(cs);
raise_exception(env, excp);
}
@@ -1026,7 +1026,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
{
CPUState *cs;
- cs = CPU(ppc_env_get_cpu(env));
+ cs = env_cpu(env);
cs->halted = 1;
/*
@@ -1043,7 +1043,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* MSR:POW cannot be set by any form of rfi */
msr &= ~(1ULL << MSR_POW);
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0b7308f539..ffbd19afa1 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -271,7 +271,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
env->fpscr |= FP_FX;
/* We must update the target FPR before raising the exception */
if (fpscr_ve != 0) {
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
@@ -315,7 +315,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
static inline void float_overflow_excp(CPUPPCState *env)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
@@ -335,7 +335,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
static inline void float_underflow_excp(CPUPPCState *env)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
@@ -352,7 +352,7 @@ static inline void float_underflow_excp(CPUPPCState *env)
static inline void float_inexact_excp(CPUPPCState *env)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->fpscr |= 1 << FPSCR_FI;
env->fpscr |= 1 << FPSCR_XX;
@@ -442,7 +442,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int prev;
prev = (env->fpscr >> bit) & 1;
@@ -574,7 +574,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong prev, new;
int i;
@@ -612,7 +612,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int status = get_float_exception_flags(&env->fp_status);
bool inexact_happened = false;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 02e22e2017..4228cddcdc 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1989,9 +1989,8 @@ static int kvmppc_get_dec_bits(void)
}
static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
- {
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+{
+ CPUState *cs = env_cpu(env);
if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
!kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 0a81e98ee9..49a8a02363 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -81,28 +81,24 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
void helper_store_sdr1(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
if (env->spr[SPR_SDR1] != val) {
ppc_store_sdr1(env, val);
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
#if defined(TARGET_PPC64)
void helper_store_ptcr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
if (env->spr[SPR_PTCR] != val) {
ppc_store_ptcr(env, val);
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
void helper_store_pcr(CPUPPCState *env, target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
env->spr[SPR_PCR] = value & pcc->pcr_mask;
@@ -111,16 +107,12 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value)
void helper_store_pidr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
env->spr[SPR_BOOKS_PID] = val;
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void helper_store_lpidr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
env->spr[SPR_LPIDR] = val;
/*
@@ -129,7 +121,7 @@ void helper_store_lpidr(CPUPPCState *env, target_ulong val)
* potentially access and cache entries for the current LPID as
* well.
*/
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
@@ -151,12 +143,10 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
if (likely(env->pb[num] != value)) {
env->pb[num] = value;
/* Should be optimized */
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7899eb2918..da8966ccf5 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -96,7 +96,7 @@ void dump_slb(PowerPCCPU *cpu)
void helper_slbia(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
int n;
/* XXX: Warning: slbia never invalidates the first segment */
@@ -118,7 +118,7 @@ void helper_slbia(CPUPPCState *env)
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_slb_t *slb;
slb = slb_lookup(cpu, addr);
@@ -251,7 +251,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
@@ -261,7 +261,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
@@ -273,7 +273,7 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
@@ -285,7 +285,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
@@ -1163,7 +1163,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc_store_lpcr(cpu, val);
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b32693f24e..44afcee461 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -239,7 +239,6 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc6xx_tlb_t *tlb;
int nr, max;
@@ -253,7 +252,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
tlb = &env->tlb.tlb6[nr];
pte_invalidate(&tlb->pte0);
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
@@ -261,7 +260,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
int is_code, int match_epn)
{
#if !defined(FLUSH_ALL_TLBS)
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
ppc6xx_tlb_t *tlb;
int way, nr;
@@ -474,7 +473,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
hwaddr hash;
target_ulong vsid;
int ds, pr, target_page_bits;
@@ -670,7 +669,6 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
/* Helpers specific to PowerPC 40x implementations */
static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
int i;
@@ -678,7 +676,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
tlb = &env->tlb.tlbe[i];
tlb->prot &= ~PAGE_VALID;
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
@@ -749,11 +747,10 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
void store_40x_sler(CPUPPCState *env, uint32_t val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
/* XXX: TO BE FIXED */
if (val != 0x00000000) {
- cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n");
+ cpu_abort(env_cpu(env),
+ "Little-endian regions are not supported by now\n");
}
env->spr[SPR_405_SLER] = val;
}
@@ -863,7 +860,6 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
static void booke206_flush_tlb(CPUPPCState *env, int flags,
const int check_iprot)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
int tlb_size;
int i, j;
ppcmas_tlb_t *tlb = env->tlb.tlbm;
@@ -880,7 +876,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
tlb += booke206_tlb_size(env, i);
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
@@ -1275,7 +1271,7 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
static void mmu6xx_dump_mmu(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
ppc6xx_tlb_t *tlb;
target_ulong sr;
int type, way, entry, i;
@@ -1347,13 +1343,13 @@ void dump_mmu(CPUPPCState *env)
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_07:
- dump_slb(ppc_env_get_cpu(env));
+ dump_slb(env_archcpu(env));
break;
case POWERPC_MMU_3_00:
- if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
+ if (ppc64_v3_radix(env_archcpu(env))) {
/* TODO - Unsupported */
} else {
- dump_slb(ppc_env_get_cpu(env));
+ dump_slb(env_archcpu(env));
break;
}
#endif
@@ -1419,7 +1415,6 @@ static int get_physical_address_wtlb(
target_ulong eaddr, int rw, int access_type,
int mmu_idx)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
int ret = -1;
bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
|| (access_type != ACCESS_CODE && msr_dr == 0);
@@ -1460,18 +1455,18 @@ static int get_physical_address_wtlb(
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
+ cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_REAL:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, rw);
} else {
- cpu_abort(CPU(cpu),
+ cpu_abort(env_cpu(env),
"PowerPC in real mode do not do any translation\n");
}
return -1;
default:
- cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n");
+ cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n");
return -1;
}
@@ -1583,7 +1578,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
int rw, int mmu_idx)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
PowerPCCPU *cpu = POWERPC_CPU(cs);
mmu_ctx_t ctx;
int access_type;
@@ -1815,7 +1810,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
target_ulong mask)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong base, end, page;
base = BATu & ~0x0001FFFF;
@@ -1847,7 +1842,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
#if defined(FLUSH_ALL_TLBS)
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
#endif
dump_store_bat(env, 'I', 0, nr, value);
@@ -1868,7 +1863,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
#if !defined(FLUSH_ALL_TLBS)
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
#else
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
#endif
}
}
@@ -1883,7 +1878,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
#if defined(FLUSH_ALL_TLBS)
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
#endif
dump_store_bat(env, 'D', 0, nr, value);
@@ -1904,7 +1899,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
#if !defined(FLUSH_ALL_TLBS)
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
#else
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
#endif
}
}
@@ -1919,7 +1914,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
{
target_ulong mask;
#if defined(FLUSH_ALL_TLBS)
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
int do_inval;
#endif
@@ -1953,7 +1948,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
}
#if defined(FLUSH_ALL_TLBS)
if (do_inval) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
#endif
}
@@ -1964,7 +1959,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
#if !defined(FLUSH_ALL_TLBS)
target_ulong mask;
#else
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
int do_inval;
#endif
@@ -1993,7 +1988,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
env->DBAT[1][nr] = value;
#if defined(FLUSH_ALL_TLBS)
if (do_inval) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
#endif
}
@@ -2003,12 +1998,10 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
/* TLB management */
void ppc_tlb_invalidate_all(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
env->tlb_need_flush = 0;
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
} else
#endif /* defined(TARGET_PPC64) */
switch (env->mmu_model) {
@@ -2021,14 +2014,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
ppc4xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_REAL:
- cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
+ cpu_abort(env_cpu(env), "No TLB for PowerPC 4xx in real mode\n");
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
+ cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE:
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
break;
case POWERPC_MMU_BOOKE206:
booke206_flush_tlb(env, -1, 0);
@@ -2036,11 +2029,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
env->tlb_need_flush = 0;
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
break;
default:
/* XXX: TODO */
- cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model);
+ cpu_abort(env_cpu(env), "Unknown MMU model %x\n", env->mmu_model);
break;
}
}
@@ -2091,7 +2084,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
/* Special registers manipulation */
void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
assert(!cpu->vhyp);
#if defined(TARGET_PPC64)
@@ -2118,7 +2111,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
#if defined(TARGET_PPC64)
void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
target_ulong patbsize = value & PTCR_PATS;
@@ -2163,7 +2156,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
(int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = env_archcpu(env);
uint64_t esid, vsid;
/* ESID = srnum */
@@ -2190,7 +2183,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
page = (16 << 20) * srnum;
end = page + (16 << 20);
for (; page != end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(CPU(cpu), page);
+ tlb_flush_page(env_cpu(env), page);
}
}
#else
@@ -2212,12 +2205,10 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr)
void helper_tlbiva(CPUPPCState *env, target_ulong addr)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
/* tlbiva instruction only exists on BookE */
assert(env->mmu_model == POWERPC_MMU_BOOKE);
/* XXX: TODO */
- cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
+ cpu_abort(env_cpu(env), "BookE MMU model is not implemented\n");
}
/* Software driven TLBs management */
@@ -2433,8 +2424,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry)
void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
ppcemb_tlb_t *tlb;
target_ulong page, end;
@@ -2529,7 +2519,6 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
target_ulong value)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
target_ulong EPN, RPN, size;
int do_flush_tlbs;
@@ -2565,13 +2554,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
}
tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
if (do_flush_tlbs) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
break;
case 1:
RPN = value & 0xFFFFFC0F;
if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
tlb->RPN = RPN;
break;
@@ -2665,7 +2654,6 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address)
static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint32_t tlbncfg = 0;
int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT;
int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK);
@@ -2675,7 +2663,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb];
if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) {
- cpu_abort(CPU(cpu), "we don't support HES yet\n");
+ cpu_abort(env_cpu(env), "we don't support HES yet\n");
}
return booke206_get_tlbm(env, tlb, ea, esel);
@@ -2683,40 +2671,33 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
env->spr[pidn] = pid;
/* changing PIDs mean we're in a different address space now */
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void helper_booke_set_eplc(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
env->spr[SPR_BOOKE_EPLC] = val & EPID_MASK;
- tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD);
+ tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_LOAD);
}
void helper_booke_set_epsc(CPUPPCState *env, target_ulong val)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
env->spr[SPR_BOOKE_EPSC] = val & EPID_MASK;
- tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE);
+ tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_STORE);
}
static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
-
if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
- tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
+ tlb_flush_page(env_cpu(env), tlb->mas2 & MAS2_EPN_MASK);
} else {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
void helper_booke206_tlbwe(CPUPPCState *env)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint32_t tlbncfg, tlbn;
ppcmas_tlb_t *tlb;
uint32_t size_tlb, size_ps;
@@ -2770,7 +2751,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
}
if (msr_gs) {
- cpu_abort(CPU(cpu), "missing HV implementation\n");
+ cpu_abort(env_cpu(env), "missing HV implementation\n");
}
if (tlb->mas1 & MAS1_VALID) {
@@ -2968,7 +2949,6 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address)
void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
int i, j;
int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
ppcmas_tlb_t *tlb = env->tlb.tlbm;
@@ -2985,12 +2965,11 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
}
tlb += booke206_tlb_size(env, i);
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
int i, j;
ppcmas_tlb_t *tlb;
int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
@@ -3026,7 +3005,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
tlb->mas1 &= ~MAS1_VALID;
}
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 0394a9ddad..6343e25624 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -3432,7 +3432,7 @@ static void init_proc_401(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(12, 16, 20, 24);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3486,7 +3486,7 @@ static void init_proc_401x2(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(12, 16, 20, 24);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3538,7 +3538,7 @@ static void init_proc_401x3(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(12, 16, 20, 24);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3597,7 +3597,7 @@ static void init_proc_IOP480(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(8, 12, 16, 20);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3648,7 +3648,7 @@ static void init_proc_403(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(8, 12, 16, 20);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3714,7 +3714,7 @@ static void init_proc_403GCX(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(8, 12, 16, 20);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3780,7 +3780,7 @@ static void init_proc_405(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(8, 12, 16, 20);
SET_WDT_PERIOD(16, 20, 24, 28);
@@ -3878,7 +3878,7 @@ static void init_proc_440EP(CPUPPCState *env)
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(12, 16, 20, 24);
SET_WDT_PERIOD(20, 24, 28, 32);
@@ -4186,7 +4186,7 @@ static void init_proc_440x5(CPUPPCState *env)
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
- ppc40x_irq_init(ppc_env_get_cpu(env));
+ ppc40x_irq_init(env_archcpu(env));
SET_FIT_PERIOD(12, 16, 20, 24);
SET_WDT_PERIOD(20, 24, 28, 32);
@@ -4392,7 +4392,7 @@ static void init_proc_G2(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
@@ -4472,7 +4472,7 @@ static void init_proc_G2LE(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
@@ -4727,7 +4727,7 @@ static void init_proc_e300(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
@@ -4805,7 +4805,6 @@ enum fsl_e500_version {
static void init_proc_e500(CPUPPCState *env, int version)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint32_t tlbncfg[2];
uint64_t ivor_mask;
uint64_t ivpr_mask = 0xFFFF0000ULL;
@@ -4877,7 +4876,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
tlbncfg[1] = 0x40028040;
break;
default:
- cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
+ cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
env->spr[SPR_PVR]);
}
#endif
@@ -4902,7 +4901,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
l1cfg1 |= 0x0B83820;
break;
default:
- cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
+ cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
env->spr[SPR_PVR]);
}
gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
@@ -5018,7 +5017,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
init_excp_e200(env, ivpr_mask);
/* Allocate hardware IRQ controller */
- ppce500_irq_init(ppc_env_get_cpu(env));
+ ppce500_irq_init(env_archcpu(env));
}
static void init_proc_e500v1(CPUPPCState *env)
@@ -5291,7 +5290,7 @@ static void init_proc_601(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 64;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
@@ -5396,7 +5395,7 @@ static void init_proc_602(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
@@ -5466,7 +5465,7 @@ static void init_proc_603(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
@@ -5533,7 +5532,7 @@ static void init_proc_603E(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
@@ -5594,7 +5593,7 @@ static void init_proc_604(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
@@ -5678,7 +5677,7 @@ static void init_proc_604E(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
@@ -5749,7 +5748,7 @@ static void init_proc_740(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
@@ -5829,7 +5828,7 @@ static void init_proc_750(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
@@ -5993,7 +5992,7 @@ static void init_proc_750cl(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
@@ -6115,7 +6114,7 @@ static void init_proc_750cx(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
@@ -6203,7 +6202,7 @@ static void init_proc_750fx(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
@@ -6291,7 +6290,7 @@ static void init_proc_750gx(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
@@ -6370,7 +6369,7 @@ static void init_proc_745(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
@@ -6457,7 +6456,7 @@ static void init_proc_755(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
@@ -6527,7 +6526,7 @@ static void init_proc_7400(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
@@ -6612,7 +6611,7 @@ static void init_proc_7410(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
@@ -6723,7 +6722,7 @@ static void init_proc_7440(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
@@ -6857,7 +6856,7 @@ static void init_proc_7450(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
@@ -6994,7 +6993,7 @@ static void init_proc_7445(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
@@ -7133,7 +7132,7 @@ static void init_proc_7455(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
@@ -7296,7 +7295,7 @@ static void init_proc_7457(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
@@ -7434,7 +7433,7 @@ static void init_proc_e600(CPUPPCState *env)
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
- ppc6xx_irq_init(ppc_env_get_cpu(env));
+ ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
@@ -8298,7 +8297,7 @@ static void init_proc_970(CPUPPCState *env)
/* Allocate hardware IRQ controller */
init_excp_970(env);
- ppc970_irq_init(ppc_env_get_cpu(env));
+ ppc970_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
@@ -8372,7 +8371,7 @@ static void init_proc_power5plus(CPUPPCState *env)
/* Allocate hardware IRQ controller */
init_excp_970(env);
- ppc970_irq_init(ppc_env_get_cpu(env));
+ ppc970_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
@@ -8487,7 +8486,7 @@ static void init_proc_POWER7(CPUPPCState *env)
/* Allocate hardware IRQ controller */
init_excp_POWER7(env);
- ppcPOWER7_irq_init(ppc_env_get_cpu(env));
+ ppcPOWER7_irq_init(env_archcpu(env));
}
static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -8639,7 +8638,7 @@ static void init_proc_POWER8(CPUPPCState *env)
/* Allocate hardware IRQ controller */
init_excp_POWER8(env);
- ppcPOWER7_irq_init(ppc_env_get_cpu(env));
+ ppcPOWER7_irq_init(env_archcpu(env));
}
static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -8838,7 +8837,7 @@ static void init_proc_POWER9(CPUPPCState *env)
/* Allocate hardware IRQ controller */
init_excp_POWER9(env);
- ppcPOWER9_irq_init(ppc_env_get_cpu(env));
+ ppcPOWER9_irq_init(env_archcpu(env));
}
static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 23/39] target/riscv: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (21 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 22/39] target/ppc: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 24/39] target/s390x: " Richard Henderson
` (15 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 5 -----
linux-user/riscv/cpu_loop.c | 2 +-
target/riscv/cpu_helper.c | 4 ++--
target/riscv/csr.c | 12 ++++++------
target/riscv/op_helper.c | 8 ++++----
5 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cd4f2de798..c32428a4ef 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -211,11 +211,6 @@ typedef struct RISCVCPU {
CPURISCVState env;
} RISCVCPU;
-static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
-{
- return container_of(env, RISCVCPU, env);
-}
-
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
return (env->misa & ext) != 0;
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 31700f75d0..c1134597fd 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -25,7 +25,7 @@
void cpu_loop(CPURISCVState *env)
{
- CPUState *cs = CPU(riscv_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, signum, sigcode;
target_ulong sigaddr;
target_ulong ret;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b17f169681..72f82c1ccf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -191,7 +191,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
}
- CPUState *cs = CPU(riscv_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits;
target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
@@ -320,7 +320,7 @@ restart:
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
MMUAccessType access_type)
{
- CPUState *cs = CPU(riscv_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int page_fault_exceptions =
(env->priv_ver >= PRIV_VERSION_1_10_0) &&
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e1d91b6c60..97a4e10e3e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
@@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
MSTATUS_MPRV | MSTATUS_SUM)) {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
@@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
/* flush translation cache */
if (val != env->misa) {
- tb_flush(CPU(riscv_env_get_cpu(env)));
+ tb_flush(env_cpu(env));
}
env->misa = val;
@@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- RISCVCPU *cpu = riscv_env_get_cpu(env);
+ RISCVCPU *cpu = env_archcpu(env);
/* Allow software control of delegable interrupts not claimed by hardware */
target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
uint32_t old_mip;
@@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
env->sptbr = val & (((target_ulong)
1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
}
@@ -723,7 +723,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
env->satp = val;
}
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b7dc18a41e..f078bafbe6 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -28,7 +28,7 @@
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
- CPUState *cs = CPU(riscv_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
cs->exception_index = exception;
cpu_loop_exit_restore(cs, pc);
@@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
void helper_wfi(CPURISCVState *env)
{
- CPUState *cs = CPU(riscv_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
@@ -143,8 +143,8 @@ void helper_wfi(CPURISCVState *env)
void helper_tlb_flush(CPURISCVState *env)
{
- RISCVCPU *cpu = riscv_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 24/39] target/s390x: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (22 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 23/39] target/riscv: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 18:31 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 25/39] target/sh4: " Richard Henderson
` (14 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/cpu.h | 5 ----
linux-user/s390x/cpu_loop.c | 2 +-
target/s390x/cc_helper.c | 5 ++--
target/s390x/diag.c | 2 +-
target/s390x/excp_helper.c | 6 ++---
target/s390x/fpu_helper.c | 4 +--
target/s390x/helper.c | 7 +++---
target/s390x/int_helper.c | 3 +--
target/s390x/interrupt.c | 6 ++---
target/s390x/mem_helper.c | 28 ++++++++-------------
target/s390x/misc_helper.c | 50 ++++++++++++++++++-------------------
target/s390x/mmu_helper.c | 8 +++---
target/s390x/sigp.c | 4 +--
13 files changed, 56 insertions(+), 74 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 9cdd831a77..eefed6f509 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -163,11 +163,6 @@ struct S390CPU {
uint32_t irqstate_saved_size;
};
-static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
-{
- return container_of(env, S390CPU, env);
-}
-
#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c
index b8bd1c956c..8211022ceb 100644
--- a/linux-user/s390x/cpu_loop.c
+++ b/linux-user/s390x/cpu_loop.c
@@ -26,7 +26,7 @@
void cpu_loop(CPUS390XState *env)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, n, sig;
target_siginfo_t info;
target_ulong addr;
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index 0e467bf2b6..e9732500ad 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -405,7 +405,6 @@ static uint32_t cc_calc_lcbb(uint64_t dst)
static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
uint64_t src, uint64_t dst, uint64_t vr)
{
- S390CPU *cpu = s390_env_get_cpu(env);
uint32_t r = 0;
switch (cc_op) {
@@ -526,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
break;
default:
- cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op));
+ cpu_abort(env_cpu(env), "Unknown CC operation: %s\n", cc_name(cc_op));
}
HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
@@ -550,7 +549,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src,
void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
load_psw(env, mask, addr);
- cpu_loop_exit(CPU(s390_env_get_cpu(env)));
+ cpu_loop_exit(env_cpu(env));
}
void HELPER(sacf)(CPUS390XState *env, uint64_t a1)
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
index aafa740f61..65eabf0461 100644
--- a/target/s390x/diag.c
+++ b/target/s390x/diag.c
@@ -55,7 +55,7 @@ int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3)
void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint64_t addr = env->regs[r1];
uint64_t subcode = env->regs[r3];
IplParameterBlock *iplb;
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index f84bfb1284..b83c1e6559 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -36,7 +36,7 @@
void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code,
int ilen, uintptr_t ra)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cpu_restore_state(cs, ra, true);
qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
@@ -51,7 +51,7 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
g_assert(dxc <= 0xff);
#if !defined(CONFIG_USER_ONLY)
/* Store the DXC into the lowcore */
- stl_phys(CPU(s390_env_get_cpu(env))->as,
+ stl_phys(env_cpu(env)->as,
env->psa + offsetof(LowCore, data_exc_code), dxc);
#endif
@@ -261,7 +261,7 @@ static void do_svc_interrupt(CPUS390XState *env)
static void do_ext_interrupt(CPUS390XState *env)
{
QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
uint64_t mask, addr;
uint16_t cpu_addr;
LowCore *lowcore;
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
index 1be68bafea..906fa8ce99 100644
--- a/target/s390x/fpu_helper.c
+++ b/target/s390x/fpu_helper.c
@@ -114,8 +114,6 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
{
- S390CPU *cpu = s390_env_get_cpu(env);
-
switch (float_compare) {
case float_relation_equal:
return 0;
@@ -126,7 +124,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
case float_relation_unordered:
return 3;
default:
- cpu_abort(CPU(cpu), "unknown return value for float compare\n");
+ cpu_abort(env_cpu(env), "unknown return value for float compare\n");
}
}
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index f957a2c830..52399bf7f4 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -111,11 +111,11 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
env->cc_op = (mask >> 44) & 3;
if ((old_mask ^ mask) & PSW_MASK_PER) {
- s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env)));
+ s390_cpu_recompute_watchpoints(env_cpu(env));
}
if (mask & PSW_MASK_WAIT) {
- s390_handle_wait(s390_env_get_cpu(env));
+ s390_handle_wait(env_archcpu(env));
}
}
@@ -137,14 +137,13 @@ uint64_t get_psw_mask(CPUS390XState *env)
LowCore *cpu_map_lowcore(CPUS390XState *env)
{
- S390CPU *cpu = s390_env_get_cpu(env);
LowCore *lowcore;
hwaddr len = sizeof(LowCore);
lowcore = cpu_physical_memory_map(env->psa, &len, 1);
if (len < sizeof(LowCore)) {
- cpu_abort(CPU(cpu), "Could not map lowcore\n");
+ cpu_abort(env_cpu(env), "Could not map lowcore\n");
}
return lowcore;
diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c
index abbbc20d9c..d13cc49be6 100644
--- a/target/s390x/int_helper.c
+++ b/target/s390x/int_helper.c
@@ -109,10 +109,9 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al,
s390_program_interrupt(env, PGM_FIXPT_DIVIDE, ILEN_AUTO, GETPC());
}
#else
- S390CPU *cpu = s390_env_get_cpu(env);
/* 32-bit hosts would need special wrapper functionality - just abort if
we encounter such a case; it's very unlikely anyways. */
- cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n");
+ cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n");
#endif
}
return ret;
diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c
index a17eff5ebc..a8f9b38795 100644
--- a/target/s390x/interrupt.c
+++ b/target/s390x/interrupt.c
@@ -23,7 +23,7 @@
/* Ensure to exit the TB after this call! */
void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_PGM;
env->int_pgm_code = code;
@@ -33,10 +33,8 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen)
void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
uintptr_t ra)
{
- S390CPU *cpu = s390_env_get_cpu(env);
-
if (kvm_enabled()) {
- kvm_s390_program_interrupt(cpu, code);
+ kvm_s390_program_interrupt(env_archcpu(env), code);
} else if (tcg_enabled()) {
tcg_s390_program_interrupt(env, code, ilen, ra);
} else {
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index e2992deb2f..f02eb85d30 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1633,7 +1633,6 @@ uint32_t HELPER(csst_parallel)(CPUS390XState *env, uint32_t r3, uint64_t a1,
void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
uintptr_t ra = GETPC();
- S390CPU *cpu = s390_env_get_cpu(env);
bool PERchanged = false;
uint64_t src = a2;
uint32_t i;
@@ -1658,16 +1657,15 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
if (PERchanged && env->psw.mask & PSW_MASK_PER) {
- s390_cpu_recompute_watchpoints(CPU(cpu));
+ s390_cpu_recompute_watchpoints(env_cpu(env));
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
uintptr_t ra = GETPC();
- S390CPU *cpu = s390_env_get_cpu(env);
bool PERchanged = false;
uint64_t src = a2;
uint32_t i;
@@ -1691,10 +1689,10 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
if (PERchanged && env->psw.mask & PSW_MASK_PER) {
- s390_cpu_recompute_watchpoints(CPU(cpu));
+ s390_cpu_recompute_watchpoints(env_cpu(env));
}
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@@ -1753,8 +1751,8 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr)
uint32_t HELPER(tprot)(CPUS390XState *env, uint64_t a1, uint64_t a2)
{
- S390CPU *cpu = s390_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ S390CPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
/*
* TODO: we currently don't handle all access protection types
@@ -1922,7 +1920,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
const uintptr_t ra = GETPC();
uint64_t table, entry, raddr;
uint16_t entries, i, index = 0;
@@ -1974,7 +1972,7 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
uint32_t m4)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
const uintptr_t ra = GETPC();
uint64_t page = vaddr & TARGET_PAGE_MASK;
uint64_t pte_addr, pte;
@@ -2014,17 +2012,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
/* flush local tlb */
void HELPER(ptlb)(CPUS390XState *env)
{
- S390CPU *cpu = s390_env_get_cpu(env);
-
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
/* flush global tlb */
void HELPER(purge)(CPUS390XState *env)
{
- S390CPU *cpu = s390_env_get_cpu(env);
-
- tlb_flush_all_cpus_synced(CPU(cpu));
+ tlb_flush_all_cpus_synced(env_cpu(env));
}
/* load using real address */
@@ -2068,7 +2062,7 @@ void HELPER(sturg)(CPUS390XState *env, uint64_t addr, uint64_t v1)
/* load real address */
uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t cc = 0;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
uint64_t ret;
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
index ee67c1fa0c..c806c3ec00 100644
--- a/target/s390x/misc_helper.c
+++ b/target/s390x/misc_helper.c
@@ -55,7 +55,7 @@
/* Raise an exception statically from a TB. */
void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
HELPER_LOG("%s: exception %d\n", __func__, excp);
cs->exception_index = excp;
@@ -150,7 +150,7 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num)
/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t prefix = a1 & 0x7fffe000;
env->psa = prefix;
@@ -256,7 +256,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1)
const uint32_t sel2 = r1 & STSI_R1_SEL2_MASK;
const MachineState *ms = MACHINE(qdev_get_machine());
uint16_t total_cpus = 0, conf_cpus = 0, reserved_cpus = 0;
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
SysIB sysib = { };
int i, cc = 0;
@@ -411,7 +411,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
#ifndef CONFIG_USER_ONLY
void HELPER(xsch)(CPUS390XState *env, uint64_t r1)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_xsch(cpu, r1, GETPC());
qemu_mutex_unlock_iothread();
@@ -419,7 +419,7 @@ void HELPER(xsch)(CPUS390XState *env, uint64_t r1)
void HELPER(csch)(CPUS390XState *env, uint64_t r1)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_csch(cpu, r1, GETPC());
qemu_mutex_unlock_iothread();
@@ -427,7 +427,7 @@ void HELPER(csch)(CPUS390XState *env, uint64_t r1)
void HELPER(hsch)(CPUS390XState *env, uint64_t r1)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_hsch(cpu, r1, GETPC());
qemu_mutex_unlock_iothread();
@@ -435,7 +435,7 @@ void HELPER(hsch)(CPUS390XState *env, uint64_t r1)
void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_msch(cpu, r1, inst >> 16, GETPC());
qemu_mutex_unlock_iothread();
@@ -443,7 +443,7 @@ void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
void HELPER(rchp)(CPUS390XState *env, uint64_t r1)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_rchp(cpu, r1, GETPC());
qemu_mutex_unlock_iothread();
@@ -451,7 +451,7 @@ void HELPER(rchp)(CPUS390XState *env, uint64_t r1)
void HELPER(rsch)(CPUS390XState *env, uint64_t r1)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_rsch(cpu, r1, GETPC());
qemu_mutex_unlock_iothread();
@@ -459,7 +459,7 @@ void HELPER(rsch)(CPUS390XState *env, uint64_t r1)
void HELPER(sal)(CPUS390XState *env, uint64_t r1)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_sal(cpu, r1, GETPC());
@@ -468,7 +468,7 @@ void HELPER(sal)(CPUS390XState *env, uint64_t r1)
void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_schm(cpu, r1, r2, inst >> 16, GETPC());
@@ -477,7 +477,7 @@ void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst)
void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_ssch(cpu, r1, inst >> 16, GETPC());
qemu_mutex_unlock_iothread();
@@ -485,7 +485,7 @@ void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
void HELPER(stcrw)(CPUS390XState *env, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_stcrw(cpu, inst >> 16, GETPC());
@@ -494,7 +494,7 @@ void HELPER(stcrw)(CPUS390XState *env, uint64_t inst)
void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_stsch(cpu, r1, inst >> 16, GETPC());
qemu_mutex_unlock_iothread();
@@ -503,7 +503,7 @@ void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr)
{
const uintptr_t ra = GETPC();
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
QEMUS390FlicIO *io = NULL;
LowCore *lowcore;
@@ -555,7 +555,7 @@ uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr)
void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_tsch(cpu, r1, inst >> 16, GETPC());
qemu_mutex_unlock_iothread();
@@ -563,7 +563,7 @@ void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
void HELPER(chsc)(CPUS390XState *env, uint64_t inst)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
ioinst_handle_chsc(cpu, inst >> 16, GETPC());
qemu_mutex_unlock_iothread();
@@ -618,7 +618,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr)
/* If the instruction has to be nullified, trigger the
exception immediately. */
if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) {
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
env->per_perc_atmid |= PER_CODE_EVENT_NULLIFICATION;
env->int_pgm_code = PGM_PER;
@@ -695,7 +695,7 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr)
*/
void HELPER(clp)(CPUS390XState *env, uint32_t r2)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
clp_service_call(cpu, r2, GETPC());
@@ -704,7 +704,7 @@ void HELPER(clp)(CPUS390XState *env, uint32_t r2)
void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
pcilg_service_call(cpu, r1, r2, GETPC());
@@ -713,7 +713,7 @@ void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
pcistg_service_call(cpu, r1, r2, GETPC());
@@ -723,7 +723,7 @@ void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba,
uint32_t ar)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
stpcifc_service_call(cpu, r1, fiba, ar, GETPC());
@@ -745,7 +745,7 @@ void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint64_t r3)
void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
rpcit_service_call(cpu, r1, r2, GETPC());
@@ -755,7 +755,7 @@ void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2)
void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3,
uint64_t gaddr, uint32_t ar)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
pcistb_service_call(cpu, r1, r3, gaddr, ar, GETPC());
@@ -765,7 +765,7 @@ void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3,
void HELPER(mpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba,
uint32_t ar)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
qemu_mutex_lock_iothread();
mpcifc_service_call(cpu, r1, fiba, ar, GETPC());
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index 145b62a7ef..9669bae393 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -58,12 +58,12 @@
static void trigger_access_exception(CPUS390XState *env, uint32_t type,
uint32_t ilen, uint64_t tec)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
if (kvm_enabled()) {
kvm_s390_access_exception(cpu, type, tec);
} else {
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
if (type != PGM_ADDRESSING) {
stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
}
@@ -185,7 +185,7 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
target_ulong *raddr, int *flags, int rw,
bool exc)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint64_t origin, offs, pt_entry;
if (st_entry & SEGMENT_ENTRY_RO) {
@@ -214,7 +214,7 @@ static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
target_ulong *raddr, int *flags, int rw,
bool exc)
{
- CPUState *cs = CPU(s390_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint64_t origin, offs, new_entry;
const int pchks[4] = {
PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index c1f9245797..ea5f69d5d8 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -454,7 +454,7 @@ int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3)
{
uint64_t *status_reg = &env->regs[r1];
uint64_t param = (r1 % 2) ? env->regs[r1] : env->regs[r1 + 1];
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
S390CPU *dst_cpu = NULL;
int ret;
@@ -492,7 +492,7 @@ int s390_cpu_restart(S390CPU *cpu)
void do_stop_interrupt(CPUS390XState *env)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = env_archcpu(env);
if (s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu) == 0) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 25/39] target/sh4: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (23 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 24/39] target/s390x: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:14 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 26/39] target/sparc: " Richard Henderson
` (13 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/cpu.h | 5 -----
linux-user/sh4/cpu_loop.c | 2 +-
target/sh4/helper.c | 26 ++++++++++++--------------
target/sh4/op_helper.c | 9 +++------
4 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index c1a9e4f981..2ed942ca47 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -207,11 +207,6 @@ struct SuperHCPU {
CPUSH4State env;
};
-static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
-{
- return container_of(env, SuperHCPU, env);
-}
-
#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
index 59cbbeda7e..add8817d86 100644
--- a/linux-user/sh4/cpu_loop.c
+++ b/linux-user/sh4/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUSH4State *env)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 2ff0cf4060..5240da715e 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -238,8 +238,6 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
static int itlb_replacement(CPUSH4State * env)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
-
if ((env->mmucr & 0xe0000000) == 0xe0000000) {
return 0;
}
@@ -252,7 +250,7 @@ static int itlb_replacement(CPUSH4State * env)
if ((env->mmucr & 0x2c000000) == 0x00000000) {
return 3;
}
- cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
+ cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
@@ -308,7 +306,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
itlb = itlb_replacement(env);
ientry = &env->itlb[itlb];
if (ientry->v) {
- tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
+ tlb_flush_page(env_cpu(env), ientry->vpn << 10);
}
*ientry = env->utlb[utlb];
update_itlb_use(env, itlb);
@@ -533,14 +531,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void cpu_load_tlb(CPUSH4State * env)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
+ CPUState *cs = env_cpu(env);
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(cpu), address);
+ tlb_flush_page(cs, address);
}
/* Take values into cpu status from registers. */
@@ -563,7 +561,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->size = 1024 * 1024; /* 1M */
break;
default:
- cpu_abort(CPU(cpu), "Unhandled load_tlb");
+ cpu_abort(cs, "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
@@ -590,7 +588,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->v = 0;
}
- tlb_flush(CPU(sh_env_get_cpu(s)));
+ tlb_flush(env_cpu(s));
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
@@ -616,7 +614,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->asid = asid;
entry->vpn = vpn;
@@ -658,7 +656,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
@@ -711,7 +709,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) {
- CPUState *cs = CPU(sh_env_get_cpu(s));
+ CPUState *cs = env_cpu(s);
/* Multiple TLB Exception */
cs->exception_index = 0x140;
@@ -743,14 +741,14 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
}
if (needs_tlb_flush) {
- tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
+ tlb_flush_page(env_cpu(s), vpn << 10);
}
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
if (entry->v) {
- CPUState *cs = CPU(sh_env_get_cpu(s));
+ CPUState *cs = env_cpu(s);
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
@@ -805,7 +803,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 12fba6fc78..11cb68cc1c 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -58,10 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
- SuperHCPU *cpu = sh_env_get_cpu(env);
-
- /* XXXXX */
- cpu_abort(CPU(cpu), "Unhandled ldtlb");
+ cpu_abort(env_cpu(env), "Unhandled ldtlb");
#else
cpu_load_tlb(env);
#endif
@@ -70,7 +67,7 @@ void helper_ldtlb(CPUSH4State *env)
static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
uintptr_t retaddr)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit_restore(cs, retaddr);
@@ -103,7 +100,7 @@ void helper_debug(CPUSH4State *env)
void helper_sleep(CPUSH4State *env)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->halted = 1;
env->in_sleep = 1;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 26/39] target/sparc: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (24 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 25/39] target/sh4: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:15 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 27/39] target/tilegx: Use env_cpu Richard Henderson
` (12 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/cpu.h | 5 -----
bsd-user/main.c | 2 +-
hw/sparc/leon3.c | 4 ++--
hw/sparc/sun4m.c | 4 ++--
hw/sparc64/sparc64.c | 2 +-
linux-user/sparc/cpu_loop.c | 2 +-
target/sparc/fop_helper.c | 2 +-
target/sparc/helper.c | 8 ++++----
target/sparc/ldst_helper.c | 33 +++++++++++++++------------------
target/sparc/mmu_helper.c | 10 +++++-----
10 files changed, 32 insertions(+), 40 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5a10680d8f..1442232cef 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -532,11 +532,6 @@ struct SPARCCPU {
CPUSPARCState env;
};
-static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
-{
- return container_of(env, SPARCCPU, env);
-}
-
#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY
diff --git a/bsd-user/main.c b/bsd-user/main.c
index bfdcae4269..f6f76f1a64 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -486,7 +486,7 @@ static void flush_windows(CPUSPARCState *env)
void cpu_loop(CPUSPARCState *env)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret, syscall_nr;
//target_siginfo_t info;
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 774639af33..ef74bc81c2 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -91,7 +91,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
- cs = CPU(sparc_env_get_cpu(env));
+ cs = env_cpu(env);
trace_leon3_set_irq(i);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -99,7 +99,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
- cs = CPU(sparc_env_get_cpu(env));
+ cs = env_cpu(env);
trace_leon3_reset_irq(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index ca1e3825d5..a87bef6d4f 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -147,7 +147,7 @@ void cpu_check_irqs(CPUSPARCState *env)
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
- cs = CPU(sparc_env_get_cpu(env));
+ cs = env_cpu(env);
trace_sun4m_cpu_interrupt(i);
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
@@ -155,7 +155,7 @@ void cpu_check_irqs(CPUSPARCState *env)
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
- cs = CPU(sparc_env_get_cpu(env));
+ cs = env_cpu(env);
trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
env->interrupt_index = 0;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index 408388945e..689801f37d 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -46,7 +46,7 @@ void cpu_check_irqs(CPUSPARCState *env)
if (env->ivec_status & 0x20) {
return;
}
- cs = CPU(sparc_env_get_cpu(env));
+ cs = env_cpu(env);
/* check if TM or SM in SOFTINT are set
setting these also causes interrupt 14 */
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
index 9e357229c0..d85359037c 100644
--- a/linux-user/sparc/cpu_loop.c
+++ b/linux-user/sparc/cpu_loop.c
@@ -145,7 +145,7 @@ static void flush_windows(CPUSPARCState *env)
void cpu_loop (CPUSPARCState *env)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
abi_long ret;
target_siginfo_t info;
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
index b6642fd1d7..9eb9b75718 100644
--- a/target/sparc/fop_helper.c
+++ b/target/sparc/fop_helper.c
@@ -53,7 +53,7 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
}
if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* Unmasked exception, generate a trap. Note that while
the helper is marked as NO_WG, we can get away with
diff --git a/target/sparc/helper.c b/target/sparc/helper.c
index 46232788c8..1a52061fbf 100644
--- a/target/sparc/helper.c
+++ b/target/sparc/helper.c
@@ -26,7 +26,7 @@
void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = tt;
cpu_loop_exit_restore(cs, ra);
@@ -34,7 +34,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra)
void helper_raise_exception(CPUSPARCState *env, int tt)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = tt;
cpu_loop_exit(cs);
@@ -42,7 +42,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt)
void helper_debug(CPUSPARCState *env)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = EXCP_DEBUG;
cpu_loop_exit(cs);
@@ -243,7 +243,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
#ifndef TARGET_SPARC64
void helper_power_down(CPUSPARCState *env)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->halted = 1;
cs->exception_index = EXCP_HLT;
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index a7fcb84ac0..a2d033a61f 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -122,13 +122,13 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
static void replace_tlb_entry(SparcTLBEntry *tlb,
uint64_t tlb_tag, uint64_t tlb_tte,
- CPUSPARCState *env1)
+ CPUSPARCState *env)
{
target_ulong mask, size, va, offset;
/* flush page range if translation is valid */
if (TTE_IS_VALID(tlb->tte)) {
- CPUState *cs = CPU(sparc_env_get_cpu(env1));
+ CPUState *cs = env_cpu(env);
size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte);
mask = 1ULL + ~size;
@@ -499,7 +499,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
{
int size = 1 << (memop & MO_SIZE);
int sign = memop & MO_SIGN;
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint64_t ret = 0;
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_addr = addr;
@@ -725,8 +725,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
int asi, uint32_t memop)
{
int size = 1 << (memop & MO_SIZE);
- SPARCCPU *cpu = sparc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
do_check_align(env, addr, size - 1, GETPC());
switch (asi) {
@@ -874,13 +873,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
DPRINTF_MMU("mmu flush level %d\n", mmulev);
switch (mmulev) {
case 0: /* flush page */
- tlb_flush_page(CPU(cpu), addr & 0xfffff000);
+ tlb_flush_page(cs, addr & 0xfffff000);
break;
case 1: /* flush segment (256k) */
case 2: /* flush region (16M) */
case 3: /* flush context (4G) */
case 4: /* flush entire */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
default:
break;
@@ -905,7 +904,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
are invalid in normal mode. */
if ((oldreg ^ env->mmuregs[reg])
& (MMU_NF | env->def.mmu_bm)) {
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
}
break;
case 1: /* Context Table Pointer Register */
@@ -916,7 +915,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
}
break;
case 3: /* Synchronous Fault Status Register with Clear */
@@ -1027,8 +1026,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case ASI_USERTXT: /* User code access, XXX */
case ASI_KERNELTXT: /* Supervisor code access, XXX */
default:
- cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
- addr, true, false, asi, size);
+ cpu_unassigned_access(cs, addr, true, false, asi, size);
break;
case ASI_USERDATA: /* User data access */
@@ -1175,7 +1173,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
{
int size = 1 << (memop & MO_SIZE);
int sign = memop & MO_SIGN;
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint64_t ret = 0;
#if defined(DEBUG_ASI)
target_ulong last_addr = addr;
@@ -1481,8 +1479,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, uint32_t memop)
{
int size = 1 << (memop & MO_SIZE);
- SPARCCPU *cpu = sparc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
@@ -1686,13 +1683,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
env->dmmu.mmu_primary_context = val;
/* can be optimized to only flush MMU_USER_IDX
and MMU_KERNEL_IDX entries */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
case 2: /* Secondary context */
env->dmmu.mmu_secondary_context = val;
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
and MMU_KERNEL_SECONDARY_IDX entries */
- tlb_flush(CPU(cpu));
+ tlb_flush(cs);
break;
case 5: /* TSB access */
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@@ -1768,13 +1765,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
case 1:
env->dmmu.mmu_primary_context = val;
env->immu.mmu_primary_context = val;
- tlb_flush_by_mmuidx(CPU(cpu),
+ tlb_flush_by_mmuidx(cs,
(1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
break;
case 2:
env->dmmu.mmu_secondary_context = val;
env->immu.mmu_secondary_context = val;
- tlb_flush_by_mmuidx(CPU(cpu),
+ tlb_flush_by_mmuidx(cs,
(1 << MMU_USER_SECONDARY_IDX) |
(1 << MMU_KERNEL_SECONDARY_IDX));
break;
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index afcc5b617d..2cfcb6a976 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -96,7 +96,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
uint32_t pde;
int error_code = 0, is_dirty, is_user;
unsigned long page_offset;
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
is_user = mmu_idx == MMU_USER_IDX;
@@ -256,7 +256,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
hwaddr pde_ptr;
uint32_t pde;
@@ -323,7 +323,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
void dump_mmu(CPUSPARCState *env)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_ulong va, va1, va2;
unsigned int n, m, o;
hwaddr pde_ptr, pa;
@@ -482,7 +482,7 @@ static int get_physical_address_data(CPUSPARCState *env,
hwaddr *physical, int *prot,
target_ulong address, int rw, int mmu_idx)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
unsigned int i;
uint64_t context;
uint64_t sfsr = 0;
@@ -600,7 +600,7 @@ static int get_physical_address_code(CPUSPARCState *env,
hwaddr *physical, int *prot,
target_ulong address, int mmu_idx)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
unsigned int i;
uint64_t context;
bool is_user = false;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 27/39] target/tilegx: Use env_cpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (25 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 26/39] target/sparc: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:16 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 28/39] target/tricore: " Richard Henderson
` (11 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tilegx/cpu.h | 5 -----
linux-user/tilegx/cpu_loop.c | 2 +-
target/tilegx/helper.c | 2 +-
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 135df63523..7f8fe7c513 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -138,11 +138,6 @@ typedef struct TileGXCPU {
CPUTLGState env;
} TileGXCPU;
-static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
-{
- return container_of(env, TileGXCPU, env);
-}
-
#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c
index 4f39eb9ad3..d4abe29dcd 100644
--- a/linux-user/tilegx/cpu_loop.c
+++ b/linux-user/tilegx/cpu_loop.c
@@ -206,7 +206,7 @@ static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
void cpu_loop(CPUTLGState *env)
{
- CPUState *cs = CPU(tilegx_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr;
while (1) {
diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c
index 4964bb9111..a57a679825 100644
--- a/target/tilegx/helper.c
+++ b/target/tilegx/helper.c
@@ -28,7 +28,7 @@
void helper_exception(CPUTLGState *env, uint32_t excp)
{
- CPUState *cs = CPU(tilegx_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
cpu_loop_exit(cs);
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 28/39] target/tricore: Use env_cpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (26 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 27/39] target/tilegx: Use env_cpu Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:16 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu Richard Henderson
` (10 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/cpu.h | 5 -----
target/tricore/op_helper.c | 4 ++--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 4c997b6d30..fc3328fdf5 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -208,11 +208,6 @@ struct TriCoreCPU {
CPUTriCoreState env;
};
-static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env)
-{
- return TRICORE_CPU(container_of(env, TriCoreCPU, env));
-}
-
#define ENV_OFFSET offsetof(TriCoreCPU, env)
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index ed9dc0c83e..ba2f21a6c3 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -29,7 +29,7 @@ static void QEMU_NORETURN
raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
uintptr_t pc, uint32_t fcd_pc)
{
- CPUState *cs = CPU(tricore_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
/* in case we come from a helper-call we need to restore the PC */
cpu_restore_state(cs, pc, true);
@@ -2800,7 +2800,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
int error_code,
uintptr_t pc)
{
- CPUState *cs = CPU(tricore_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = exception;
env->error_code = error_code;
/* now we have a real cpu fault */
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (27 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 28/39] target/tricore: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:17 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 30/39] target/xtensa: " Richard Henderson
` (9 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/unicore32/cpu.h | 5 -----
hw/unicore32/puv3.c | 2 +-
target/unicore32/helper.c | 8 ++------
target/unicore32/op_helper.c | 2 +-
target/unicore32/softmmu.c | 11 ++++-------
target/unicore32/translate.c | 26 ++------------------------
target/unicore32/ucf64_helper.c | 2 +-
7 files changed, 11 insertions(+), 45 deletions(-)
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 22e22345dc..2dd1b34765 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -76,11 +76,6 @@ struct UniCore32CPU {
CPUUniCore32State env;
};
-static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
-{
- return container_of(env, UniCore32CPU, env);
-}
-
#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
index b42e600f74..132e6086ee 100644
--- a/hw/unicore32/puv3.c
+++ b/hw/unicore32/puv3.c
@@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize interrupt controller */
cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler,
- uc32_env_get_cpu(env), 0);
+ env_archcpu(env), 0);
dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc);
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c
index a5ff2ddb74..19ba865482 100644
--- a/target/unicore32/helper.c
+++ b/target/unicore32/helper.c
@@ -31,8 +31,6 @@
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
uint32_t cop)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
/*
* movc pp.nn, rn, #imm9
* rn: UCOP_REG_D
@@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
case 6:
if ((cop <= 6) && (cop >= 2)) {
/* invalid all tlb */
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
return;
}
break;
@@ -218,10 +216,8 @@ void helper_cp1_putc(target_ulong x)
#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (mode != ASR_MODE_USER) {
- cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
+ cpu_abort(env_cpu(env), "Tried to switch out of user mode\n");
}
}
diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c
index e0a15882d3..44ff84420e 100644
--- a/target/unicore32/op_helper.c
+++ b/target/unicore32/op_helper.c
@@ -19,7 +19,7 @@
void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
{
- CPUState *cs = CPU(uc32_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
cpu_loop_exit(cs);
diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c
index 00c7e0d028..2f31592faf 100644
--- a/target/unicore32/softmmu.c
+++ b/target/unicore32/softmmu.c
@@ -36,8 +36,6 @@
/* Map CPU modes onto saved register banks. */
static inline int bank_number(CPUUniCore32State *env, int mode)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
switch (mode) {
case ASR_MODE_USER:
case ASR_MODE_SUSR:
@@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode)
case ASR_MODE_INTR:
return 4;
}
- cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
+ cpu_abort(env_cpu(env), "Bad mode %x\n", mode);
return -1;
}
@@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
int access_type, int is_user, uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
int code;
uint32_t table;
uint32_t desc;
@@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
*page_size = TARGET_PAGE_SIZE;
break;
default:
- cpu_abort(CPU(cpu), "wrong page type!");
+ cpu_abort(cs, "wrong page type!");
}
break;
default:
- cpu_abort(CPU(cpu), "wrong page type!");
+ cpu_abort(cs, "wrong page type!");
}
*phys_ptr = phys_addr;
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 89b02d1c3c..d27451eed3 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -180,7 +180,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
#define UCOP_SET_L UCOP_SET(24)
#define UCOP_SET_S UCOP_SET(24)
-#define ILLEGAL cpu_abort(CPU(cpu), \
+#define ILLEGAL cpu_abort(env_cpu(env), \
"Illegal UniCore32 instruction %x at line %d!", \
insn, __LINE__)
@@ -188,7 +188,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp, tmp2, tmp3;
if ((insn & 0xfe000000) == 0xe0000000) {
tmp2 = new_tmp();
@@ -214,7 +213,6 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
if ((insn & 0xff003fff) == 0xe1000400) {
@@ -682,7 +680,6 @@ static inline long ucf64_reg_offset(int reg)
/* UniCore-F64 single load/store I_offset */
static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
int offset;
TCGv tmp;
TCGv addr;
@@ -729,7 +726,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in
/* UniCore-F64 load/store multiple words */
static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int i;
int j, n, freg;
TCGv tmp;
@@ -815,7 +811,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in
/* UniCore-F64 mrc/mcr */
static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
if ((insn & 0xfe0003ff) == 0xe2000000) {
@@ -880,8 +875,6 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins
/* UniCore-F64 convert instructions */
static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
}
@@ -948,8 +941,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn
/* UniCore-F64 compare instructions */
static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (UCOP_SET(25)) {
ILLEGAL;
}
@@ -1028,8 +1019,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn
/* UniCore-F64 data processing */
static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
}
@@ -1063,8 +1052,6 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins
/* Disassemble an F64 instruction */
static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (!UCOP_SET(29)) {
if (UCOP_SET(26)) {
do_ucf64_ldst_m(env, s, insn);
@@ -1162,8 +1149,6 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
switch (UCOP_CPNUM) {
#ifndef CONFIG_USER_ONLY
case 0:
@@ -1178,14 +1163,13 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
break;
default:
/* Unknown coprocessor. */
- cpu_abort(CPU(cpu), "Unknown coprocessor!");
+ cpu_abort(env_cpu(env), "Unknown coprocessor!");
}
}
/* data processing instructions */
static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
TCGv tmp2;
int logic_cc;
@@ -1419,7 +1403,6 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* miscellaneous instructions */
static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val;
TCGv tmp;
@@ -1545,7 +1528,6 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* SWP instruction */
static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv addr;
TCGv tmp;
TCGv tmp2;
@@ -1573,7 +1555,6 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* load/store hw/sb */
static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv addr;
TCGv tmp;
@@ -1626,7 +1607,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val, i, mmu_idx;
int j, n, reg, user, loaded_base;
TCGv tmp;
@@ -1768,7 +1748,6 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* branch (and link) */
static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val;
int32_t offset;
TCGv tmp;
@@ -1798,7 +1777,6 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int insn;
insn = cpu_ldl_code(env, s->pc);
diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helper.c
index fad3fa6618..e078e84437 100644
--- a/target/unicore32/ucf64_helper.c
+++ b/target/unicore32/ucf64_helper.c
@@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
+ UniCore32CPU *cpu = env_archcpu(env);
int i;
uint32_t changed;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 30/39] target/xtensa: Use env_cpu, env_archcpu
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (28 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:19 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h Richard Henderson
` (8 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
so that the definition of env_cpu is available.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/cpu.h | 17 ++++++-----------
hw/xtensa/pic_cpu.c | 2 +-
linux-user/xtensa/cpu_loop.c | 2 +-
target/xtensa/dbg_helper.c | 4 ++--
target/xtensa/exc_helper.c | 9 ++++-----
target/xtensa/helper.c | 2 +-
target/xtensa/mmu_helper.c | 11 ++++-------
target/xtensa/xtensa-semi.c | 2 +-
8 files changed, 20 insertions(+), 29 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a20541b5d6..86c88eae40 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -529,11 +529,6 @@ struct XtensaCPU {
CPUXtensaState env;
};
-static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
-{
- return container_of(env, XtensaCPU, env);
-}
-
#define ENV_OFFSET offsetof(XtensaCPU, env)
@@ -711,10 +706,15 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
+typedef CPUXtensaState CPUArchState;
+typedef XtensaCPU ArchCPU;
+
+#include "exec/cpu-all.h"
+
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
*pc = env->pc;
*cs_base = 0;
@@ -784,9 +784,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
}
}
-typedef CPUXtensaState CPUArchState;
-typedef XtensaCPU ArchCPU;
-
-#include "exec/cpu-all.h"
-
#endif
diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c
index a8939f5e58..df3acbb541 100644
--- a/hw/xtensa/pic_cpu.c
+++ b/hw/xtensa/pic_cpu.c
@@ -33,7 +33,7 @@
void check_interrupts(CPUXtensaState *env)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
int level;
diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c
index bee78edb8a..64831c9199 100644
--- a/linux-user/xtensa/cpu_loop.c
+++ b/linux-user/xtensa/cpu_loop.c
@@ -123,7 +123,7 @@ static void xtensa_underflow12(CPUXtensaState *env)
void cpu_loop(CPUXtensaState *env)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_siginfo_t info;
abi_ulong ret;
int trapnr;
diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
index cd8fbd653a..be1f81107b 100644
--- a/target/xtensa/dbg_helper.c
+++ b/target/xtensa/dbg_helper.c
@@ -71,7 +71,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
uint32_t dbreakc)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t mask = dbreakc | ~DBREAKC_MASK;
@@ -118,7 +118,7 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
set_dbreak(env, i, env->sregs[DBREAKA + i], v);
} else {
if (env->cpu_watchpoint[i]) {
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
env->cpu_watchpoint[i] = NULL;
diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
index 4a1f7aef5d..601341d13a 100644
--- a/target/xtensa/exc_helper.c
+++ b/target/xtensa/exc_helper.c
@@ -34,7 +34,7 @@
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
if (excp == EXCP_YIELD) {
@@ -100,7 +100,7 @@ void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
{
- CPUState *cpu;
+ CPUState *cpu = env_cpu(env);
env->pc = pc;
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
@@ -111,11 +111,10 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
qemu_mutex_unlock_iothread();
if (env->pending_irq_level) {
- cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
+ cpu_loop_exit(cpu);
return;
}
- cpu = CPU(xtensa_env_get_cpu(env));
cpu->halted = 1;
HELPER(exception)(env, EXCP_HLT);
}
@@ -165,7 +164,7 @@ static void handle_interrupt(CPUXtensaState *env)
(env->config->level_mask[level] &
env->sregs[INTSET] &
env->sregs[INTENABLE])) {
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (level > 1) {
env->sregs[EPC1 + level - 1] = env->pc;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 5f37f378a3..7e5c10e098 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -316,7 +316,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
void xtensa_runstall(CPUXtensaState *env, bool runstall)
{
- CPUState *cpu = CPU(xtensa_env_get_cpu(env));
+ CPUState *cpu = env_cpu(env);
env->runstall = runstall;
cpu->halted = runstall;
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 79a10da231..2603f43807 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -46,12 +46,10 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
-
v = (v & 0xffffff00) | 0x1;
if (v != env->sregs[RASID]) {
env->sregs[RASID] = v;
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
@@ -250,7 +248,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
- tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
+ tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
}
}
@@ -296,8 +294,7 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
@@ -652,7 +649,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t paddr;
uint32_t page_size;
unsigned access;
diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
index 5f5ce4f344..bb29adc921 100644
--- a/target/xtensa/xtensa-semi.c
+++ b/target/xtensa/xtensa-semi.c
@@ -197,7 +197,7 @@ void xtensa_sim_open_console(Chardev *chr)
void HELPER(simcall)(CPUXtensaState *env)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t *regs = env->regs;
switch (regs[2]) {
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (29 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 30/39] target/xtensa: " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 32/39] cpu: Introduce cpu_set_cpustate_pointers Richard Henderson
` (7 subsequent siblings)
38 siblings, 0 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 2 ++
target/alpha/cpu.h | 1 -
target/arm/cpu.h | 2 --
target/cris/cpu.h | 1 -
target/hppa/cpu.h | 1 -
target/i386/cpu.h | 1 -
target/lm32/cpu.h | 1 -
target/m68k/cpu.h | 1 -
target/microblaze/cpu.h | 1 -
target/mips/cpu.h | 1 -
target/moxie/cpu.h | 1 -
target/nios2/cpu.h | 1 -
target/openrisc/cpu.h | 1 -
target/ppc/cpu.h | 1 -
target/riscv/cpu.h | 2 --
target/s390x/cpu.h | 1 -
target/sh4/cpu.h | 1 -
target/sparc/cpu.h | 1 -
target/tilegx/cpu.h | 1 -
target/tricore/cpu.h | 1 -
target/unicore32/cpu.h | 1 -
target/xtensa/cpu.h | 2 --
22 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 24f7991781..9cfa6ccce5 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -5,6 +5,8 @@
/* Helpers for instruction counting code generation. */
+#define ENV_OFFSET offsetof(ArchCPU, env)
+
static TCGOp *icount_start_insn;
static inline void gen_tb_start(TranslationBlock *tb)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 53c085f691..66782cf5d4 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -273,7 +273,6 @@ struct AlphaCPU {
QEMUTimer *alarm_timer;
};
-#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_alpha_cpu;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c54c67fde4..23beb1de9a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -915,8 +915,6 @@ void arm_cpu_post_init(Object *obj);
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
-#define ENV_OFFSET offsetof(ARMCPU, env)
-
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_arm_cpu;
#endif
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 7f244ad545..c19fdcec1e 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -183,7 +183,6 @@ struct CRISCPU {
CPUCRISState env;
};
-#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_cris_cpu;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index a5ddc53bf1..58b2bf2933 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -222,7 +222,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
-#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState;
typedef HPPACPU ArchCPU;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e7f94437b1..a9cfb42b22 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1479,7 +1479,6 @@ struct X86CPU {
int32_t hv_max_vps;
};
-#define ENV_OFFSET offsetof(X86CPU, env)
#ifndef CONFIG_USER_ONLY
extern struct VMStateDescription vmstate_x86_cpu;
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 8e7b70a275..4234a439a3 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -195,7 +195,6 @@ struct LM32CPU {
uint32_t features;
};
-#define ENV_OFFSET offsetof(LM32CPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_lm32_cpu;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index f8d5a0819b..02fbff3625 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -163,7 +163,6 @@ struct M68kCPU {
CPUM68KState env;
};
-#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 7b85beb556..1becb9270b 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -310,7 +310,6 @@ struct MicroBlazeCPU {
CPUMBState env;
};
-#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index e0645eb1d1..52286fcb0e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1051,7 +1051,6 @@ struct MIPSCPU {
CPUMIPSState env;
};
-#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list(void);
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index a481a92833..ebe1c66f52 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -90,7 +90,6 @@ typedef struct MoxieCPU {
CPUMoxieState env;
} MoxieCPU;
-#define ENV_OFFSET offsetof(MoxieCPU, env)
void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index f2ffc1469f..96c8193179 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -193,7 +193,6 @@ typedef struct Nios2CPU {
uint32_t fast_tlb_miss_addr;
} Nios2CPU;
-#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs);
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 91ba667139..150227d450 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -317,7 +317,6 @@ typedef struct OpenRISCCPU {
} OpenRISCCPU;
-#define ENV_OFFSET offsetof(OpenRISCCPU, env)
void cpu_openrisc_list(void);
void openrisc_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ef00a3415d..f970853556 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1203,7 +1203,6 @@ struct PowerPCCPU {
int32_t mig_slb_nr;
};
-#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c32428a4ef..818692dde5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -229,8 +229,6 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
-#define ENV_OFFSET offsetof(RISCVCPU, env)
-
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index eefed6f509..971dc0ccbd 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -163,7 +163,6 @@ struct S390CPU {
uint32_t irqstate_saved_size;
};
-#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_s390_cpu;
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 2ed942ca47..3f2f4043e0 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -207,7 +207,6 @@ struct SuperHCPU {
CPUSH4State env;
};
-#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 1442232cef..b170dd592e 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -532,7 +532,6 @@ struct SPARCCPU {
CPUSPARCState env;
};
-#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_sparc_cpu;
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 7f8fe7c513..643b7dbd17 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -138,7 +138,6 @@ typedef struct TileGXCPU {
CPUTLGState env;
} TileGXCPU;
-#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index fc3328fdf5..581e68e37c 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -208,7 +208,6 @@ struct TriCoreCPU {
CPUTriCoreState env;
};
-#define ENV_OFFSET offsetof(TriCoreCPU, env)
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 2dd1b34765..abb36b5d48 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -76,7 +76,6 @@ struct UniCore32CPU {
CPUUniCore32State env;
};
-#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 86c88eae40..748b6fca25 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -529,8 +529,6 @@ struct XtensaCPU {
CPUXtensaState env;
};
-#define ENV_OFFSET offsetof(XtensaCPU, env)
-
int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
int mmu_idx);
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 32/39] cpu: Introduce cpu_set_cpustate_pointers
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (30 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:32 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 33/39] cpu: Introduce CPUNegativeOffsetState Richard Henderson
` (6 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Consolidate some boilerplate from foo_cpu_initfn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 11 +++++++++++
target/alpha/cpu.c | 3 +--
target/arm/cpu.c | 3 +--
target/cris/cpu.c | 3 +--
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 3 +--
target/lm32/cpu.c | 3 +--
target/m68k/cpu.c | 4 +---
target/microblaze/cpu.c | 3 +--
target/mips/cpu.c | 3 +--
target/moxie/cpu.c | 3 +--
target/nios2/cpu.c | 6 ++----
target/openrisc/cpu.c | 3 +--
target/ppc/translate_init.inc.c | 3 +--
target/riscv/cpu.c | 3 +--
target/s390x/cpu.c | 9 +++++----
target/sh4/cpu.c | 3 +--
target/sparc/cpu.c | 3 +--
target/tilegx/cpu.c | 4 +---
target/tricore/cpu.c | 4 +---
target/unicore32/cpu.c | 3 +--
target/xtensa/cpu.c | 3 +--
22 files changed, 37 insertions(+), 48 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index c62f07b354..71154070a7 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
int cpu_exec(CPUState *cpu);
+/**
+ * cpu_set_cpustate_pointers(cpu)
+ * @cpu: The cpu object
+ *
+ * Set the generic pointers in CPUState into the outer object.
+ */
+static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
+{
+ cpu->parent_obj.env_ptr = &cpu->env;
+}
+
/**
* env_archcpu(env)
* @env: The architecture environment
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index ad3588a44a..b771b9f3fe 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -191,11 +191,10 @@ static void ev67_cpu_initfn(Object *obj)
static void alpha_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
AlphaCPU *cpu = ALPHA_CPU(obj);
CPUAlphaState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->lock_addr = -1;
#if defined(CONFIG_USER_ONLY)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a181fa8dc1..79d5096270 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -698,10 +698,9 @@ static void cpreg_hashtable_data_destroy(gpointer data)
static void arm_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
ARMCPU *cpu = ARM_CPU(obj);
- cs->env_ptr = &cpu->env;
+ cpu_set_cpustate_pointers(cpu);
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
g_free, cpreg_hashtable_data_destroy);
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 75729bfdd5..070f8be363 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -172,12 +172,11 @@ static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
static void cris_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
CRISCPU *cpu = CRIS_CPU(obj);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
CPUCRISState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->pregs[PR_VR] = ccc->vr;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e64f48581e..fdff057793 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -134,7 +134,7 @@ static void hppa_cpu_initfn(Object *obj)
HPPACPU *cpu = HPPA_CPU(obj);
CPUHPPAState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
cs->exception_index = -1;
cpu_hppa_loaded_fr0(env);
cpu_hppa_put_psw(env, PSW_W);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5b84629f91..7eff4c4dea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5588,13 +5588,12 @@ static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
static void x86_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
X86CPU *cpu = X86_CPU(obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
CPUX86State *env = &cpu->env;
FeatureWord w;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
x86_cpuid_version_get_family,
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 282da19994..ebcbd2faa8 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -142,11 +142,10 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
static void lm32_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
LM32CPU *cpu = LM32_CPU(obj);
CPULM32State *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->flags = 0;
}
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 582e3a73b3..930e1be59f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -238,11 +238,9 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
static void m68k_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
M68kCPU *cpu = M68K_CPU(obj);
- CPUM68KState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
}
static const VMStateDescription vmstate_m68k_cpu = {
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 5596cd5485..db4dcdb4ad 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -221,11 +221,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
static void mb_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
CPUMBState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e217fb3e36..3d1b693eef 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -152,12 +152,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
static void mips_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(obj);
CPUMIPSState *env = &cpu->env;
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->cpu_model = mcc->cpu_def;
}
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 46434e65ba..316ee9c534 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -74,10 +74,9 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
static void moxie_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
MoxieCPU *cpu = MOXIE_CPU(obj);
- cs->env_ptr = &cpu->env;
+ cpu_set_cpustate_pointers(cpu);
}
static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index fbfaa2ce26..43677fa802 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -66,14 +66,12 @@ static void nios2_cpu_reset(CPUState *cs)
static void nios2_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
Nios2CPU *cpu = NIOS2_CPU(obj);
- CPUNios2State *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
#if !defined(CONFIG_USER_ONLY)
- mmu_init(env);
+ mmu_init(&cpu->env);
#endif
}
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index d125236977..5177575821 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -92,10 +92,9 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
static void openrisc_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
- cs->env_ptr = &cpu->env;
+ cpu_set_cpustate_pointers(cpu);
}
/* CPU models */
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 6343e25624..739c14fd26 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -10473,12 +10473,11 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
static void ppc_cpu_instance_init(Object *obj)
{
- CPUState *cs = CPU(obj);
PowerPCCPU *cpu = POWERPC_CPU(obj);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
env->msr_mask = pcc->msr_mask;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bcf4eaeb8..35e69a9e12 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -315,10 +315,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
static void riscv_cpu_init(Object *obj)
{
- CPUState *cs = CPU(obj);
RISCVCPU *cpu = RISCV_CPU(obj);
- cs->env_ptr = &cpu->env;
+ cpu_set_cpustate_pointers(cpu);
}
static const VMStateDescription vmstate_riscv_cpu = {
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index b58ef0a8ef..16bcb933ec 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -282,17 +282,18 @@ static void s390_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
S390CPU *cpu = S390_CPU(obj);
- CPUS390XState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
cs->halted = 1;
cs->exception_index = EXCP_HLT;
object_property_add(obj, "crash-information", "GuestPanicInformation",
s390_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
s390_cpu_model_register_props(obj);
#if !defined(CONFIG_USER_ONLY)
- env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
- env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
+ cpu->env.tod_timer =
+ timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
+ cpu->env.cpu_timer =
+ timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
#endif
}
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index da2799082e..62a9123173 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -194,11 +194,10 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
static void superh_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
SuperHCPU *cpu = SUPERH_CPU(obj);
CPUSH4State *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->movcal_backup_tail = &(env->movcal_backup);
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 4654c2a6a0..90109754eb 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -774,12 +774,11 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
static void sparc_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
SPARCCPU *cpu = SPARC_CPU(obj);
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
CPUSPARCState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
if (scc->cpu_def) {
env->def = *scc->cpu_def;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index b9d37105fa..0bfd4187b8 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -99,11 +99,9 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
static void tilegx_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
TileGXCPU *cpu = TILEGX_CPU(obj);
- CPUTLGState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
}
static void tilegx_cpu_do_interrupt(CPUState *cs)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index e8d37e4040..fc3c3075b3 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -104,11 +104,9 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
static void tricore_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
TriCoreCPU *cpu = TRICORE_CPU(obj);
- CPUTriCoreState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
}
static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 2b49d1ca40..700c5c5585 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -103,11 +103,10 @@ static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
static void uc32_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
UniCore32CPU *cpu = UNICORE32_CPU(obj);
CPUUniCore32State *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index a54dbe4260..9461ebad02 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -138,12 +138,11 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
static void xtensa_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
XtensaCPU *cpu = XTENSA_CPU(obj);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
CPUXtensaState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->config = xcc->config;
#ifndef CONFIG_USER_ONLY
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 33/39] cpu: Introduce CPUNegativeOffsetState
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (31 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 32/39] cpu: Introduce cpu_set_cpustate_pointers Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:36 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 34/39] cpu: Move icount_decr to CPUNegativeOffsetState Richard Henderson
` (5 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Nothing in there so far, but all of the plumbing done
within the target ArchCPU state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 24 ++++++++++++++++++++++++
include/exec/cpu-defs.h | 8 ++++++++
target/alpha/cpu.h | 1 +
target/arm/cpu.h | 1 +
target/cris/cpu.h | 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/lm32/cpu.h | 1 +
target/m68k/cpu.h | 1 +
target/microblaze/cpu.h | 5 +++--
target/mips/cpu.h | 1 +
target/moxie/cpu.h | 1 +
target/nios2/cpu.h | 2 ++
target/openrisc/cpu.h | 2 +-
target/ppc/cpu.h | 2 ++
target/riscv/cpu.h | 1 +
target/s390x/cpu.h | 1 +
target/sh4/cpu.h | 1 +
target/sparc/cpu.h | 1 +
target/tilegx/cpu.h | 1 +
target/tricore/cpu.h | 1 +
target/unicore32/cpu.h | 1 +
target/xtensa/cpu.h | 1 +
23 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 71154070a7..5ae83405c8 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -404,4 +404,28 @@ static inline CPUState *env_cpu(CPUArchState *env)
return &env_archcpu(env)->parent_obj;
}
+/**
+ * env_neg(env)
+ * @env: The architecture environment
+ *
+ * Return the CPUNegativeOffsetState associated with the environment.
+ */
+static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
+{
+ ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
+ return &arch_cpu->neg;
+}
+
+/**
+ * cpu_neg(cpu)
+ * @cpu: The generic CPUState
+ *
+ * Return the CPUNegativeOffsetState associated with the cpu.
+ */
+static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
+{
+ ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
+ return &arch_cpu->neg;
+}
+
#endif /* CPU_ALL_H */
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index fbe8945606..ad97991faf 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -227,4 +227,12 @@ typedef struct CPUTLB {
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+/*
+ * This structure must be placed in ArchCPU immedately
+ * before CPUArchState, as a field named "neg".
+ */
+typedef struct CPUNegativeOffsetState {
+ /* Empty */
+} CPUNegativeOffsetState;
+
#endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 66782cf5d4..f4bb67c101 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -267,6 +267,7 @@ struct AlphaCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUAlphaState env;
/* This alarm doesn't exist in real hardware; we wish it did. */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 23beb1de9a..909cb4604d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -719,6 +719,7 @@ struct ARMCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUARMState env;
/* Coprocessor information */
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index c19fdcec1e..eeab483dba 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -180,6 +180,7 @@ struct CRISCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUCRISState env;
};
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 58b2bf2933..0661ff60c1 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -218,6 +218,7 @@ struct HPPACPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUHPPAState env;
QEMUTimer *alarm_timer;
};
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a9cfb42b22..43bb6ab841 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1368,6 +1368,7 @@ struct X86CPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUX86State env;
bool hyperv_vapic;
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 4234a439a3..0ec898eb1d 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -186,6 +186,7 @@ struct LM32CPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPULM32State env;
uint32_t revision;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 02fbff3625..096d1eb588 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -160,6 +160,7 @@ struct M68kCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUM68KState env;
};
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 1becb9270b..732653caed 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -287,6 +287,9 @@ struct MicroBlazeCPU {
/*< public >*/
+ CPUNegativeOffsetState neg;
+ CPUMBState env;
+
/* Microblaze Configuration Settings */
struct {
bool stackprot;
@@ -306,8 +309,6 @@ struct MicroBlazeCPU {
char *version;
uint8_t pvr;
} cfg;
-
- CPUMBState env;
};
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 52286fcb0e..2d9c5f26eb 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1048,6 +1048,7 @@ struct MIPSCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUMIPSState env;
};
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index ebe1c66f52..f5ee8a02f4 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -87,6 +87,7 @@ typedef struct MoxieCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUMoxieState env;
} MoxieCPU;
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 96c8193179..cd06a2ef41 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -181,7 +181,9 @@ typedef struct Nios2CPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUNios2State env;
+
bool mmu_present;
uint32_t pid_num_bits;
uint32_t tlb_num_ways;
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 150227d450..e1acd48652 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -313,8 +313,8 @@ typedef struct OpenRISCCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUOpenRISCState env;
-
} OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f970853556..bb57496212 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1184,7 +1184,9 @@ struct PowerPCCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUPPCState env;
+
int vcpu_id;
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 818692dde5..30a01e8386 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -208,6 +208,7 @@ typedef struct RISCVCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPURISCVState env;
} RISCVCPU;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 971dc0ccbd..ebcf7863e4 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -156,6 +156,7 @@ struct S390CPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUS390XState env;
S390CPUModel *model;
/* needed for live migration */
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 3f2f4043e0..944854dbe0 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -204,6 +204,7 @@ struct SuperHCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUSH4State env;
};
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index b170dd592e..ae9ac07a9d 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -529,6 +529,7 @@ struct SPARCCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUSPARCState env;
};
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 643b7dbd17..deb3e836ea 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -135,6 +135,7 @@ typedef struct TileGXCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUTLGState env;
} TileGXCPU;
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 581e68e37c..43ef29b6bd 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -205,6 +205,7 @@ struct TriCoreCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUTriCoreState env;
};
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index abb36b5d48..140c590ec1 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -73,6 +73,7 @@ struct UniCore32CPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUUniCore32State env;
};
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 748b6fca25..1bbb839bed 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -526,6 +526,7 @@ struct XtensaCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUXtensaState env;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 34/39] cpu: Move icount_decr to CPUNegativeOffsetState
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (32 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 33/39] cpu: Introduce CPUNegativeOffsetState Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-09 20:26 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 35/39] cpu: Move the softmmu tlb " Richard Henderson
` (4 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
Amusingly, we had already ignored the comment to keep this value at the
end of CPUState. This restores the minimum negative offset from TCG_AREG0
for code generation.
For the couple of uses within qom/cpu.c, add a pointer from the CPUState
object to the IcountDecr object within CPUNegativeOffsetState.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 1 +
include/exec/cpu-defs.h | 3 ++-
include/exec/gen-icount.h | 16 ++++++++++------
include/qom/cpu.h | 40 ++++++++++++++++++---------------------
accel/tcg/cpu-exec.c | 23 +++++++++++-----------
accel/tcg/tcg-all.c | 6 ++----
accel/tcg/translate-all.c | 8 ++++----
cpus.c | 9 +++++----
qom/cpu.c | 4 ++--
9 files changed, 56 insertions(+), 54 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 5ae83405c8..253dd1d9a5 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -380,6 +380,7 @@ int cpu_exec(CPUState *cpu);
static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
{
cpu->parent_obj.env_ptr = &cpu->env;
+ cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
}
/**
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index ad97991faf..3971910653 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -33,6 +33,7 @@
#include "exec/hwaddr.h"
#endif
#include "exec/memattrs.h"
+#include "qom/cpu.h"
#include "cpu-param.h"
@@ -232,7 +233,7 @@ typedef struct CPUTLB {
* before CPUArchState, as a field named "neg".
*/
typedef struct CPUNegativeOffsetState {
- /* Empty */
+ IcountDecr icount_decr;
} CPUNegativeOffsetState;
#endif
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 9cfa6ccce5..f7669b6841 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -5,8 +5,6 @@
/* Helpers for instruction counting code generation. */
-#define ENV_OFFSET offsetof(ArchCPU, env)
-
static TCGOp *icount_start_insn;
static inline void gen_tb_start(TranslationBlock *tb)
@@ -21,7 +19,8 @@ static inline void gen_tb_start(TranslationBlock *tb)
}
tcg_gen_ld_i32(count, cpu_env,
- -ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
+ offsetof(ArchCPU, neg.icount_decr.u32) -
+ offsetof(ArchCPU, env));
if (tb_cflags(tb) & CF_USE_ICOUNT) {
imm = tcg_temp_new_i32();
@@ -39,7 +38,8 @@ static inline void gen_tb_start(TranslationBlock *tb)
if (tb_cflags(tb) & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, cpu_env,
- -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
+ offsetof(ArchCPU, neg.icount_decr.u16.low) -
+ offsetof(ArchCPU, env));
}
tcg_temp_free_i32(count);
@@ -60,14 +60,18 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env,
+ offsetof(ArchCPU, parent_obj.can_do_io) -
+ offsetof(ArchCPU, env));
tcg_temp_free_i32(tmp);
}
static inline void gen_io_end(void)
{
TCGv_i32 tmp = tcg_const_i32(0);
- tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env,
+ offsetof(ArchCPU, parent_obj.can_do_io) -
+ offsetof(ArchCPU, env));
tcg_temp_free_i32(tmp);
}
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 08abcbd3fe..0d8fc1caa6 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -226,17 +226,25 @@ typedef struct CPUClass {
bool gdb_stop_before_watchpoint;
} CPUClass;
+/*
+ * Low 16 bits: number of cycles left, used only in icount mode.
+ * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
+ * for this CPU and return to its top level loop (even in non-icount mode).
+ * This allows a single read-compare-cbranch-write sequence to test
+ * for both decrementer underflow and exceptions.
+ */
+typedef union IcountDecr {
+ uint32_t u32;
+ struct {
#ifdef HOST_WORDS_BIGENDIAN
-typedef struct icount_decr_u16 {
- uint16_t high;
- uint16_t low;
-} icount_decr_u16;
+ uint16_t high;
+ uint16_t low;
#else
-typedef struct icount_decr_u16 {
- uint16_t low;
- uint16_t high;
-} icount_decr_u16;
+ uint16_t low;
+ uint16_t high;
#endif
+ } u16;
+} IcountDecr;
typedef struct CPUBreakpoint {
vaddr pc;
@@ -308,11 +316,6 @@ struct qemu_work_item;
* @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
* @singlestep_enabled: Flags for single-stepping.
* @icount_extra: Instructions until next timer event.
- * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode.
- * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this
- * CPU and return to its top level loop (even in non-icount mode).
- * This allows a single read-compare-cbranch-write sequence to test
- * for both decrementer underflow and exceptions.
* @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
* requires that IO only be performed on the last instruction of a TB
* so that interrupts take effect immediately.
@@ -322,6 +325,7 @@ struct qemu_work_item;
* @as: Pointer to the first AddressSpace, for the convenience of targets which
* only have a single AddressSpace
* @env_ptr: Pointer to subclass-specific CPUArchState field.
+ * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
* @gdb_regs: Additional GDB registers.
* @gdb_num_regs: Number of total registers accessible to GDB.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
@@ -380,6 +384,7 @@ struct CPUState {
MemoryRegion *memory;
void *env_ptr; /* CPUArchState */
+ IcountDecr *icount_decr_ptr;
/* Accessed in parallel; all accesses must be atomic */
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
@@ -434,15 +439,6 @@ struct CPUState {
bool ignore_memory_transaction_failures;
- /* Note that this is accessed at the start of every TB via a negative
- offset from AREG0. Leave this field at the end so as to make the
- (absolute value) offset as small as possible. This reduces code
- size, especially for hosts without large memory offsets. */
- union {
- uint32_t u32;
- icount_decr_u16 u16;
- } icount_decr;
-
struct hax_vcpu_state *hax_vcpu;
int hvf_fd;
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 45ef41ebb2..032a62672e 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -54,7 +54,7 @@ typedef struct SyncClocks {
#define MAX_DELAY_PRINT_RATE 2000000000LL
#define MAX_NB_PRINTS 100
-static void align_clocks(SyncClocks *sc, const CPUState *cpu)
+static void align_clocks(SyncClocks *sc, CPUState *cpu)
{
int64_t cpu_icount;
@@ -62,7 +62,7 @@ static void align_clocks(SyncClocks *sc, const CPUState *cpu)
return;
}
- cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
+ cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
sc->last_cpu_icount = cpu_icount;
@@ -105,15 +105,15 @@ static void print_delay(const SyncClocks *sc)
}
}
-static void init_delay_params(SyncClocks *sc,
- const CPUState *cpu)
+static void init_delay_params(SyncClocks *sc, CPUState *cpu)
{
if (!icount_align_option) {
return;
}
sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
- sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
+ sc->last_cpu_icount
+ = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
if (sc->diff_clk < max_delay) {
max_delay = sc->diff_clk;
}
@@ -467,7 +467,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (cpu->exception_index < 0) {
#ifndef CONFIG_USER_ONLY
if (replay_has_exception()
- && cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
+ && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
/* try to cause an exception pending in the log */
cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
}
@@ -525,7 +525,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
* Ensure zeroing happens before reading cpu->exit_request or
* cpu->interrupt_request (see also smp_wmb in cpu_exit())
*/
- atomic_mb_set(&cpu->icount_decr.u16.high, 0);
+ atomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0);
if (unlikely(atomic_read(&cpu->interrupt_request))) {
int interrupt_request;
@@ -596,8 +596,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
}
/* Finally, check if we need to exit to the main loop. */
- if (unlikely(atomic_read(&cpu->exit_request)
- || (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra == 0))) {
+ if (unlikely(atomic_read(&cpu->exit_request))
+ || (use_icount
+ && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) {
atomic_set(&cpu->exit_request, 0);
if (cpu->exception_index == -1) {
cpu->exception_index = EXCP_INTERRUPT;
@@ -624,7 +625,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
}
*last_tb = NULL;
- insns_left = atomic_read(&cpu->icount_decr.u32);
+ insns_left = atomic_read(&cpu_neg(cpu)->icount_decr.u32);
if (insns_left < 0) {
/* Something asked us to stop executing chained TBs; just
* continue round the main loop. Whatever requested the exit
@@ -643,7 +644,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
cpu_update_icount(cpu);
/* Refill decrementer and continue execution. */
insns_left = MIN(0xffff, cpu->icount_budget);
- cpu->icount_decr.u16.low = insns_left;
+ cpu_neg(cpu)->icount_decr.u16.low = insns_left;
cpu->icount_extra = cpu->icount_budget - insns_left;
if (!cpu->icount_extra) {
/* Execute any remaining instructions, then let the main loop
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 3d25bdcc17..9b215dcc5a 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -28,13 +28,12 @@
#include "sysemu/sysemu.h"
#include "qom/object.h"
#include "qemu-common.h"
-#include "qom/cpu.h"
+#include "cpu.h"
#include "sysemu/cpus.h"
#include "qemu/main-loop.h"
unsigned long tcg_tb_size;
-#ifndef CONFIG_USER_ONLY
/* mask must never be zero, except for A20 change call */
static void tcg_handle_interrupt(CPUState *cpu, int mask)
{
@@ -51,7 +50,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
if (!qemu_cpu_is_self(cpu)) {
qemu_cpu_kick(cpu);
} else {
- atomic_set(&cpu->icount_decr.u16.high, -1);
+ atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
if (use_icount &&
!cpu->can_do_io
&& (mask & ~old_mask) != 0) {
@@ -59,7 +58,6 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
}
}
}
-#endif
static int tcg_init(MachineState *ms)
{
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 52d94facf0..e24ee3a172 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -364,7 +364,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
assert(use_icount);
/* Reset the cycle counter to the start of the block
and shift if to the number of actually executed instructions */
- cpu->icount_decr.u16.low += num_insns - i;
+ cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
}
restore_state_to_opc(env, tb, data);
@@ -2200,7 +2200,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& env->active_tc.PC != tb->pc) {
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
- cpu->icount_decr.u16.low++;
+ cpu_neg(cpu)->icount_decr.u16.low++;
env->hflags &= ~MIPS_HFLAG_BMASK;
n = 2;
}
@@ -2208,7 +2208,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
&& env->pc != tb->pc) {
env->pc -= 2;
- cpu->icount_decr.u16.low++;
+ cpu_neg(cpu)->icount_decr.u16.low++;
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
n = 2;
}
@@ -2382,7 +2382,7 @@ void cpu_interrupt(CPUState *cpu, int mask)
{
g_assert(qemu_mutex_iothread_locked());
cpu->interrupt_request |= mask;
- atomic_set(&cpu->icount_decr.u16.high, -1);
+ atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
}
/*
diff --git a/cpus.c b/cpus.c
index e58e7ab0f6..150f5dd047 100644
--- a/cpus.c
+++ b/cpus.c
@@ -238,7 +238,8 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp)
*/
static int64_t cpu_get_icount_executed(CPUState *cpu)
{
- return cpu->icount_budget - (cpu->icount_decr.u16.low + cpu->icount_extra);
+ return (cpu->icount_budget -
+ (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra));
}
/*
@@ -1386,12 +1387,12 @@ static void prepare_icount_for_run(CPUState *cpu)
* each vCPU execution. However u16.high can be raised
* asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
*/
- g_assert(cpu->icount_decr.u16.low == 0);
+ g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
g_assert(cpu->icount_extra == 0);
cpu->icount_budget = tcg_get_icount_limit();
insns_left = MIN(0xffff, cpu->icount_budget);
- cpu->icount_decr.u16.low = insns_left;
+ cpu_neg(cpu)->icount_decr.u16.low = insns_left;
cpu->icount_extra = cpu->icount_budget - insns_left;
replay_mutex_lock();
@@ -1405,7 +1406,7 @@ static void process_icount_data(CPUState *cpu)
cpu_update_icount(cpu);
/* Reset the counters */
- cpu->icount_decr.u16.low = 0;
+ cpu_neg(cpu)->icount_decr.u16.low = 0;
cpu->icount_extra = 0;
cpu->icount_budget = 0;
diff --git a/qom/cpu.c b/qom/cpu.c
index 3c5493c96c..6b4632abda 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -115,7 +115,7 @@ void cpu_exit(CPUState *cpu)
atomic_set(&cpu->exit_request, 1);
/* Ensure cpu_exec will see the exit request after TCG has exited. */
smp_wmb();
- atomic_set(&cpu->icount_decr.u16.high, -1);
+ atomic_set(&cpu->icount_decr_ptr->u16.high, -1);
}
int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -264,7 +264,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->mem_io_pc = 0;
cpu->mem_io_vaddr = 0;
cpu->icount_extra = 0;
- atomic_set(&cpu->icount_decr.u32, 0);
+ atomic_set(&cpu->icount_decr_ptr->u32, 0);
cpu->can_do_io = 1;
cpu->exception_index = -1;
cpu->crash_occurred = false;
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 35/39] cpu: Move the softmmu tlb to CPUNegativeOffsetState
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (33 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 34/39] cpu: Move icount_decr to CPUNegativeOffsetState Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-10 20:57 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON Richard Henderson
` (3 subsequent siblings)
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
We have for some time had code within the tcg backends to
handle large positive offsets from env. This move makes
sure that need not happen. Indeed, we are able to assert
at build time that simple offsets suffice for all hosts.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 22 +++++++++++++-------
tcg/aarch64/tcg-target.inc.c | 29 ++++++--------------------
tcg/arm/tcg-target.inc.c | 40 ++++++++----------------------------
tcg/i386/tcg-target.inc.c | 6 ++++--
tcg/mips/tcg-target.inc.c | 39 ++++++++---------------------------
tcg/ppc/tcg-target.inc.c | 30 ++++++++-------------------
tcg/riscv/tcg-target.inc.c | 31 +++++++---------------------
tcg/s390/tcg-target.inc.c | 11 +++++-----
tcg/sparc/tcg-target.inc.c | 32 +++++++++--------------------
9 files changed, 74 insertions(+), 166 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 3971910653..4cde7d611c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -178,13 +178,14 @@ typedef struct CPUTLBDesc {
/*
* Data elements that are per MMU mode, accessed by the fast path.
+ * The structure is aligned to aid loading the pair with one insn.
*/
typedef struct CPUTLBDescFast {
/* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
uintptr_t mask;
/* The array of tlb entries itself. */
CPUTLBEntry *table;
-} CPUTLBDescFast;
+} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
/*
* Data elements that are shared between all MMU modes.
@@ -211,28 +212,35 @@ typedef struct CPUTLBCommon {
/*
* The entire softmmu tlb, for all MMU modes.
* The meaning of each of the MMU modes is defined in the target code.
+ * Since this is placed within CPUNegativeOffsetState, the smallest
+ * negative offsets are at the end of the struct.
*/
typedef struct CPUTLB {
- CPUTLBDescFast f[NB_MMU_MODES];
- CPUTLBDesc d[NB_MMU_MODES];
CPUTLBCommon c;
+ CPUTLBDesc d[NB_MMU_MODES];
+ CPUTLBDescFast f[NB_MMU_MODES];
} CPUTLB;
-/* There are target-specific members named "tlb". This is temporary. */
-#define CPU_COMMON CPUTLB tlb_;
-#define env_tlb(ENV) (&(ENV)->tlb_)
+#define env_tlb(ENV) (&env_neg(ENV)->tlb)
+
+/* This will be used by TCG backends to compute offsets. */
+#define TLB_MASK_TABLE_OFS(IDX) \
+ ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env))
#else
-#define CPU_COMMON /* Nothing */
+typedef struct CPUTLB { } CPUTLB;
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#define CPU_COMMON /* Nothing */
+
/*
* This structure must be placed in ArchCPU immedately
* before CPUArchState, as a field named "neg".
*/
typedef struct CPUNegativeOffsetState {
+ CPUTLB tlb;
IcountDecr icount_decr;
} CPUNegativeOffsetState;
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 72cf4c5ff8..afac018301 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1455,9 +1455,9 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
label->label_ptr[0] = label_ptr;
}
-/* We expect to use a 24-bit unsigned offset from ENV. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
- > 0xffffff);
+/* We expect to use a 7-bit scaled negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512);
/* Load and compare a TLB entry, emitting the conditional jump to the
slow path for the failure case, which will be patched later when finalizing
@@ -1467,8 +1467,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
tcg_insn_unit **label_ptr, int mem_index,
bool is_read)
{
- int mask_ofs = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- int table_ofs = offsetof(CPUArchState, tlb_.f[mem_index].table);
+ int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
+ int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
unsigned a_bits = get_alignment_bits(opc);
unsigned s_bits = opc & MO_SIZE;
unsigned a_mask = (1u << a_bits) - 1;
@@ -1477,24 +1478,6 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
TCGType mask_type;
uint64_t compare_mask;
- if (table_ofs > 0xfff) {
- int table_hi = table_ofs & ~0xfff;
- int mask_hi = mask_ofs & ~0xfff;
-
- table_base = TCG_REG_X1;
- if (mask_hi == table_hi) {
- mask_base = table_base;
- } else if (mask_hi) {
- mask_base = TCG_REG_X0;
- tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64,
- mask_base, TCG_AREG0, mask_hi);
- }
- tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64,
- table_base, TCG_AREG0, table_hi);
- mask_ofs -= mask_hi;
- table_ofs -= table_hi;
- }
-
mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32
? TCG_TYPE_I64 : TCG_TYPE_I32);
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 28b911e550..ad32b04e13 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1220,9 +1220,9 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
-/* We expect to use a 20-bit unsigned offset from ENV. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
- > 0xfffff);
+/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
/* Load and compare a TLB entry, leaving the flags set. Returns the register
containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
@@ -1232,39 +1232,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
{
int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
- int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
- TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
- if (table_off > 0xfff) {
- int mask_hi = mask_off & ~0xfff;
- int table_hi = table_off & ~0xfff;
- int rot;
-
- table_base = TCG_REG_R2;
- if (mask_hi == table_hi) {
- mask_base = table_base;
- } else if (mask_hi) {
- mask_base = TCG_REG_TMP;
- rot = encode_imm(mask_hi);
- assert(rot >= 0);
- tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0,
- rotl(mask_hi, rot) | (rot << 7));
- }
- rot = encode_imm(table_hi);
- assert(rot >= 0);
- tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0,
- rotl(table_hi, rot) | (rot << 7));
-
- mask_off -= mask_hi;
- table_off -= table_hi;
- }
-
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off);
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off);
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off);
/* Extract the tlb index from the address into TMP. */
tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrlo,
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index b2e11a4b7c..fd6a9160ac 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -1655,10 +1655,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
- offsetof(CPUArchState, tlb_.f[mem_index].mask));
+ TLB_MASK_TABLE_OFS(mem_index) +
+ offsetof(CPUTLBDescFast, mask));
tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
- offsetof(CPUArchState, tlb_.f[mem_index].table));
+ TLB_MASK_TABLE_OFS(mem_index) +
+ offsetof(CPUTLBDescFast, table));
/* If the required alignment is at least as large as the access, simply
copy the address and mask. For lesser alignments, check that we don't
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 45b26e596f..46f7749cbc 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1201,6 +1201,10 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
return i;
}
+/* We expect to use a 16-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
+
/*
* Perform the tlb comparison operation.
* The complete host address is placed in BASE.
@@ -1214,42 +1218,17 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
int mem_index = get_mmuidx(oi);
- int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- int table_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
int add_off = offsetof(CPUTLBEntry, addend);
int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
- TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
target_ulong mask;
- if (table_off > 0x7fff) {
- int mask_hi = mask_off - (int16_t)mask_off;
- int table_hi = table_off - (int16_t)table_off;
-
- table_base = TCG_TMP1;
- if (likely(mask_hi == table_hi)) {
- mask_base = table_base;
- tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >> 16);
- tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0);
- mask_off -= mask_hi;
- table_off -= mask_hi;
- } else {
- if (mask_hi != 0) {
- mask_base = TCG_TMP0;
- tcg_out_opc_imm(s, OPC_LUI,
- mask_base, TCG_REG_ZERO, mask_hi >> 16);
- tcg_out_opc_reg(s, ALIAS_PADD,
- mask_base, mask_base, TCG_AREG0);
- }
- table_off -= mask_off;
- mask_off -= mask_hi;
- tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_off);
- }
- }
-
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
/* Extract the TLB index from the address into TMP3. */
tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index a248603bc5..400cee31ce 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -1497,6 +1497,10 @@ static void * const qemu_st_helpers[16] = {
[MO_BEQ] = helper_be_stq_mmu,
};
+/* We expect to use a 16-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
+
/* Perform the TLB load and compare. Places the result of the comparison
in CR7, loads the addend of the TLB into R3, and returns the register
containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
@@ -1509,31 +1513,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
= (is_read
? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write));
- int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
- TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
- if (table_off > 0x7fff) {
- int mask_hi = mask_off - (int16_t)mask_off;
- int table_hi = table_off - (int16_t)table_off;
-
- table_base = TCG_REG_R4;
- if (mask_hi == table_hi) {
- mask_base = table_base;
- } else if (mask_hi) {
- mask_base = TCG_REG_R3;
- tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16));
- }
- tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16));
- mask_off -= mask_hi;
- table_off -= table_hi;
- }
-
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
/* Extract the page index, shifted into place for tlb index. */
if (TCG_TARGET_REG_BITS == 32) {
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 85acbb9514..029d9a0fb2 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -961,6 +961,10 @@ static void * const qemu_st_helpers[16] = {
/* We don't support oversize guests */
QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
+/* We expect to use a 12-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
+
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
TCGReg addrh, TCGMemOpIdx oi,
tcg_insn_unit **label_ptr, bool is_load)
@@ -970,32 +974,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
unsigned a_bits = get_alignment_bits(opc);
tcg_target_long compare_mask;
int mem_index = get_mmuidx(oi);
- int mask_off, table_off;
+ int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
+ int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
- mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
- if (table_off > 0x7ff) {
- int mask_hi = mask_off - sextreg(mask_off, 0, 12);
- int table_hi = table_off - sextreg(table_off, 0, 12);
-
- if (likely(mask_hi == table_hi)) {
- mask_base = table_base = TCG_REG_TMP1;
- tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi);
- tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0);
- mask_off -= mask_hi;
- table_off -= mask_hi;
- } else {
- mask_base = TCG_REG_TMP0;
- table_base = TCG_REG_TMP1;
- tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi);
- tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0);
- table_off -= mask_off;
- mask_off -= mask_hi;
- tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off);
- }
- }
-
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off);
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off);
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 1f578ea980..0ce129a369 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1537,9 +1537,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
#if defined(CONFIG_SOFTMMU)
#include "tcg-ldst.inc.c"
-/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */
-QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
- > 0x7ffff);
+/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
addend into R2. Returns a register with the santitized guest address. */
@@ -1550,8 +1550,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
unsigned a_bits = get_alignment_bits(opc);
unsigned s_mask = (1 << s_bits) - 1;
unsigned a_mask = (1 << a_bits) - 1;
- int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
int ofs, a_off;
uint64_t tlb_mask;
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index be10124e11..fe7524a802 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1061,6 +1061,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
}
#if defined(CONFIG_SOFTMMU)
+
+/* We expect to use a 13-bit negative offset from ENV. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));
+
/* Perform the TLB load and compare.
Inputs:
@@ -1077,9 +1082,9 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
TCGMemOp opc, int which)
{
- int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
- int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
- TCGReg base = TCG_AREG0;
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
const TCGReg r0 = TCG_REG_O0;
const TCGReg r1 = TCG_REG_O1;
const TCGReg r2 = TCG_REG_O2;
@@ -1087,26 +1092,9 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
unsigned a_bits = get_alignment_bits(opc);
tcg_target_long compare_mask;
- if (!check_fit_i32(table_off, 13)) {
- int table_hi;
-
- base = r1;
- if (table_off <= 2 * 0xfff) {
- table_hi = 0xfff;
- tcg_out_arithi(s, base, TCG_AREG0, table_hi, ARITH_ADD);
- } else {
- table_hi = table_off & ~0x3ff;
- tcg_out_sethi(s, base, table_hi);
- tcg_out_arith(s, base, TCG_AREG0, base, ARITH_ADD);
- }
- mask_off -= table_hi;
- table_off -= table_hi;
- tcg_debug_assert(check_fit_i32(mask_off, 13));
- }
-
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, r0, base, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, r1, base, table_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off);
/* Extract the page index, shifted into place for tlb index. */
tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (34 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 35/39] cpu: Move the softmmu tlb " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-10 20:58 ` Alistair Francis
2019-05-11 13:21 ` Aleksandar Markovic
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 37/39] tcg/aarch64: Use LDP to load tlb mask+table Richard Henderson
` (2 subsequent siblings)
38 siblings, 2 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
This macro is now always empty, so remove it. This leaves the
entire contents of CPUArchState under the control of the guest
architecture.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 2 --
target/alpha/cpu.h | 3 ---
target/arm/cpu.h | 4 +---
target/cris/cpu.h | 2 --
target/hppa/cpu.h | 3 ---
target/i386/cpu.h | 4 +---
target/lm32/cpu.h | 2 --
target/m68k/cpu.h | 2 --
target/microblaze/cpu.h | 2 --
target/mips/cpu.h | 2 --
target/moxie/cpu.h | 3 ---
target/nios2/cpu.h | 2 --
target/openrisc/cpu.h | 2 --
target/ppc/cpu.h | 2 --
target/riscv/cpu.h | 4 ----
target/s390x/cpu.h | 2 --
target/sh4/cpu.h | 2 --
target/sparc/cpu.h | 2 --
target/tilegx/cpu.h | 2 --
target/tricore/cpu.h | 2 --
target/unicore32/cpu.h | 2 --
target/xtensa/cpu.h | 2 --
22 files changed, 2 insertions(+), 51 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 4cde7d611c..1f75a97701 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB;
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
-#define CPU_COMMON /* Nothing */
-
/*
* This structure must be placed in ArchCPU immedately
* before CPUArchState, as a field named "neg".
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index f4bb67c101..5bd90b7ce5 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -246,9 +246,6 @@ struct CPUAlphaState {
/* This alarm doesn't exist in real hardware; we wish it did. */
uint64_t alarm_expire;
- /* Those resources are used only in QEMU core */
- CPU_COMMON
-
int error_code;
uint32_t features;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 909cb4604d..135a16a351 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -643,9 +643,7 @@ typedef struct CPUARMState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
- /* Fields after CPU_COMMON are preserved across CPU reset. */
+ /* Fields after this point are preserved across CPU reset. */
/* Internal CPU feature flags. */
uint64_t features;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index eeab483dba..6dc4502e9a 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -163,8 +163,6 @@ typedef struct CPUCRISState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Members from load_info on are preserved across resets. */
void *load_info;
} CPUCRISState;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 0661ff60c1..3ed2ac3c25 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -197,9 +197,6 @@ struct CPUHPPAState {
target_ureg cr_back[2]; /* back of cr17/cr18 */
target_ureg shadow[7]; /* shadow registers */
- /* Those resources are used only in QEMU core */
- CPU_COMMON
-
/* ??? The number of entries isn't specified by the architecture. */
/* ??? Implement a unified itlb/dtlb for the moment. */
/* ??? We should use a more intelligent data structure. */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 43bb6ab841..8069e5b19d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1288,9 +1288,7 @@ typedef struct CPUX86State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
- /* Fields after CPU_COMMON are preserved across CPU reset. */
+ /* Fields after this point are preserved across CPU reset. */
/* processor features (e.g. for CPUID insn) */
/* Minimum level/xlevel/xlevel2, based on CPU model + features */
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 0ec898eb1d..563600a30a 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -159,8 +159,6 @@ struct CPULM32State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
uint32_t eba; /* exception base address */
uint32_t deba; /* debug exception base address */
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 096d1eb588..4e27ff677f 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -143,8 +143,6 @@ typedef struct CPUM68KState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
uint32_t features;
} CPUM68KState;
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 732653caed..6a470a2492 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -266,8 +266,6 @@ struct CPUMBState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* These fields are preserved on reset. */
struct {
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2d9c5f26eb..b9e58ed883 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1021,8 +1021,6 @@ struct CPUMIPSState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index f5ee8a02f4..a62cca1817 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -45,9 +45,6 @@ typedef struct CPUMoxieState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
-
- CPU_COMMON
-
} CPUMoxieState;
#include "qom/cpu.h"
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index cd06a2ef41..75ea964632 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -166,8 +166,6 @@ struct CPUNios2State {
uint32_t irq_pending;
#endif
-
- CPU_COMMON
};
/**
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index e1acd48652..e3ffa618c9 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
uint32_t cpucfgr; /* CPU configure register */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bb57496212..bbc8eb0cfc 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -999,8 +999,6 @@ struct CPUPPCState {
/* when a memory exception occurs, the access type is stored here */
int access_type;
- CPU_COMMON
-
/* MMU context - only relevant for full system emulation */
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 30a01e8386..7086b336c6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -169,10 +169,6 @@ struct CPURISCVState {
float_status fp_status;
- /* QEMU */
- CPU_COMMON
-
- /* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */
};
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index ebcf7863e4..17d54f9587 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -114,8 +114,6 @@ struct CPUS390XState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
#if !defined(CONFIG_USER_ONLY)
uint32_t core_id; /* PoP "CPU address", same as cpu_index */
uint64_t cpuid;
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 944854dbe0..974d46aae1 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -179,8 +179,6 @@ typedef struct CPUSH4State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved over CPU reset. */
int id; /* CPU model */
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index ae9ac07a9d..69e2199569 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -446,8 +446,6 @@ struct CPUSPARCState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
target_ulong version;
uint32_t nwindows;
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index deb3e836ea..c2acb43c2b 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -93,8 +93,6 @@ typedef struct CPUTLGState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
-
- CPU_COMMON
} CPUTLGState;
#include "qom/cpu.h"
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 43ef29b6bd..9fe501f98f 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -184,8 +184,6 @@ struct CPUTriCoreState {
int error_code;
uint32_t hflags; /* CPU State */
- CPU_COMMON
-
/* Internal CPU feature flags. */
uint64_t features;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 140c590ec1..1ae0d78f4f 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -55,8 +55,6 @@ typedef struct CPUUniCore32State {
float_status fp_status;
} ucf64;
- CPU_COMMON
-
/* Internal CPU feature flags. */
uint32_t features;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 1bbb839bed..4e289dfa6e 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -511,8 +511,6 @@ typedef struct CPUXtensaState {
/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
-
- CPU_COMMON
} CPUXtensaState;
/**
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 37/39] tcg/aarch64: Use LDP to load tlb mask+table
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (35 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-10 21:01 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD " Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 39/39] tcg/arm: Remove mostly unreachable tlb special case Richard Henderson
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
This changes the code generation for the tlb from e.g.
ldur x0, [x19, #0xffffffffffffffe0]
ldur x1, [x19, #0xffffffffffffffe8]
and x0, x0, x20, lsr #8
add x1, x1, x0
ldr x0, [x1]
ldr x1, [x1, #0x18]
to
ldp x0, x1, [x19, #-0x20]
and x0, x0, x20, lsr #8
add x1, x1, x0
ldr x0, [x1]
ldr x1, [x1, #0x18]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes.
---
tcg/aarch64/tcg-target.inc.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index afac018301..2863a371a0 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -1459,6 +1459,10 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512);
+/* These offsets are built into the LDP below. */
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);
+
/* Load and compare a TLB entry, emitting the conditional jump to the
slow path for the failure case, which will be patched later when finalizing
the slow path. Generated code returns the host addend in X1,
@@ -1467,23 +1471,20 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
tcg_insn_unit **label_ptr, int mem_index,
bool is_read)
{
- int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
- int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
- int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
unsigned a_bits = get_alignment_bits(opc);
unsigned s_bits = opc & MO_SIZE;
unsigned a_mask = (1u << a_bits) - 1;
unsigned s_mask = (1u << s_bits) - 1;
- TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0, x3;
+ TCGReg x3;
TCGType mask_type;
uint64_t compare_mask;
mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32
? TCG_TYPE_I64 : TCG_TYPE_I32);
- /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs);
+ /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */
+ tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0,
+ TLB_MASK_TABLE_OFS(mem_index), 1, 0);
/* Extract the TLB index from the address into X0. */
tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64,
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD to load tlb mask+table
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (36 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 37/39] tcg/aarch64: Use LDP to load tlb mask+table Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-10 21:08 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 39/39] tcg/arm: Remove mostly unreachable tlb special case Richard Henderson
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
This changes the code generation for the tlb from e.g.
ldr ip, [r6, #-0x10]
ldr r2, [r6, #-0xc]
and ip, ip, r4, lsr #8
ldrd r0, r1, [r2, ip]!
ldr r2, [r2, #0x18]
to
ldrd r0, r1, [r6, #-0x10]
and r0, r0, r4, lsr #8
ldrd r2, r3, [r1, r0]!
ldr r1, [r1, #0x18]
for armv7 hosts. Rearranging the register allocation in
order to avoid overlap between the two ldrd pairs causes
the patch to be larger than it ordinarily would be.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes.
---
tcg/arm/tcg-target.inc.c | 92 +++++++++++++++++++++++-----------------
1 file changed, 53 insertions(+), 39 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index ad32b04e13..ac813abfb8 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -267,6 +267,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
#endif
break;
@@ -1224,6 +1225,10 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
+/* These offsets are built into the LDRD below. */
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
+QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
+
/* Load and compare a TLB entry, leaving the flags set. Returns the register
containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
@@ -1238,47 +1243,54 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
unsigned s_bits = opc & MO_SIZE;
unsigned a_bits = get_alignment_bits(opc);
- /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off);
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off);
-
- /* Extract the tlb index from the address into TMP. */
- tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrlo,
- SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
-
/*
- * Add the tlb_table pointer, creating the CPUTLBEntry address in R2.
- * Load the tlb comparator into R0/R1 and the fast path addend into R2.
+ * We don't support inline unaligned acceses, but we can easily
+ * support overalignment checks.
*/
- if (cmp_off == 0) {
- if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
- tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_TMP);
- } else {
- tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_TMP);
- }
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
- TCG_REG_R2, TCG_REG_R2, TCG_REG_TMP, 0);
- if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
- tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off);
- } else {
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off);
- }
- }
- if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4);
- }
-
- /* Load the tlb addend. */
- tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2,
- offsetof(CPUTLBEntry, addend));
-
- /* Check alignment. We don't support inline unaligned acceses,
- but we can easily support overalignment checks. */
if (a_bits < s_bits) {
a_bits = s_bits;
}
+ /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
+ if (use_armv6_instructions) {
+ tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
+ } else {
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off);
+ }
+
+ /* Extract the tlb index from the address into R0. */
+ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
+ SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
+
+ /*
+ * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
+ * Load the tlb comparator into R2/R3 and the fast path addend into R1.
+ */
+ if (cmp_off == 0) {
+ if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
+ tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
+ } else {
+ tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
+ }
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
+ TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
+ if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
+ tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
+ } else {
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
+ }
+ }
+ if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4);
+ }
+
+ /* Load the tlb addend. */
+ tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
+ offsetof(CPUTLBEntry, addend));
+
+ /* Check alignment, check comparators. */
if (use_armv7_instructions) {
tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
int rot = encode_imm(mask);
@@ -1291,22 +1303,24 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
addrlo, TCG_REG_TMP, 0);
}
- tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, 0);
+ tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
} else {
if (a_bits) {
tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,
(1 << a_bits) - 1);
}
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo,
+ SHIFT_IMM_LSR(TARGET_PAGE_BITS));
tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,
- 0, TCG_REG_R0, TCG_REG_TMP,
+ 0, TCG_REG_R2, TCG_REG_TMP,
SHIFT_IMM_LSL(TARGET_PAGE_BITS));
}
if (TARGET_LONG_BITS == 64) {
- tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0);
+ tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
}
- return TCG_REG_R2;
+ return TCG_REG_R1;
}
/* Record the context of a call to the out of line helper code for the slow
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [Qemu-devel] [PATCH v3 39/39] tcg/arm: Remove mostly unreachable tlb special case
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
` (37 preceding siblings ...)
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD " Richard Henderson
@ 2019-05-08 0:06 ` Richard Henderson
2019-05-10 21:04 ` Alistair Francis
38 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 0:06 UTC (permalink / raw)
To: qemu-devel
There was nothing armv7 specific about the bic+cmp sequence, however
looking at the set of guests more closely shows that the 8-bit immediate
operand for the bic can only be satisfied with one guest in tree:
baseline m-profile -- 10-bit pages with aligned 4-byte memory ops.
Therefore it does not seem useful to keep this path.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.inc.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index ac813abfb8..e0fcc1d990 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1290,19 +1290,20 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
offsetof(CPUTLBEntry, addend));
- /* Check alignment, check comparators. */
- if (use_armv7_instructions) {
+ /*
+ * Check alignment, check comparators.
+ * Do this in no more than 3 insns. Use MOVW for v7, if possible,
+ * to reduce the number of sequential conditional instructions.
+ * Almost all guests have at least 4k pages, which means that we need
+ * to clear at least 9 bits even for an 8-byte memory, which means it
+ * isn't worth checking for an immediate operand for BIC.
+ */
+ if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
- int rot = encode_imm(mask);
- if (rot >= 0) {
- tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo,
- rotl(mask, rot) | (rot << 7));
- } else {
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
- tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
- addrlo, TCG_REG_TMP, 0);
- }
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
+ tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
+ addrlo, TCG_REG_TMP, 0);
tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
} else {
if (a_bits) {
--
2.17.1
^ permalink raw reply related [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c Richard Henderson
@ 2019-05-08 6:26 ` Philippe Mathieu-Daudé
2019-05-09 18:01 ` Alistair Francis
1 sibling, 0 replies; 81+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-05-08 6:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 5/8/19 2:06 AM, Richard Henderson wrote:
> Fix all of the coding style errors in this file at once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/cris/mmu.c | 479 +++++++++++++++++++++++-----------------------
> 1 file changed, 237 insertions(+), 242 deletions(-)
>
> diff --git a/target/cris/mmu.c b/target/cris/mmu.c
> index b8db908823..9cb73bbfec 100644
> --- a/target/cris/mmu.c
> +++ b/target/cris/mmu.c
> @@ -33,96 +33,99 @@
>
> void cris_mmu_init(CPUCRISState *env)
> {
> - env->mmu_rand_lfsr = 0xcccc;
> + env->mmu_rand_lfsr = 0xcccc;
> }
>
> #define SR_POLYNOM 0x8805
> static inline unsigned int compute_polynom(unsigned int sr)
> {
> - unsigned int i;
> - unsigned int f;
> + unsigned int i;
> + unsigned int f;
>
> - f = 0;
> - for (i = 0; i < 16; i++)
> - f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
> + f = 0;
> + for (i = 0; i < 16; i++) {
> + f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
> + }
>
> - return f;
> + return f;
> }
>
> static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
> {
> - unsigned int f;
> + unsigned int f;
>
> - /* Update lfsr at every fault. */
> - f = compute_polynom(env->mmu_rand_lfsr);
> - env->mmu_rand_lfsr >>= 1;
> - env->mmu_rand_lfsr |= (f << 15);
> - env->mmu_rand_lfsr &= 0xffff;
> + /* Update lfsr at every fault. */
> + f = compute_polynom(env->mmu_rand_lfsr);
> + env->mmu_rand_lfsr >>= 1;
> + env->mmu_rand_lfsr |= (f << 15);
> + env->mmu_rand_lfsr &= 0xffff;
> }
>
> static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
> {
> - return (rw_gc_cfg & 12) != 0;
> + return (rw_gc_cfg & 12) != 0;
> }
>
> static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
> {
> - return (1 << seg) & rw_mm_cfg;
> + return (1 << seg) & rw_mm_cfg;
> }
>
> static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
> {
> - uint32_t base;
> - int i;
> + uint32_t base;
> + int i;
>
> - if (seg < 8)
> - base = env->sregs[SFR_RW_MM_KBASE_LO];
> - else
> - base = env->sregs[SFR_RW_MM_KBASE_HI];
> + if (seg < 8) {
> + base = env->sregs[SFR_RW_MM_KBASE_LO];
> + } else {
> + base = env->sregs[SFR_RW_MM_KBASE_HI];
> + }
>
> - i = seg & 7;
> - base >>= i * 4;
> - base &= 15;
> + i = seg & 7;
> + base >>= i * 4;
> + base &= 15;
>
> - base <<= 28;
> - return base;
> + base <<= 28;
> + return base;
> }
> -/* Used by the tlb decoder. */
> -#define EXTRACT_FIELD(src, start, end) \
> - (((src) >> start) & ((1 << (end - start + 1)) - 1))
>
> -static inline void set_field(uint32_t *dst, unsigned int val,
> +/* Used by the tlb decoder. */
> +#define EXTRACT_FIELD(src, start, end) \
> + (((src) >> start) & ((1 << (end - start + 1)) - 1))
> +
> +static inline void set_field(uint32_t *dst, unsigned int val,
> unsigned int offset, unsigned int width)
> {
> - uint32_t mask;
> + uint32_t mask;
>
> - mask = (1 << width) - 1;
> - mask <<= offset;
> - val <<= offset;
> + mask = (1 << width) - 1;
> + mask <<= offset;
> + val <<= offset;
>
> - val &= mask;
> - *dst &= ~(mask);
> - *dst |= val;
> + val &= mask;
> + *dst &= ~(mask);
> + *dst |= val;
> }
>
> #ifdef DEBUG
> static void dump_tlb(CPUCRISState *env, int mmu)
> {
> - int set;
> - int idx;
> - uint32_t hi, lo, tlb_vpn, tlb_pfn;
> + int set;
> + int idx;
> + uint32_t hi, lo, tlb_vpn, tlb_pfn;
>
> - for (set = 0; set < 4; set++) {
> - for (idx = 0; idx < 16; idx++) {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> - tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> - tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> + for (set = 0; set < 4; set++) {
> + for (idx = 0; idx < 16; idx++) {
> + lo = env->tlbsets[mmu][set][idx].lo;
> + hi = env->tlbsets[mmu][set][idx].hi;
> + tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> + tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
>
> - printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
> - set, idx, hi, lo, tlb_vpn, tlb_pfn);
> - }
> - }
> + printf("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
> + set, idx, hi, lo, tlb_vpn, tlb_pfn);
> + }
> + }
> }
> #endif
>
> @@ -131,232 +134,224 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
> CPUCRISState *env, uint32_t vaddr,
> int rw, int usermode, int debug)
> {
> - unsigned int vpage;
> - unsigned int idx;
> - uint32_t pid, lo, hi;
> - uint32_t tlb_vpn, tlb_pfn = 0;
> - int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
> - int cfg_v, cfg_k, cfg_w, cfg_x;
> - int set, match = 0;
> - uint32_t r_cause;
> - uint32_t r_cfg;
> - int rwcause;
> - int mmu = 1; /* Data mmu is default. */
> - int vect_base;
> + unsigned int vpage;
> + unsigned int idx;
> + uint32_t pid, lo, hi;
> + uint32_t tlb_vpn, tlb_pfn = 0;
> + int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
> + int cfg_v, cfg_k, cfg_w, cfg_x;
> + int set, match = 0;
> + uint32_t r_cause;
> + uint32_t r_cfg;
> + int rwcause;
> + int mmu = 1; /* Data mmu is default. */
> + int vect_base;
>
> - r_cause = env->sregs[SFR_R_MM_CAUSE];
> - r_cfg = env->sregs[SFR_RW_MM_CFG];
> - pid = env->pregs[PR_PID] & 0xff;
> + r_cause = env->sregs[SFR_R_MM_CAUSE];
> + r_cfg = env->sregs[SFR_RW_MM_CFG];
> + pid = env->pregs[PR_PID] & 0xff;
>
> - switch (rw) {
> - case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
> - case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
> - default:
> - case 0: rwcause = CRIS_MMU_ERR_READ; break;
> - }
> + switch (rw) {
> + case 2:
> + rwcause = CRIS_MMU_ERR_EXEC;
> + mmu = 0;
> + break;
> + case 1:
> + rwcause = CRIS_MMU_ERR_WRITE;
> + break;
> + default:
> + case 0:
> + rwcause = CRIS_MMU_ERR_READ;
> + break;
> + }
>
> - /* I exception vectors 4 - 7, D 8 - 11. */
> - vect_base = (mmu + 1) * 4;
> + /* I exception vectors 4 - 7, D 8 - 11. */
> + vect_base = (mmu + 1) * 4;
>
> - vpage = vaddr >> 13;
> + vpage = vaddr >> 13;
>
> - /* We know the index which to check on each set.
> - Scan both I and D. */
> -#if 0
> - for (set = 0; set < 4; set++) {
> - for (idx = 0; idx < 16; idx++) {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> - tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> - tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
You remove dead code, OK.
Reviewed using 'git diff --ignore-all-space --word-diff=color'.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> + /*
> + * We know the index which to check on each set.
> + * Scan both I and D.
> + */
> + idx = vpage & 15;
> + for (set = 0; set < 4; set++) {
> + lo = env->tlbsets[mmu][set][idx].lo;
> + hi = env->tlbsets[mmu][set][idx].hi;
>
> - printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
> - set, idx, hi, lo, tlb_vpn, tlb_pfn);
> - }
> - }
> -#endif
> + tlb_vpn = hi >> 13;
> + tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> + tlb_g = EXTRACT_FIELD(lo, 4, 4);
>
> - idx = vpage & 15;
> - for (set = 0; set < 4; set++)
> - {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> + D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
> + mmu, set, idx, tlb_vpn, vpage, lo, hi);
> + if ((tlb_g || (tlb_pid == pid)) && tlb_vpn == vpage) {
> + match = 1;
> + break;
> + }
> + }
>
> - tlb_vpn = hi >> 13;
> - tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> - tlb_g = EXTRACT_FIELD(lo, 4, 4);
> + res->bf_vec = vect_base;
> + if (match) {
> + cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
> + cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
> + cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
> + cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
>
> - D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
> - mmu, set, idx, tlb_vpn, vpage, lo, hi);
> - if ((tlb_g || (tlb_pid == pid))
> - && tlb_vpn == vpage) {
> - match = 1;
> - break;
> - }
> - }
> + tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> + tlb_v = EXTRACT_FIELD(lo, 3, 3);
> + tlb_k = EXTRACT_FIELD(lo, 2, 2);
> + tlb_w = EXTRACT_FIELD(lo, 1, 1);
> + tlb_x = EXTRACT_FIELD(lo, 0, 0);
>
> - res->bf_vec = vect_base;
> - if (match) {
> - cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
> - cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
> - cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
> - cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
> + /*
> + * set_exception_vector(0x04, i_mmu_refill);
> + * set_exception_vector(0x05, i_mmu_invalid);
> + * set_exception_vector(0x06, i_mmu_access);
> + * set_exception_vector(0x07, i_mmu_execute);
> + * set_exception_vector(0x08, d_mmu_refill);
> + * set_exception_vector(0x09, d_mmu_invalid);
> + * set_exception_vector(0x0a, d_mmu_access);
> + * set_exception_vector(0x0b, d_mmu_write);
> + */
> + if (cfg_k && tlb_k && usermode) {
> + D(printf("tlb: kernel protected %x lo=%x pc=%x\n",
> + vaddr, lo, env->pc));
> + match = 0;
> + res->bf_vec = vect_base + 2;
> + } else if (rw == 1 && cfg_w && !tlb_w) {
> + D(printf("tlb: write protected %x lo=%x pc=%x\n",
> + vaddr, lo, env->pc));
> + match = 0;
> + /* write accesses never go through the I mmu. */
> + res->bf_vec = vect_base + 3;
> + } else if (rw == 2 && cfg_x && !tlb_x) {
> + D(printf("tlb: exec protected %x lo=%x pc=%x\n",
> + vaddr, lo, env->pc));
> + match = 0;
> + res->bf_vec = vect_base + 3;
> + } else if (cfg_v && !tlb_v) {
> + D(printf("tlb: invalid %x\n", vaddr));
> + match = 0;
> + res->bf_vec = vect_base + 1;
> + }
>
> - tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> - tlb_v = EXTRACT_FIELD(lo, 3, 3);
> - tlb_k = EXTRACT_FIELD(lo, 2, 2);
> - tlb_w = EXTRACT_FIELD(lo, 1, 1);
> - tlb_x = EXTRACT_FIELD(lo, 0, 0);
> + res->prot = 0;
> + if (match) {
> + res->prot |= PAGE_READ;
> + if (tlb_w) {
> + res->prot |= PAGE_WRITE;
> + }
> + if (mmu == 0 && (cfg_x || tlb_x)) {
> + res->prot |= PAGE_EXEC;
> + }
> + } else {
> + D(dump_tlb(env, mmu));
> + }
> + } else {
> + /* If refill, provide a randomized set. */
> + set = env->mmu_rand_lfsr & 3;
> + }
>
> - /*
> - set_exception_vector(0x04, i_mmu_refill);
> - set_exception_vector(0x05, i_mmu_invalid);
> - set_exception_vector(0x06, i_mmu_access);
> - set_exception_vector(0x07, i_mmu_execute);
> - set_exception_vector(0x08, d_mmu_refill);
> - set_exception_vector(0x09, d_mmu_invalid);
> - set_exception_vector(0x0a, d_mmu_access);
> - set_exception_vector(0x0b, d_mmu_write);
> - */
> - if (cfg_k && tlb_k && usermode) {
> - D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
> - vaddr, lo, env->pc));
> - match = 0;
> - res->bf_vec = vect_base + 2;
> - } else if (rw == 1 && cfg_w && !tlb_w) {
> - D(printf ("tlb: write protected %x lo=%x pc=%x\n",
> - vaddr, lo, env->pc));
> - match = 0;
> - /* write accesses never go through the I mmu. */
> - res->bf_vec = vect_base + 3;
> - } else if (rw == 2 && cfg_x && !tlb_x) {
> - D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
> - vaddr, lo, env->pc));
> - match = 0;
> - res->bf_vec = vect_base + 3;
> - } else if (cfg_v && !tlb_v) {
> - D(printf ("tlb: invalid %x\n", vaddr));
> - match = 0;
> - res->bf_vec = vect_base + 1;
> - }
> + if (!match && !debug) {
> + cris_mmu_update_rand_lfsr(env);
>
> - res->prot = 0;
> - if (match) {
> - res->prot |= PAGE_READ;
> - if (tlb_w)
> - res->prot |= PAGE_WRITE;
> - if (mmu == 0 && (cfg_x || tlb_x))
> - res->prot |= PAGE_EXEC;
> - }
> - else
> - D(dump_tlb(env, mmu));
> - } else {
> - /* If refill, provide a randomized set. */
> - set = env->mmu_rand_lfsr & 3;
> - }
> + /* Compute index. */
> + idx = vpage & 15;
>
> - if (!match && !debug) {
> - cris_mmu_update_rand_lfsr(env);
> + /* Update RW_MM_TLB_SEL. */
> + env->sregs[SFR_RW_MM_TLB_SEL] = 0;
> + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
> + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
>
> - /* Compute index. */
> - idx = vpage & 15;
> + /* Update RW_MM_CAUSE. */
> + set_field(&r_cause, rwcause, 8, 2);
> + set_field(&r_cause, vpage, 13, 19);
> + set_field(&r_cause, pid, 0, 8);
> + env->sregs[SFR_R_MM_CAUSE] = r_cause;
> + D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
> + }
>
> - /* Update RW_MM_TLB_SEL. */
> - env->sregs[SFR_RW_MM_TLB_SEL] = 0;
> - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
> - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
> + D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
> + " %x cause=%x sel=%x sp=%x %x %x\n",
> + __func__, rw, match, env->pc,
> + vaddr, vpage,
> + tlb_vpn, tlb_pfn, tlb_pid,
> + pid,
> + r_cause,
> + env->sregs[SFR_RW_MM_TLB_SEL],
> + env->regs[R_SP], env->pregs[PR_USP], env->ksp));
>
> - /* Update RW_MM_CAUSE. */
> - set_field(&r_cause, rwcause, 8, 2);
> - set_field(&r_cause, vpage, 13, 19);
> - set_field(&r_cause, pid, 0, 8);
> - env->sregs[SFR_R_MM_CAUSE] = r_cause;
> - D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
> - }
> -
> - D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
> - " %x cause=%x sel=%x sp=%x %x %x\n",
> - __func__, rw, match, env->pc,
> - vaddr, vpage,
> - tlb_vpn, tlb_pfn, tlb_pid,
> - pid,
> - r_cause,
> - env->sregs[SFR_RW_MM_TLB_SEL],
> - env->regs[R_SP], env->pregs[PR_USP], env->ksp));
> -
> - res->phy = tlb_pfn << TARGET_PAGE_BITS;
> - return !match;
> + res->phy = tlb_pfn << TARGET_PAGE_BITS;
> + return !match;
> }
>
> void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> CRISCPU *cpu = cris_env_get_cpu(env);
> - target_ulong vaddr;
> - unsigned int idx;
> - uint32_t lo, hi;
> - uint32_t tlb_vpn;
> - int tlb_pid, tlb_g, tlb_v;
> - unsigned int set;
> - unsigned int mmu;
> + target_ulong vaddr;
> + unsigned int idx;
> + uint32_t lo, hi;
> + uint32_t tlb_vpn;
> + int tlb_pid, tlb_g, tlb_v;
> + unsigned int set;
> + unsigned int mmu;
>
> - pid &= 0xff;
> - for (mmu = 0; mmu < 2; mmu++) {
> - for (set = 0; set < 4; set++)
> - {
> - for (idx = 0; idx < 16; idx++) {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> -
> - tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> - tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> - tlb_g = EXTRACT_FIELD(lo, 4, 4);
> - tlb_v = EXTRACT_FIELD(lo, 3, 3);
> + pid &= 0xff;
> + for (mmu = 0; mmu < 2; mmu++) {
> + for (set = 0; set < 4; set++) {
> + for (idx = 0; idx < 16; idx++) {
> + lo = env->tlbsets[mmu][set][idx].lo;
> + hi = env->tlbsets[mmu][set][idx].hi;
>
> - if (tlb_v && !tlb_g && (tlb_pid == pid)) {
> - vaddr = tlb_vpn << TARGET_PAGE_BITS;
> - D_LOG("flush pid=%x vaddr=%x\n",
> - pid, vaddr);
> + tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> + tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> + tlb_g = EXTRACT_FIELD(lo, 4, 4);
> + tlb_v = EXTRACT_FIELD(lo, 3, 3);
> +
> + if (tlb_v && !tlb_g && (tlb_pid == pid)) {
> + vaddr = tlb_vpn << TARGET_PAGE_BITS;
> + D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
> tlb_flush_page(CPU(cpu), vaddr);
> - }
> - }
> - }
> - }
> + }
> + }
> + }
> + }
> }
>
> int cris_mmu_translate(struct cris_mmu_result *res,
> CPUCRISState *env, uint32_t vaddr,
> int rw, int mmu_idx, int debug)
> {
> - int seg;
> - int miss = 0;
> - int is_user = mmu_idx == MMU_USER_IDX;
> - uint32_t old_srs;
> + int seg;
> + int miss = 0;
> + int is_user = mmu_idx == MMU_USER_IDX;
> + uint32_t old_srs;
>
> - old_srs= env->pregs[PR_SRS];
> + old_srs = env->pregs[PR_SRS];
>
> - /* rw == 2 means exec, map the access to the insn mmu. */
> - env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
> + /* rw == 2 means exec, map the access to the insn mmu. */
> + env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
>
> - if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
> - res->phy = vaddr;
> - res->prot = PAGE_BITS;
> - goto done;
> - }
> + if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
> + res->phy = vaddr;
> + res->prot = PAGE_BITS;
> + goto done;
> + }
>
> - seg = vaddr >> 28;
> - if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
> - {
> - uint32_t base;
> + seg = vaddr >> 28;
> + if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
> + uint32_t base;
>
> - miss = 0;
> - base = cris_mmu_translate_seg(env, seg);
> - res->phy = base | (0x0fffffff & vaddr);
> - res->prot = PAGE_BITS;
> - } else {
> - miss = cris_mmu_translate_page(res, env, vaddr, rw,
> - is_user, debug);
> - }
> - done:
> - env->pregs[PR_SRS] = old_srs;
> - return miss;
> + miss = 0;
> + base = cris_mmu_translate_seg(env, seg);
> + res->phy = base | (0x0fffffff & vaddr);
> + res->prot = PAGE_BITS;
> + } else {
> + miss = cris_mmu_translate_page(res, env, vaddr, rw,
> + is_user, debug);
> + }
> + done:
> + env->pregs[PR_SRS] = old_srs;
> + return miss;
> }
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c Richard Henderson
@ 2019-05-08 6:28 ` Philippe Mathieu-Daudé
2019-05-09 18:03 ` Alistair Francis
1 sibling, 0 replies; 81+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-05-08 6:28 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 5/8/19 2:06 AM, Richard Henderson wrote:
> Fix all of the coding style errors in this file at once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/cris/op_helper.c | 817 +++++++++++++++++++---------------------
> 1 file changed, 398 insertions(+), 419 deletions(-)
Reviewed using 'git diff --ignore-all-space --word-diff=color'.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 18/39] target/mips: " Richard Henderson
@ 2019-05-08 8:15 ` Aleksandar Markovic
2019-05-08 14:32 ` Richard Henderson
0 siblings, 1 reply; 81+ messages in thread
From: Aleksandar Markovic @ 2019-05-08 8:15 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On May 8, 2019 2:19 AM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
>
>
This commit message doesnˊt explain the reason for the change, and why is
this an improvement. The underlyng reason for distingishing between
env_cpu and env_archcpu cases is not explained too.
Thanks,
Aleksandar
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/cpu.h | 5 -----
> hw/intc/mips_gic.c | 2 +-
> hw/mips/mips_int.c | 2 +-
> linux-user/mips/cpu_loop.c | 2 +-
> target/mips/helper.c | 15 +++++----------
> target/mips/op_helper.c | 25 +++++++++++--------------
> target/mips/translate.c | 3 +--
> target/mips/translate_init.inc.c | 4 +---
> 8 files changed, 21 insertions(+), 37 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 31e15834ca..e0645eb1d1 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1051,11 +1051,6 @@ struct MIPSCPU {
> CPUMIPSState env;
> };
>
> -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
> -{
> - return container_of(env, MIPSCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(MIPSCPU, env)
>
> void mips_cpu_list(void);
> diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c
> index 15e6e40f9f..8f509493ea 100644
> --- a/hw/intc/mips_gic.c
> +++ b/hw/intc/mips_gic.c
> @@ -44,7 +44,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int
vp, int pin)
> GIC_VP_MASK_CMP_SHF;
> }
> if (kvm_enabled()) {
> - kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env),
> + kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env),
> pin + GIC_CPU_PIN_OFFSET,
> ored_level);
> } else {
> diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
> index 5ddeb15848..f899f6ceb3 100644
> --- a/hw/mips/mips_int.c
> +++ b/hw/mips/mips_int.c
> @@ -76,7 +76,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
> qemu_irq *qi;
> int i;
>
> - qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env),
8);
> + qi = qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8);
> for (i = 0; i < 8; i++) {
> env->irq[i] = qi[i];
> }
> diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
> index 828137cd84..ac6c6d1504 100644
> --- a/linux-user/mips/cpu_loop.c
> +++ b/linux-user/mips/cpu_loop.c
> @@ -425,7 +425,7 @@ static int do_break(CPUMIPSState *env,
target_siginfo_t *info,
>
> void cpu_loop(CPUMIPSState *env)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_siginfo_t info;
> int trapnr;
> abi_long ret;
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index c44cdca3b5..1fc0a4ce4b 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -336,10 +336,8 @@ static int get_physical_address (CPUMIPSState *env,
hwaddr *physical,
>
> void cpu_mips_tlb_flush(CPUMIPSState *env)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> -
> /* Flush qemu's TLB and discard all shadowed entries. */
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> env->tlb->tlb_in_use = env->tlb->nb_tlb;
> }
>
> @@ -401,7 +399,7 @@ void cpu_mips_store_status(CPUMIPSState *env,
target_ulong val)
> #if defined(TARGET_MIPS64)
> if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
> /* Access to at least one of the 64-bit segments has been
disabled */
> - tlb_flush(CPU(mips_env_get_cpu(env)));
> + tlb_flush(env_cpu(env));
> }
> #endif
> if (env->CP0_Config3 & (1 << CP0C3_MT)) {
> @@ -446,7 +444,7 @@ void cpu_mips_store_cause(CPUMIPSState *env,
target_ulong val)
> static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> int rw, int tlb_error)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int exception = 0, error_code = 0;
>
> if (rw == MMU_INST_FETCH) {
> @@ -1400,8 +1398,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
> #if !defined(CONFIG_USER_ONLY)
> void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> - CPUState *cs;
> + CPUState *cs = env_cpu(env);
> r4k_tlb_t *tlb;
> target_ulong addr;
> target_ulong end;
> @@ -1427,7 +1424,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int
idx, int use_extra)
> /* 1k pages are not supported. */
> mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
> if (tlb->V0) {
> - cs = CPU(cpu);
> addr = tlb->VPN & ~mask;
> #if defined(TARGET_MIPS64)
> if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
> @@ -1441,7 +1437,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int
idx, int use_extra)
> }
> }
> if (tlb->V1) {
> - cs = CPU(cpu);
> addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
> #if defined(TARGET_MIPS64)
> if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
> @@ -1462,7 +1457,7 @@ void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState *env,
> int error_code,
> uintptr_t pc)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
> __func__, exception, error_code);
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 0f272a5b93..0705e8c686 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -350,7 +350,7 @@ static inline hwaddr
do_translate_address(CPUMIPSState *env,
> int rw, uintptr_t
retaddr)
> {
> hwaddr paddr;
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> paddr = cpu_mips_translate_address(env, address, rw);
>
> @@ -699,7 +699,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState
*env, int *tc)
> return env;
> }
>
> - cs = CPU(mips_env_get_cpu(env));
> + cs = env_cpu(env);
> vpe_idx = tc_idx / cs->nr_threads;
> *tc = tc_idx % cs->nr_threads;
> other_cs = qemu_get_cpu(vpe_idx);
> @@ -1298,7 +1298,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env,
target_ulong arg1)
>
> void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> + MIPSCPU *cpu = env_archcpu(env);
>
> env->active_tc.CP0_TCHalt = arg1 & 0x1;
>
> @@ -1314,7 +1314,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env,
target_ulong arg1)
> {
> int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
> CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
> - MIPSCPU *other_cpu = mips_env_get_cpu(other);
> + MIPSCPU *other_cpu = env_archcpu(other);
>
> // TODO: Halt TC / Restart (if allocated+active) TC.
>
> @@ -1427,7 +1427,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env,
target_ulong arg1)
>
> void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
> tlb_flush(cs);
> @@ -1435,7 +1435,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env,
target_ulong arg1)
>
> void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
> tlb_flush(cs);
> @@ -1443,7 +1443,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env,
target_ulong arg1)
>
> void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
> tlb_flush(cs);
> @@ -1666,7 +1666,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env,
target_ulong arg1)
> /* If the ASID changes, flush qemu's TLB. */
> if ((old & env->CP0_EntryHi_ASID_mask) !=
> (val & env->CP0_EntryHi_ASID_mask)) {
> - tlb_flush(CPU(mips_env_get_cpu(env)));
> + tlb_flush(env_cpu(env));
> }
> }
>
> @@ -1686,7 +1686,6 @@ void helper_mtc0_compare(CPUMIPSState *env,
target_ulong arg1)
>
> void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> uint32_t val, old;
>
> old = env->CP0_Status;
> @@ -1706,7 +1705,7 @@ void helper_mtc0_status(CPUMIPSState *env,
target_ulong arg1)
> case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
> case MIPS_HFLAG_KM: qemu_log("\n"); break;
> default:
> - cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
> + cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
> break;
> }
> }
> @@ -2485,8 +2484,6 @@ static void debug_pre_eret(CPUMIPSState *env)
>
> static void debug_post_eret(CPUMIPSState *env)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> -
> if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
> qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
> env->active_tc.PC, env->CP0_EPC);
> @@ -2502,7 +2499,7 @@ static void debug_post_eret(CPUMIPSState *env)
> case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
> case MIPS_HFLAG_KM: qemu_log("\n"); break;
> default:
> - cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
> + cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
> break;
> }
> }
> @@ -2633,7 +2630,7 @@ void helper_pmon(CPUMIPSState *env, int function)
>
> void helper_wait(CPUMIPSState *env)
> {
> - CPUState *cs = CPU(mips_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->halted = 1;
> cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index f96c0d01ef..8043e8d398 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -29912,8 +29912,7 @@ void cpu_set_exception_base(int vp_index,
target_ulong address)
>
> void cpu_state_reset(CPUMIPSState *env)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> /* Reset registers to their default values */
> env->CP0_PRid = env->cpu_model->CP0_PRid;
> diff --git a/target/mips/translate_init.inc.c
b/target/mips/translate_init.inc.c
> index 1c2d017d36..6d145a905a 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -871,8 +871,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const
mips_def_t *def)
>
> static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> -
> env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
>
> switch (def->mmu_type) {
> @@ -889,7 +887,7 @@ static void mmu_init (CPUMIPSState *env, const
mips_def_t *def)
> case MMU_TYPE_R6000:
> case MMU_TYPE_R8000:
> default:
> - cpu_abort(CPU(cpu), "MMU type not supported\n");
> + cpu_abort(env_cpu(env), "MMU type not supported\n");
> }
> }
> #endif /* CONFIG_USER_ONLY */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 8:15 ` Aleksandar Markovic
@ 2019-05-08 14:32 ` Richard Henderson
2019-05-08 21:53 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 81+ messages in thread
From: Richard Henderson @ 2019-05-08 14:32 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: qemu-devel
On 5/8/19 1:15 AM, Aleksandar Markovic wrote:
>
> On May 8, 2019 2:19 AM, "Richard Henderson" <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
>>
>>
>>
>
> This commit message doesnˊt explain the reason for the change, and why is this
> an improvement. The underlyng reason for distingishing between env_cpu and
> env_archcpu cases is not explained too.
It's certainly explained in the preceeding patches that introduce those functions.
Are you suggesting that it is beneficial to copy-and-paste a common block
explanation into 21 commit messages for each of target/foo/?
r~
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 14:32 ` Richard Henderson
@ 2019-05-08 21:53 ` Philippe Mathieu-Daudé
2019-05-09 21:19 ` Aleksandar Markovic
2019-05-11 14:31 ` Aleksandar Markovic
2019-05-16 6:29 ` Aleksandar Markovic
2 siblings, 1 reply; 81+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-05-08 21:53 UTC (permalink / raw)
To: Richard Henderson, Aleksandar Markovic; +Cc: qemu-devel
Hi Richard, Aleksandar.
On 5/8/19 4:32 PM, Richard Henderson wrote:
> On 5/8/19 1:15 AM, Aleksandar Markovic wrote:
>>
>> On May 8, 2019 2:19 AM, "Richard Henderson" <richard.henderson@linaro.org
>> <mailto:richard.henderson@linaro.org>> wrote:
>>>
>>>
>>>
>>
>> This commit message doesnˊt explain the reason for the change, and why is this
>> an improvement. The underlyng reason for distingishing between env_cpu and
>> env_archcpu cases is not explained too.
>
> It's certainly explained in the preceeding patches that introduce those functions.
>
> Are you suggesting that it is beneficial to copy-and-paste a common block
> explanation into 21 commit messages for each of target/foo/?
*) Richard:
I tried to put myself in Aleksandar shoes. I believe Aleksandar is
worried about his MIPS maintainer duty, wanting to Ack-by this patch.
It is true that out of the context of the series, it is hard to see what
is the problem you try to solve.
You could copy/paste the explanation you used previously,
with s/$arch/mips/:
"Cleanup in the boilerplate that each target must define."
"Combined uses of CPU(mips_env_get_cpu()) were failures to use
the more proper, ENV_GET_CPU macro, now replaced by env_cpu."
Now to clearly understand this patch we still need to look at the
previous two arch-generic patches
- "cpu: Replace ENV_GET_CPU with env_cpu" and
- "cpu: Introduce env_archcpu".
Also, it is tedious to copy/paste the same explanation, but thinking of
forks or stable branch that cherry-pick not all but some commits of a
series, it might be useful.
Another guess is Aleksandar might have looked at the series cover, which
is not well explained as your v2:
https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg07635.html
I think you mistakenly copied the v1 blurb instead of the v2 one.
So at some point I can understand Aleksandar frustation.
*) Aleksandar:
This series fall under the "Overall Guest CPU cores (TCG)" section
maintained by Richard and Paolo. I think you have to see this series as
a whole to understand the benefits of it.
With the same reasoning, I believe you shouldn't worry to not give your
Ack if you don't feel comfortable.
I think Richard sent this v3 to simply address comments raised by the
previous reviewer during v1/v2, where there was some discussions: I took
it as "this is the last round before getting merged" (unless someone
object).
It is hard to make everybody happy on a such big project, with so many
areas, lines of code, people, culture, etc... I believe we all try to
give our best, neither the commiters nor the reviewers are perfect, but
slowly we help this project to improve :)
Best regards,
Phil.
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc Richard Henderson
@ 2019-05-09 17:48 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 17:48 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:10 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-defs.h | 17 ++++-------------
> accel/tcg/cputlb.c | 24 ++++++++++++------------
> 2 files changed, 16 insertions(+), 25 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 8f2a848bf5..52d150aaf1 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -127,18 +127,6 @@ typedef struct CPUIOTLBEntry {
> MemTxAttrs attrs;
> } CPUIOTLBEntry;
>
> -/**
> - * struct CPUTLBWindow
> - * @begin_ns: host time (in ns) at the beginning of the time window
> - * @max_entries: maximum number of entries observed in the window
> - *
> - * See also: tlb_mmu_resize_locked()
> - */
> -typedef struct CPUTLBWindow {
> - int64_t begin_ns;
> - size_t max_entries;
> -} CPUTLBWindow;
> -
> typedef struct CPUTLBDesc {
> /*
> * Describe a region covering all of the large pages allocated
> @@ -148,9 +136,12 @@ typedef struct CPUTLBDesc {
> */
> target_ulong large_page_addr;
> target_ulong large_page_mask;
> + /* host time (in ns) at the beginning of the time window */
> + int64_t window_begin_ns;
> + /* maximum number of entries observed in the window */
> + size_t window_max_entries;
> /* The next index to use in the tlb victim table. */
> size_t vindex;
> - CPUTLBWindow window;
> size_t n_used_entries;
> } CPUTLBDesc;
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index f2f618217d..6c7593235c 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -79,11 +79,11 @@ static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx)
> return env->tlb_mask[mmu_idx] + (1 << CPU_TLB_ENTRY_BITS);
> }
>
> -static void tlb_window_reset(CPUTLBWindow *window, int64_t ns,
> +static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
> size_t max_entries)
> {
> - window->begin_ns = ns;
> - window->max_entries = max_entries;
> + desc->window_begin_ns = ns;
> + desc->window_max_entries = max_entries;
> }
>
> static void tlb_dyn_init(CPUArchState *env)
> @@ -94,7 +94,7 @@ static void tlb_dyn_init(CPUArchState *env)
> CPUTLBDesc *desc = &env->tlb_d[i];
> size_t n_entries = 1 << CPU_TLB_DYN_DEFAULT_BITS;
>
> - tlb_window_reset(&desc->window, get_clock_realtime(), 0);
> + tlb_window_reset(desc, get_clock_realtime(), 0);
> desc->n_used_entries = 0;
> env->tlb_mask[i] = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
> env->tlb_table[i] = g_new(CPUTLBEntry, n_entries);
> @@ -151,18 +151,18 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
> int64_t now = get_clock_realtime();
> int64_t window_len_ms = 100;
> int64_t window_len_ns = window_len_ms * 1000 * 1000;
> - bool window_expired = now > desc->window.begin_ns + window_len_ns;
> + bool window_expired = now > desc->window_begin_ns + window_len_ns;
>
> - if (desc->n_used_entries > desc->window.max_entries) {
> - desc->window.max_entries = desc->n_used_entries;
> + if (desc->n_used_entries > desc->window_max_entries) {
> + desc->window_max_entries = desc->n_used_entries;
> }
> - rate = desc->window.max_entries * 100 / old_size;
> + rate = desc->window_max_entries * 100 / old_size;
>
> if (rate > 70) {
> new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
> } else if (rate < 30 && window_expired) {
> - size_t ceil = pow2ceil(desc->window.max_entries);
> - size_t expected_rate = desc->window.max_entries * 100 / ceil;
> + size_t ceil = pow2ceil(desc->window_max_entries);
> + size_t expected_rate = desc->window_max_entries * 100 / ceil;
>
> /*
> * Avoid undersizing when the max number of entries seen is just below
> @@ -182,7 +182,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
>
> if (new_size == old_size) {
> if (window_expired) {
> - tlb_window_reset(&desc->window, now, desc->n_used_entries);
> + tlb_window_reset(desc, now, desc->n_used_entries);
> }
> return;
> }
> @@ -190,7 +190,7 @@ static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx)
> g_free(env->tlb_table[mmu_idx]);
> g_free(env->iotlb[mmu_idx]);
>
> - tlb_window_reset(&desc->window, now, 0);
> + tlb_window_reset(desc, now, 0);
> /* desc->n_used_entries is cleared by the caller */
> env->tlb_mask[mmu_idx] = (new_size - 1) << CPU_TLB_ENTRY_BITS;
> env->tlb_table[mmu_idx] = g_try_new(CPUTLBEntry, new_size);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 07/39] cpu: Introduce env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 07/39] cpu: Introduce env_archcpu Richard Henderson
@ 2019-05-09 17:52 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 17:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:07 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This will replace foo_env_get_cpu with a generic definition.
> No changes to the target specific code so far.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-all.h | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 454f6d663f..c62f07b354 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
>
> int cpu_exec(CPUState *cpu);
>
> +/**
> + * env_archcpu(env)
> + * @env: The architecture environment
> + *
> + * Return the ArchCPU associated with the environment.
> + */
> +static inline ArchCPU *env_archcpu(CPUArchState *env)
> +{
> + return container_of(env, ArchCPU, env);
> +}
> +
> /**
> * env_cpu(env)
> * @env: The architecture environment
> @@ -379,8 +390,7 @@ int cpu_exec(CPUState *cpu);
> */
> static inline CPUState *env_cpu(CPUArchState *env)
> {
> - ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
> - return &arch_cpu->parent_obj;
> + return &env_archcpu(env)->parent_obj;
> }
>
> #endif /* CPU_ALL_H */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 08/39] target/alpha: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 08/39] target/alpha: Use env_cpu, env_archcpu Richard Henderson
@ 2019-05-09 17:56 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 17:56 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:07 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> With exactly one exception, most uses of alpha_env_get_cpu
> were failures to use the more proper, ENV_GET_CPU macro,
> now replaced by env_cpu.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/alpha/cpu.h | 5 -----
> linux-user/alpha/cpu_loop.c | 2 +-
> target/alpha/helper.c | 8 +++-----
> target/alpha/sys_helper.c | 8 ++++----
> 4 files changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index 2c7f75f584..53c085f691 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -273,11 +273,6 @@ struct AlphaCPU {
> QEMUTimer *alarm_timer;
> };
>
> -static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
> -{
> - return container_of(env, AlphaCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(AlphaCPU, env)
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c
> index 61992571e1..7a94eee84c 100644
> --- a/linux-user/alpha/cpu_loop.c
> +++ b/linux-user/alpha/cpu_loop.c
> @@ -23,7 +23,7 @@
>
> void cpu_loop(CPUAlphaState *env)
> {
> - CPUState *cs = CPU(alpha_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> target_siginfo_t info;
> abi_long sysret;
> diff --git a/target/alpha/helper.c b/target/alpha/helper.c
> index 7201576aae..08dfb834a5 100644
> --- a/target/alpha/helper.c
> +++ b/target/alpha/helper.c
> @@ -119,7 +119,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
> int prot_need, int mmu_idx,
> target_ulong *pphys, int *pprot)
> {
> - CPUState *cs = CPU(alpha_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_long saddr = addr;
> target_ulong phys = 0;
> target_ulong L1pte, L2pte, L3pte;
> @@ -463,8 +463,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> We expect that ENV->PC has already been updated. */
> void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
> {
> - AlphaCPU *cpu = alpha_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> env->error_code = error;
> @@ -475,8 +474,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
> void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
> int excp, int error)
> {
> - AlphaCPU *cpu = alpha_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> env->error_code = error;
> diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c
> index ac22323191..f9c34b1144 100644
> --- a/target/alpha/sys_helper.c
> +++ b/target/alpha/sys_helper.c
> @@ -44,17 +44,17 @@ uint64_t helper_load_pcc(CPUAlphaState *env)
> #ifndef CONFIG_USER_ONLY
> void helper_tbia(CPUAlphaState *env)
> {
> - tlb_flush(CPU(alpha_env_get_cpu(env)));
> + tlb_flush(env_cpu(env));
> }
>
> void helper_tbis(CPUAlphaState *env, uint64_t p)
> {
> - tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);
> + tlb_flush_page(env_cpu(env), p);
> }
>
> void helper_tb_flush(CPUAlphaState *env)
> {
> - tb_flush(CPU(alpha_env_get_cpu(env)));
> + tb_flush(env_cpu(env));
> }
>
> void helper_halt(uint64_t restart)
> @@ -78,7 +78,7 @@ uint64_t helper_get_walltime(void)
>
> void helper_set_alarm(CPUAlphaState *env, uint64_t expire)
> {
> - AlphaCPU *cpu = alpha_env_get_cpu(env);
> + AlphaCPU *cpu = env_archcpu(env);
>
> if (expire) {
> env->alarm_expire = expire;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 09/39] target/arm: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 09/39] target/arm: " Richard Henderson
@ 2019-05-09 17:57 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 17:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:16 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Combined uses of CPU(arm_env_get_cpu()) were failures to use
> the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/arm/cpu.h | 5 --
> linux-user/aarch64/cpu_loop.c | 6 +-
> linux-user/aarch64/signal.c | 4 +-
> linux-user/arm/cpu_loop.c | 2 +-
> linux-user/syscall.c | 8 +--
> target/arm/arm-semi.c | 4 +-
> target/arm/cpu64.c | 2 +-
> target/arm/helper-a64.c | 4 +-
> target/arm/helper.c | 120 +++++++++++++++++-----------------
> target/arm/op_helper.c | 21 +++---
> target/arm/translate-a64.c | 2 +-
> target/arm/translate.c | 2 +-
> target/arm/vfp_helper.c | 2 +-
> 13 files changed, 88 insertions(+), 94 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index a633a233cc..c54c67fde4 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -911,11 +911,6 @@ struct ARMCPU {
> uint32_t sve_max_vq;
> };
>
> -static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
> -{
> - return container_of(env, ARMCPU, env);
> -}
> -
> void arm_cpu_post_init(Object *obj);
>
> uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
> diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
> index d75fd9d3e2..97f355ee23 100644
> --- a/linux-user/aarch64/cpu_loop.c
> +++ b/linux-user/aarch64/cpu_loop.c
> @@ -72,7 +72,7 @@
> /* AArch64 main loop */
> void cpu_loop(CPUARMState *env)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> abi_long ret;
> target_siginfo_t info;
> @@ -167,8 +167,8 @@ void arm_init_pauth_key(ARMPACKey *key)
>
> void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + ARMCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> struct image_info *info = ts->info;
> int i;
> diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
> index f84a9cf28a..cd521ee42d 100644
> --- a/linux-user/aarch64/signal.c
> +++ b/linux-user/aarch64/signal.c
> @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env,
> break;
>
> case TARGET_SVE_MAGIC:
> - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) {
> + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
> vq = (env->vfp.zcr_el[1] & 0xf) + 1;
> sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
> if (!sve && size == sve_size) {
> @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
> &layout);
>
> /* SVE state needs saving only if it exists. */
> - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) {
> + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
> vq = (env->vfp.zcr_el[1] & 0xf) + 1;
> sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
> sve_ofs = alloc_sigframe_space(sve_size, &layout);
> diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
> index b7e7a6323c..ece4cf335e 100644
> --- a/linux-user/arm/cpu_loop.c
> +++ b/linux-user/arm/cpu_loop.c
> @@ -206,7 +206,7 @@ do_kernel_trap(CPUARMState *env)
>
> void cpu_loop(CPUARMState *env)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> unsigned int n, insn;
> target_siginfo_t info;
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 9f110a7581..eb7fd9a1bf 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -9683,10 +9683,10 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
> * even though the current architectural maximum is VQ=16.
> */
> ret = -TARGET_EINVAL;
> - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env))
> + if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env))
> && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
> CPUARMState *env = cpu_env;
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint32_t vq, old_vq;
>
> old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
> @@ -9703,7 +9703,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
> case TARGET_PR_SVE_GET_VL:
> ret = -TARGET_EINVAL;
> {
> - ARMCPU *cpu = arm_env_get_cpu(cpu_env);
> + ARMCPU *cpu = env_archcpu(cpu_env);
> if (cpu_isar_feature(aa64_sve, cpu)) {
> ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
> }
> @@ -9712,7 +9712,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
> case TARGET_PR_PAC_RESET_KEYS:
> {
> CPUARMState *env = cpu_env;
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (arg3 || arg4 || arg5) {
> return -TARGET_EINVAL;
> diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
> index 8b5fd7bc6e..e998b014be 100644
> --- a/target/arm/arm-semi.c
> +++ b/target/arm/arm-semi.c
> @@ -242,8 +242,8 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb,
>
> target_ulong do_arm_semihosting(CPUARMState *env)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + ARMCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
> target_ulong args;
> target_ulong arg0, arg1, arg2, arg3;
> char * s;
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 228906f267..1150cec22d 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -44,7 +44,7 @@ static inline void unset_feature(CPUARMState *env, int feature)
> #ifndef CONFIG_USER_ONLY
> static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> /* Number of cores is in [25:24]; otherwise we RAZ */
> return (cpu->core_count - 1) << 24;
> diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
> index 796ef34b55..44e45a8037 100644
> --- a/target/arm/helper-a64.c
> +++ b/target/arm/helper-a64.c
> @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
> }
>
> qemu_mutex_lock_iothread();
> - arm_call_pre_el_change_hook(arm_env_get_cpu(env));
> + arm_call_pre_el_change_hook(env_archcpu(env));
> qemu_mutex_unlock_iothread();
>
> if (!return_to_aa64) {
> @@ -1047,7 +1047,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
> aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
>
> qemu_mutex_lock_iothread();
> - arm_call_el_change_hook(arm_env_get_cpu(env));
> + arm_call_el_change_hook(env_archcpu(env));
> qemu_mutex_unlock_iothread();
>
> return;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 4c57c0ddd4..082ce89dcf 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -224,7 +224,7 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
>
> static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> const ARMCPRegInfo *ri;
> uint32_t key;
>
> @@ -522,7 +522,7 @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
>
> static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> raw_write(env, ri, value);
> tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
> @@ -530,7 +530,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
>
> static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (raw_read(env, ri) != value) {
> /* Unlike real hardware the qemu TLB uses virtual addresses,
> @@ -544,7 +544,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
> && !extended_addresses_enabled(env)) {
> @@ -605,7 +605,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate all (TLBIALL) */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (tlb_force_broadcast(env)) {
> tlbiall_is_write(env, NULL, value);
> @@ -619,7 +619,7 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (tlb_force_broadcast(env)) {
> tlbimva_is_write(env, NULL, value);
> @@ -633,7 +633,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate by ASID (TLBIASID) */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (tlb_force_broadcast(env)) {
> tlbiasid_is_write(env, NULL, value);
> @@ -647,7 +647,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (tlb_force_broadcast(env)) {
> tlbimvaa_is_write(env, NULL, value);
> @@ -1327,7 +1327,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
>
> static void pmu_update_irq(CPUARMState *env)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
> (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
> }
> @@ -1382,7 +1382,7 @@ static void pmccntr_op_finish(CPUARMState *env)
> if (overflow_in > 0) {
> int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> overflow_in;
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
> }
> #endif
> @@ -1431,7 +1431,7 @@ static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
> if (overflow_in > 0) {
> int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> overflow_in;
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
> }
> #endif
> @@ -1839,7 +1839,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> /* Begin with base v8.0 state. */
> uint32_t valid_mask = 0x3fff;
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (arm_el_is_aa64(env, 3)) {
> value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
> @@ -1876,7 +1876,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
>
> static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
> * bank
> @@ -2426,7 +2426,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
> static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
> int timeridx)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> timer_del(cpu->gt_timer[timeridx]);
> }
> @@ -2447,7 +2447,7 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
> {
> trace_arm_gt_cval_write(timeridx, value);
> env->cp15.c14_timer[timeridx].cval = value;
> - gt_recalc_timer(arm_env_get_cpu(env), timeridx);
> + gt_recalc_timer(env_archcpu(env), timeridx);
> }
>
> static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -2468,14 +2468,14 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
> trace_arm_gt_tval_write(timeridx, value);
> env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
> sextract64(value, 0, 32);
> - gt_recalc_timer(arm_env_get_cpu(env), timeridx);
> + gt_recalc_timer(env_archcpu(env), timeridx);
> }
>
> static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> int timeridx,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
>
> trace_arm_gt_ctl_write(timeridx, value);
> @@ -2553,7 +2553,7 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> trace_arm_gt_cntvoff_write(value);
> raw_write(env, ri, value);
> @@ -3186,7 +3186,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
> static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
>
> if (!u32p) {
> @@ -3201,7 +3201,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint32_t nrgs = cpu->pmsav7_dregion;
>
> if (value >= nrgs) {
> @@ -3329,7 +3329,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> TCR *tcr = raw_ptr(env, ri);
>
> if (arm_feature(env, ARM_FEATURE_LPAE)) {
> @@ -3358,7 +3358,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> TCR *tcr = raw_ptr(env, ri);
>
> /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
> @@ -3372,7 +3372,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
> if (cpreg_field_is_64bit(ri) &&
> extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> tlb_flush(CPU(cpu));
> }
> raw_write(env, ri, value);
> @@ -3381,7 +3381,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
>
> /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
> @@ -3471,7 +3471,7 @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Wait-for-interrupt (deprecated) */
> - cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
> + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
> }
>
> static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3624,7 +3624,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
>
> static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> unsigned int cur_el = arm_current_el(env);
> bool secure = arm_is_secure(env);
>
> @@ -3636,7 +3636,7 @@ static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
>
> static uint64_t mpidr_read_val(CPUARMState *env)
> {
> - ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
> + ARMCPU *cpu = env_archcpu(env);
> uint64_t mpidr = cpu->mp_affinity;
>
> if (arm_feature(env, ARM_FEATURE_V7MP)) {
> @@ -3789,7 +3789,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * stage 2 translations, whereas most other scopes only invalidate
> * stage 1 translations.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
>
> if (arm_is_secure_below_el3(env)) {
> @@ -3813,7 +3813,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
>
> tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
> @@ -3822,7 +3822,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
>
> tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
> @@ -3878,7 +3878,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * Currently handles both VAE2 and VALE2, since we don't support
> * flush-last-level-only.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> @@ -3892,7 +3892,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * Currently handles both VAE3 and VALE3, since we don't support
> * flush-last-level-only.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> @@ -3902,7 +3902,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
> bool sec = arm_is_secure_below_el3(env);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
> @@ -3926,7 +3926,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * since we don't support flush-for-specific-ASID-only or
> * flush-last-level-only.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> @@ -3975,7 +3975,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> * translation information.
> * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
> uint64_t pageaddr;
>
> @@ -4018,7 +4018,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
>
> static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int dzp_bit = 1 << 4;
>
> /* DZP indicates whether DC ZVA access is allowed */
> @@ -4053,7 +4053,7 @@ static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
> static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (raw_read(env, ri) == value) {
> /* Skip the TLB flush if nothing actually changed; Linux likes
> @@ -4545,7 +4545,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
>
> static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint64_t valid_mask = HCR_MASK;
>
> if (arm_feature(env, ARM_FEATURE_EL3)) {
> @@ -5212,7 +5212,7 @@ int sve_exception_el(CPUARMState *env, int el)
> */
> uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint32_t zcr_len = cpu->sve_max_vq - 1;
>
> if (el <= 1) {
> @@ -5380,7 +5380,7 @@ void hw_watchpoint_update_all(ARMCPU *cpu)
> static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int i = ri->crm;
>
> /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
> @@ -5396,7 +5396,7 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int i = ri->crm;
>
> raw_write(env, ri, value);
> @@ -5498,7 +5498,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu)
> static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int i = ri->crm;
>
> raw_write(env, ri, value);
> @@ -5508,7 +5508,7 @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int i = ri->crm;
>
> /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
> @@ -5604,7 +5604,7 @@ static void define_debug_regs(ARMCPU *cpu)
> */
> static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint64_t pfr1 = cpu->id_pfr1;
>
> if (env->gicv3state) {
> @@ -5615,7 +5615,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
>
> static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint64_t pfr0 = cpu->isar.id_aa64pfr0;
>
> if (env->gicv3state) {
> @@ -7353,14 +7353,14 @@ uint32_t HELPER(rbit)(uint32_t x)
> /* These should probably raise undefined insn exceptions. */
> void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
> }
>
> uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
> return 0;
> @@ -7420,7 +7420,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
>
> static void switch_mode(CPUARMState *env, int mode)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (mode != ARM_CPU_MODE_USR) {
> cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> @@ -7763,7 +7763,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
> * PreserveFPState() pseudocode.
> * We may throw an exception if the stacking fails.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
> bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK);
> bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK);
> @@ -10865,7 +10865,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
> target_ulong *page_size,
> ARMMMUFaultInfo *fi)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int level = 1;
> uint32_t table;
> uint32_t desc;
> @@ -10986,7 +10986,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
> hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
> target_ulong *page_size, ARMMMUFaultInfo *fi)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int level = 1;
> uint32_t table;
> uint32_t desc;
> @@ -11371,7 +11371,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
> target_ulong *page_size_ptr,
> ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
> /* Read an LPAE long-descriptor translation table. */
> ARMFaultType fault_type = ARMFault_Translation;
> @@ -11729,7 +11729,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
> target_ulong *page_size,
> ARMMMUFaultInfo *fi)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int n;
> bool is_user = regime_is_user(env, mmu_idx);
>
> @@ -11933,7 +11933,7 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
> * pseudocode SecurityCheck() function.
> * We assume the caller has zero-initialized *sattrs.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int r;
> bool idau_exempt = false, idau_ns = true, idau_nsc = true;
> int idau_region = IREGION_NOTVALID;
> @@ -12046,7 +12046,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
> * We set is_subpage to true if the region hit doesn't cover the
> * entire TARGET_PAGE the address is within.
> */
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> bool is_user = regime_is_user(env, mmu_idx);
> uint32_t secure = regime_is_secure(env, mmu_idx);
> int n;
> @@ -12860,7 +12860,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
> limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
>
> if (val < limit) {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cpu_restore_state(cs, GETPC(), true);
> raise_exception(env, EXCP_STKOF, 0, 1);
> @@ -13088,7 +13088,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
> * alignment faults or any memory attribute handling).
> */
>
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint64_t blocklen = 4 << cpu->dcz_blocksize;
> uint64_t vaddr = vaddr_in & ~(blocklen - 1);
>
> @@ -13585,7 +13585,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> uint32_t flags = 0;
>
> if (is_a64(env)) {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint64_t sctlr;
>
> *pc = env->pc;
> @@ -13758,7 +13758,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
> uint64_t pmask;
>
> assert(vq >= 1 && vq <= ARM_MAX_VQ);
> - assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
> + assert(vq <= env_archcpu(env)->sve_max_vq);
>
> /* Zap the high bits of the zregs. */
> for (i = 0; i < 32; i++) {
> @@ -13784,7 +13784,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
> void aarch64_sve_change_el(CPUARMState *env, int old_el,
> int new_el, bool el0_a64)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int old_len, new_len;
> bool old_a64, new_a64;
>
> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
> index 8698b4dc83..5af8a1f408 100644
> --- a/target/arm/op_helper.c
> +++ b/target/arm/op_helper.c
> @@ -31,7 +31,7 @@
> static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp,
> uint32_t syndrome, uint32_t target_el)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
> /*
> @@ -245,7 +245,7 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue)
> * raising an exception if the limit is breached.
> */
> if (newvalue < v7m_sp_limit(env)) {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> /*
> * Stack limit exceptions are a rare case, so rather than syncing
> @@ -448,7 +448,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
>
> void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int target_el = check_wfx_trap(env, false);
>
> if (cpu_has_work(cs)) {
> @@ -483,8 +483,7 @@ void HELPER(wfe)(CPUARMState *env)
>
> void HELPER(yield)(CPUARMState *env)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> /* This is a non-trappable hint instruction that generally indicates
> * that the guest is currently busy-looping. Yield control back to the
> @@ -502,7 +501,7 @@ void HELPER(yield)(CPUARMState *env)
> */
> void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
> {
> - CPUState *cs = CPU(arm_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> assert(excp_is_internal(excp));
> cs->exception_index = excp;
> @@ -545,7 +544,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
> void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
> {
> qemu_mutex_lock_iothread();
> - arm_call_pre_el_change_hook(arm_env_get_cpu(env));
> + arm_call_pre_el_change_hook(env_archcpu(env));
> qemu_mutex_unlock_iothread();
>
> cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
> @@ -558,7 +557,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
> env->regs[15] &= (env->thumb ? ~1 : ~3);
>
> qemu_mutex_lock_iothread();
> - arm_call_el_change_hook(arm_env_get_cpu(env));
> + arm_call_el_change_hook(env_archcpu(env));
> qemu_mutex_unlock_iothread();
> }
>
> @@ -863,7 +862,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
>
> void HELPER(pre_hvc)(CPUARMState *env)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int cur_el = arm_current_el(env);
> /* FIXME: Use actual secure state. */
> bool secure = false;
> @@ -903,7 +902,7 @@ void HELPER(pre_hvc)(CPUARMState *env)
>
> void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> int cur_el = arm_current_el(env);
> bool secure = arm_is_secure(env);
> bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
> @@ -1177,7 +1176,7 @@ static bool check_breakpoints(ARMCPU *cpu)
>
> void HELPER(check_breakpoints)(CPUARMState *env)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
>
> if (check_breakpoints(cpu)) {
> HELPER(exception_internal(env, EXCP_DEBUG));
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index d0fefa798e..f998f1c629 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -14318,7 +14318,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
> {
> DisasContext *dc = container_of(dcbase, DisasContext, base);
> CPUARMState *env = cpu->env_ptr;
> - ARMCPU *arm_cpu = arm_env_get_cpu(env);
> + ARMCPU *arm_cpu = env_archcpu(env);
> uint32_t tb_flags = dc->base.tb->flags;
> int bound, core_mmu_idx;
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 10bc53f91c..2170f0f3cc 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -13380,7 +13380,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *dc = container_of(dcbase, DisasContext, base);
> CPUARMState *env = cs->env_ptr;
> - ARMCPU *cpu = arm_env_get_cpu(env);
> + ARMCPU *cpu = env_archcpu(env);
> uint32_t tb_flags = dc->base.tb->flags;
> uint32_t condexec, core_mmu_idx;
>
> diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
> index 7a46d99148..d3e83b627b 100644
> --- a/target/arm/vfp_helper.c
> +++ b/target/arm/vfp_helper.c
> @@ -101,7 +101,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
> uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
>
> /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
> - if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
> + if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {
> val &= ~FPCR_FZ16;
> }
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c Richard Henderson
2019-05-08 6:26 ` Philippe Mathieu-Daudé
@ 2019-05-09 18:01 ` Alistair Francis
1 sibling, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Fix all of the coding style errors in this file at once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/cris/mmu.c | 479 +++++++++++++++++++++++-----------------------
> 1 file changed, 237 insertions(+), 242 deletions(-)
>
> diff --git a/target/cris/mmu.c b/target/cris/mmu.c
> index b8db908823..9cb73bbfec 100644
> --- a/target/cris/mmu.c
> +++ b/target/cris/mmu.c
> @@ -33,96 +33,99 @@
>
> void cris_mmu_init(CPUCRISState *env)
> {
> - env->mmu_rand_lfsr = 0xcccc;
> + env->mmu_rand_lfsr = 0xcccc;
> }
>
> #define SR_POLYNOM 0x8805
> static inline unsigned int compute_polynom(unsigned int sr)
> {
> - unsigned int i;
> - unsigned int f;
> + unsigned int i;
> + unsigned int f;
>
> - f = 0;
> - for (i = 0; i < 16; i++)
> - f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
> + f = 0;
> + for (i = 0; i < 16; i++) {
> + f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
> + }
>
> - return f;
> + return f;
> }
>
> static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
> {
> - unsigned int f;
> + unsigned int f;
>
> - /* Update lfsr at every fault. */
> - f = compute_polynom(env->mmu_rand_lfsr);
> - env->mmu_rand_lfsr >>= 1;
> - env->mmu_rand_lfsr |= (f << 15);
> - env->mmu_rand_lfsr &= 0xffff;
> + /* Update lfsr at every fault. */
> + f = compute_polynom(env->mmu_rand_lfsr);
> + env->mmu_rand_lfsr >>= 1;
> + env->mmu_rand_lfsr |= (f << 15);
> + env->mmu_rand_lfsr &= 0xffff;
> }
>
> static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
> {
> - return (rw_gc_cfg & 12) != 0;
> + return (rw_gc_cfg & 12) != 0;
> }
>
> static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
> {
> - return (1 << seg) & rw_mm_cfg;
> + return (1 << seg) & rw_mm_cfg;
> }
>
> static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
> {
> - uint32_t base;
> - int i;
> + uint32_t base;
> + int i;
>
> - if (seg < 8)
> - base = env->sregs[SFR_RW_MM_KBASE_LO];
> - else
> - base = env->sregs[SFR_RW_MM_KBASE_HI];
> + if (seg < 8) {
> + base = env->sregs[SFR_RW_MM_KBASE_LO];
> + } else {
> + base = env->sregs[SFR_RW_MM_KBASE_HI];
> + }
>
> - i = seg & 7;
> - base >>= i * 4;
> - base &= 15;
> + i = seg & 7;
> + base >>= i * 4;
> + base &= 15;
>
> - base <<= 28;
> - return base;
> + base <<= 28;
> + return base;
> }
> -/* Used by the tlb decoder. */
> -#define EXTRACT_FIELD(src, start, end) \
> - (((src) >> start) & ((1 << (end - start + 1)) - 1))
>
> -static inline void set_field(uint32_t *dst, unsigned int val,
> +/* Used by the tlb decoder. */
> +#define EXTRACT_FIELD(src, start, end) \
> + (((src) >> start) & ((1 << (end - start + 1)) - 1))
> +
> +static inline void set_field(uint32_t *dst, unsigned int val,
> unsigned int offset, unsigned int width)
> {
> - uint32_t mask;
> + uint32_t mask;
>
> - mask = (1 << width) - 1;
> - mask <<= offset;
> - val <<= offset;
> + mask = (1 << width) - 1;
> + mask <<= offset;
> + val <<= offset;
>
> - val &= mask;
> - *dst &= ~(mask);
> - *dst |= val;
> + val &= mask;
> + *dst &= ~(mask);
> + *dst |= val;
> }
>
> #ifdef DEBUG
> static void dump_tlb(CPUCRISState *env, int mmu)
> {
> - int set;
> - int idx;
> - uint32_t hi, lo, tlb_vpn, tlb_pfn;
> + int set;
> + int idx;
> + uint32_t hi, lo, tlb_vpn, tlb_pfn;
>
> - for (set = 0; set < 4; set++) {
> - for (idx = 0; idx < 16; idx++) {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> - tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> - tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> + for (set = 0; set < 4; set++) {
> + for (idx = 0; idx < 16; idx++) {
> + lo = env->tlbsets[mmu][set][idx].lo;
> + hi = env->tlbsets[mmu][set][idx].hi;
> + tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> + tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
>
> - printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
> - set, idx, hi, lo, tlb_vpn, tlb_pfn);
> - }
> - }
> + printf("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
> + set, idx, hi, lo, tlb_vpn, tlb_pfn);
> + }
> + }
> }
> #endif
>
> @@ -131,232 +134,224 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
> CPUCRISState *env, uint32_t vaddr,
> int rw, int usermode, int debug)
> {
> - unsigned int vpage;
> - unsigned int idx;
> - uint32_t pid, lo, hi;
> - uint32_t tlb_vpn, tlb_pfn = 0;
> - int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
> - int cfg_v, cfg_k, cfg_w, cfg_x;
> - int set, match = 0;
> - uint32_t r_cause;
> - uint32_t r_cfg;
> - int rwcause;
> - int mmu = 1; /* Data mmu is default. */
> - int vect_base;
> + unsigned int vpage;
> + unsigned int idx;
> + uint32_t pid, lo, hi;
> + uint32_t tlb_vpn, tlb_pfn = 0;
> + int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
> + int cfg_v, cfg_k, cfg_w, cfg_x;
> + int set, match = 0;
> + uint32_t r_cause;
> + uint32_t r_cfg;
> + int rwcause;
> + int mmu = 1; /* Data mmu is default. */
> + int vect_base;
>
> - r_cause = env->sregs[SFR_R_MM_CAUSE];
> - r_cfg = env->sregs[SFR_RW_MM_CFG];
> - pid = env->pregs[PR_PID] & 0xff;
> + r_cause = env->sregs[SFR_R_MM_CAUSE];
> + r_cfg = env->sregs[SFR_RW_MM_CFG];
> + pid = env->pregs[PR_PID] & 0xff;
>
> - switch (rw) {
> - case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
> - case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
> - default:
> - case 0: rwcause = CRIS_MMU_ERR_READ; break;
> - }
> + switch (rw) {
> + case 2:
> + rwcause = CRIS_MMU_ERR_EXEC;
> + mmu = 0;
> + break;
> + case 1:
> + rwcause = CRIS_MMU_ERR_WRITE;
> + break;
> + default:
> + case 0:
> + rwcause = CRIS_MMU_ERR_READ;
> + break;
> + }
>
> - /* I exception vectors 4 - 7, D 8 - 11. */
> - vect_base = (mmu + 1) * 4;
> + /* I exception vectors 4 - 7, D 8 - 11. */
> + vect_base = (mmu + 1) * 4;
>
> - vpage = vaddr >> 13;
> + vpage = vaddr >> 13;
>
> - /* We know the index which to check on each set.
> - Scan both I and D. */
> -#if 0
> - for (set = 0; set < 4; set++) {
> - for (idx = 0; idx < 16; idx++) {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> - tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> - tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> + /*
> + * We know the index which to check on each set.
> + * Scan both I and D.
> + */
> + idx = vpage & 15;
> + for (set = 0; set < 4; set++) {
> + lo = env->tlbsets[mmu][set][idx].lo;
> + hi = env->tlbsets[mmu][set][idx].hi;
>
> - printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
> - set, idx, hi, lo, tlb_vpn, tlb_pfn);
> - }
> - }
> -#endif
> + tlb_vpn = hi >> 13;
> + tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> + tlb_g = EXTRACT_FIELD(lo, 4, 4);
>
> - idx = vpage & 15;
> - for (set = 0; set < 4; set++)
> - {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> + D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
> + mmu, set, idx, tlb_vpn, vpage, lo, hi);
> + if ((tlb_g || (tlb_pid == pid)) && tlb_vpn == vpage) {
> + match = 1;
> + break;
> + }
> + }
>
> - tlb_vpn = hi >> 13;
> - tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> - tlb_g = EXTRACT_FIELD(lo, 4, 4);
> + res->bf_vec = vect_base;
> + if (match) {
> + cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
> + cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
> + cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
> + cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
>
> - D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
> - mmu, set, idx, tlb_vpn, vpage, lo, hi);
> - if ((tlb_g || (tlb_pid == pid))
> - && tlb_vpn == vpage) {
> - match = 1;
> - break;
> - }
> - }
> + tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> + tlb_v = EXTRACT_FIELD(lo, 3, 3);
> + tlb_k = EXTRACT_FIELD(lo, 2, 2);
> + tlb_w = EXTRACT_FIELD(lo, 1, 1);
> + tlb_x = EXTRACT_FIELD(lo, 0, 0);
>
> - res->bf_vec = vect_base;
> - if (match) {
> - cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
> - cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
> - cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
> - cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
> + /*
> + * set_exception_vector(0x04, i_mmu_refill);
> + * set_exception_vector(0x05, i_mmu_invalid);
> + * set_exception_vector(0x06, i_mmu_access);
> + * set_exception_vector(0x07, i_mmu_execute);
> + * set_exception_vector(0x08, d_mmu_refill);
> + * set_exception_vector(0x09, d_mmu_invalid);
> + * set_exception_vector(0x0a, d_mmu_access);
> + * set_exception_vector(0x0b, d_mmu_write);
> + */
> + if (cfg_k && tlb_k && usermode) {
> + D(printf("tlb: kernel protected %x lo=%x pc=%x\n",
> + vaddr, lo, env->pc));
> + match = 0;
> + res->bf_vec = vect_base + 2;
> + } else if (rw == 1 && cfg_w && !tlb_w) {
> + D(printf("tlb: write protected %x lo=%x pc=%x\n",
> + vaddr, lo, env->pc));
> + match = 0;
> + /* write accesses never go through the I mmu. */
> + res->bf_vec = vect_base + 3;
> + } else if (rw == 2 && cfg_x && !tlb_x) {
> + D(printf("tlb: exec protected %x lo=%x pc=%x\n",
> + vaddr, lo, env->pc));
> + match = 0;
> + res->bf_vec = vect_base + 3;
> + } else if (cfg_v && !tlb_v) {
> + D(printf("tlb: invalid %x\n", vaddr));
> + match = 0;
> + res->bf_vec = vect_base + 1;
> + }
>
> - tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
> - tlb_v = EXTRACT_FIELD(lo, 3, 3);
> - tlb_k = EXTRACT_FIELD(lo, 2, 2);
> - tlb_w = EXTRACT_FIELD(lo, 1, 1);
> - tlb_x = EXTRACT_FIELD(lo, 0, 0);
> + res->prot = 0;
> + if (match) {
> + res->prot |= PAGE_READ;
> + if (tlb_w) {
> + res->prot |= PAGE_WRITE;
> + }
> + if (mmu == 0 && (cfg_x || tlb_x)) {
> + res->prot |= PAGE_EXEC;
> + }
> + } else {
> + D(dump_tlb(env, mmu));
> + }
> + } else {
> + /* If refill, provide a randomized set. */
> + set = env->mmu_rand_lfsr & 3;
> + }
>
> - /*
> - set_exception_vector(0x04, i_mmu_refill);
> - set_exception_vector(0x05, i_mmu_invalid);
> - set_exception_vector(0x06, i_mmu_access);
> - set_exception_vector(0x07, i_mmu_execute);
> - set_exception_vector(0x08, d_mmu_refill);
> - set_exception_vector(0x09, d_mmu_invalid);
> - set_exception_vector(0x0a, d_mmu_access);
> - set_exception_vector(0x0b, d_mmu_write);
> - */
> - if (cfg_k && tlb_k && usermode) {
> - D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
> - vaddr, lo, env->pc));
> - match = 0;
> - res->bf_vec = vect_base + 2;
> - } else if (rw == 1 && cfg_w && !tlb_w) {
> - D(printf ("tlb: write protected %x lo=%x pc=%x\n",
> - vaddr, lo, env->pc));
> - match = 0;
> - /* write accesses never go through the I mmu. */
> - res->bf_vec = vect_base + 3;
> - } else if (rw == 2 && cfg_x && !tlb_x) {
> - D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
> - vaddr, lo, env->pc));
> - match = 0;
> - res->bf_vec = vect_base + 3;
> - } else if (cfg_v && !tlb_v) {
> - D(printf ("tlb: invalid %x\n", vaddr));
> - match = 0;
> - res->bf_vec = vect_base + 1;
> - }
> + if (!match && !debug) {
> + cris_mmu_update_rand_lfsr(env);
>
> - res->prot = 0;
> - if (match) {
> - res->prot |= PAGE_READ;
> - if (tlb_w)
> - res->prot |= PAGE_WRITE;
> - if (mmu == 0 && (cfg_x || tlb_x))
> - res->prot |= PAGE_EXEC;
> - }
> - else
> - D(dump_tlb(env, mmu));
> - } else {
> - /* If refill, provide a randomized set. */
> - set = env->mmu_rand_lfsr & 3;
> - }
> + /* Compute index. */
> + idx = vpage & 15;
>
> - if (!match && !debug) {
> - cris_mmu_update_rand_lfsr(env);
> + /* Update RW_MM_TLB_SEL. */
> + env->sregs[SFR_RW_MM_TLB_SEL] = 0;
> + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
> + set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
>
> - /* Compute index. */
> - idx = vpage & 15;
> + /* Update RW_MM_CAUSE. */
> + set_field(&r_cause, rwcause, 8, 2);
> + set_field(&r_cause, vpage, 13, 19);
> + set_field(&r_cause, pid, 0, 8);
> + env->sregs[SFR_R_MM_CAUSE] = r_cause;
> + D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
> + }
>
> - /* Update RW_MM_TLB_SEL. */
> - env->sregs[SFR_RW_MM_TLB_SEL] = 0;
> - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
> - set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
> + D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
> + " %x cause=%x sel=%x sp=%x %x %x\n",
> + __func__, rw, match, env->pc,
> + vaddr, vpage,
> + tlb_vpn, tlb_pfn, tlb_pid,
> + pid,
> + r_cause,
> + env->sregs[SFR_RW_MM_TLB_SEL],
> + env->regs[R_SP], env->pregs[PR_USP], env->ksp));
>
> - /* Update RW_MM_CAUSE. */
> - set_field(&r_cause, rwcause, 8, 2);
> - set_field(&r_cause, vpage, 13, 19);
> - set_field(&r_cause, pid, 0, 8);
> - env->sregs[SFR_R_MM_CAUSE] = r_cause;
> - D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
> - }
> -
> - D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
> - " %x cause=%x sel=%x sp=%x %x %x\n",
> - __func__, rw, match, env->pc,
> - vaddr, vpage,
> - tlb_vpn, tlb_pfn, tlb_pid,
> - pid,
> - r_cause,
> - env->sregs[SFR_RW_MM_TLB_SEL],
> - env->regs[R_SP], env->pregs[PR_USP], env->ksp));
> -
> - res->phy = tlb_pfn << TARGET_PAGE_BITS;
> - return !match;
> + res->phy = tlb_pfn << TARGET_PAGE_BITS;
> + return !match;
> }
>
> void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> CRISCPU *cpu = cris_env_get_cpu(env);
> - target_ulong vaddr;
> - unsigned int idx;
> - uint32_t lo, hi;
> - uint32_t tlb_vpn;
> - int tlb_pid, tlb_g, tlb_v;
> - unsigned int set;
> - unsigned int mmu;
> + target_ulong vaddr;
> + unsigned int idx;
> + uint32_t lo, hi;
> + uint32_t tlb_vpn;
> + int tlb_pid, tlb_g, tlb_v;
> + unsigned int set;
> + unsigned int mmu;
>
> - pid &= 0xff;
> - for (mmu = 0; mmu < 2; mmu++) {
> - for (set = 0; set < 4; set++)
> - {
> - for (idx = 0; idx < 16; idx++) {
> - lo = env->tlbsets[mmu][set][idx].lo;
> - hi = env->tlbsets[mmu][set][idx].hi;
> -
> - tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> - tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> - tlb_g = EXTRACT_FIELD(lo, 4, 4);
> - tlb_v = EXTRACT_FIELD(lo, 3, 3);
> + pid &= 0xff;
> + for (mmu = 0; mmu < 2; mmu++) {
> + for (set = 0; set < 4; set++) {
> + for (idx = 0; idx < 16; idx++) {
> + lo = env->tlbsets[mmu][set][idx].lo;
> + hi = env->tlbsets[mmu][set][idx].hi;
>
> - if (tlb_v && !tlb_g && (tlb_pid == pid)) {
> - vaddr = tlb_vpn << TARGET_PAGE_BITS;
> - D_LOG("flush pid=%x vaddr=%x\n",
> - pid, vaddr);
> + tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
> + tlb_pid = EXTRACT_FIELD(hi, 0, 7);
> + tlb_g = EXTRACT_FIELD(lo, 4, 4);
> + tlb_v = EXTRACT_FIELD(lo, 3, 3);
> +
> + if (tlb_v && !tlb_g && (tlb_pid == pid)) {
> + vaddr = tlb_vpn << TARGET_PAGE_BITS;
> + D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
> tlb_flush_page(CPU(cpu), vaddr);
> - }
> - }
> - }
> - }
> + }
> + }
> + }
> + }
> }
>
> int cris_mmu_translate(struct cris_mmu_result *res,
> CPUCRISState *env, uint32_t vaddr,
> int rw, int mmu_idx, int debug)
> {
> - int seg;
> - int miss = 0;
> - int is_user = mmu_idx == MMU_USER_IDX;
> - uint32_t old_srs;
> + int seg;
> + int miss = 0;
> + int is_user = mmu_idx == MMU_USER_IDX;
> + uint32_t old_srs;
>
> - old_srs= env->pregs[PR_SRS];
> + old_srs = env->pregs[PR_SRS];
>
> - /* rw == 2 means exec, map the access to the insn mmu. */
> - env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
> + /* rw == 2 means exec, map the access to the insn mmu. */
> + env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
>
> - if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
> - res->phy = vaddr;
> - res->prot = PAGE_BITS;
> - goto done;
> - }
> + if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
> + res->phy = vaddr;
> + res->prot = PAGE_BITS;
> + goto done;
> + }
>
> - seg = vaddr >> 28;
> - if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
> - {
> - uint32_t base;
> + seg = vaddr >> 28;
> + if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
> + uint32_t base;
>
> - miss = 0;
> - base = cris_mmu_translate_seg(env, seg);
> - res->phy = base | (0x0fffffff & vaddr);
> - res->prot = PAGE_BITS;
> - } else {
> - miss = cris_mmu_translate_page(res, env, vaddr, rw,
> - is_user, debug);
> - }
> - done:
> - env->pregs[PR_SRS] = old_srs;
> - return miss;
> + miss = 0;
> + base = cris_mmu_translate_seg(env, seg);
> + res->phy = base | (0x0fffffff & vaddr);
> + res->prot = PAGE_BITS;
> + } else {
> + miss = cris_mmu_translate_page(res, env, vaddr, rw,
> + is_user, debug);
> + }
> + done:
> + env->pregs[PR_SRS] = old_srs;
> + return miss;
> }
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c Richard Henderson
2019-05-08 6:28 ` Philippe Mathieu-Daudé
@ 2019-05-09 18:03 ` Alistair Francis
1 sibling, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Fix all of the coding style errors in this file at once.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/cris/op_helper.c | 817 +++++++++++++++++++---------------------
> 1 file changed, 398 insertions(+), 419 deletions(-)
>
> diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
> index 0ee3a3117b..d4479167a5 100644
> --- a/target/cris/op_helper.c
> +++ b/target/cris/op_helper.c
> @@ -76,9 +76,10 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index)
> void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> #if !defined(CONFIG_USER_ONLY)
> - pid &= 0xff;
> - if (pid != (env->pregs[PR_PID] & 0xff))
> - cris_mmu_flush_pid(env, env->pregs[PR_PID]);
> + pid &= 0xff;
> + if (pid != (env->pregs[PR_PID] & 0xff)) {
> + cris_mmu_flush_pid(env, env->pregs[PR_PID]);
> + }
> #endif
> }
>
> @@ -94,541 +95,519 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> }
>
> /* Used by the tlb decoder. */
> -#define EXTRACT_FIELD(src, start, end) \
> - (((src) >> start) & ((1 << (end - start + 1)) - 1))
> +#define EXTRACT_FIELD(src, start, end) \
> + (((src) >> start) & ((1 << (end - start + 1)) - 1))
>
> void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> {
> #if !defined(CONFIG_USER_ONLY)
> CRISCPU *cpu = cris_env_get_cpu(env);
> #endif
> - uint32_t srs;
> - srs = env->pregs[PR_SRS];
> - srs &= 3;
> - env->sregs[srs][sreg] = env->regs[reg];
> + uint32_t srs;
> + srs = env->pregs[PR_SRS];
> + srs &= 3;
> + env->sregs[srs][sreg] = env->regs[reg];
>
> #if !defined(CONFIG_USER_ONLY)
> - if (srs == 1 || srs == 2) {
> - if (sreg == 6) {
> - /* Writes to tlb-hi write to mm_cause as a side
> - effect. */
> - env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
> - env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
> - }
> - else if (sreg == 5) {
> - uint32_t set;
> - uint32_t idx;
> - uint32_t lo, hi;
> - uint32_t vaddr;
> - int tlb_v;
> + if (srs == 1 || srs == 2) {
> + if (sreg == 6) {
> + /* Writes to tlb-hi write to mm_cause as a side effect. */
> + env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
> + env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
> + } else if (sreg == 5) {
> + uint32_t set;
> + uint32_t idx;
> + uint32_t lo, hi;
> + uint32_t vaddr;
> + int tlb_v;
>
> - idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
> - set >>= 4;
> - set &= 3;
> + idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
> + set >>= 4;
> + set &= 3;
>
> - idx &= 15;
> - /* We've just made a write to tlb_lo. */
> - lo = env->sregs[SFR_RW_MM_TLB_LO];
> - /* Writes are done via r_mm_cause. */
> - hi = env->sregs[SFR_R_MM_CAUSE];
> + idx &= 15;
> + /* We've just made a write to tlb_lo. */
> + lo = env->sregs[SFR_RW_MM_TLB_LO];
> + /* Writes are done via r_mm_cause. */
> + hi = env->sregs[SFR_R_MM_CAUSE];
>
> - vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
> - 13, 31);
> - vaddr <<= TARGET_PAGE_BITS;
> - tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
> - 3, 3);
> - env->tlbsets[srs - 1][set][idx].lo = lo;
> - env->tlbsets[srs - 1][set][idx].hi = hi;
> + vaddr = EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].hi, 13, 31);
> + vaddr <<= TARGET_PAGE_BITS;
> + tlb_v = EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].lo, 3, 3);
> + env->tlbsets[srs - 1][set][idx].lo = lo;
> + env->tlbsets[srs - 1][set][idx].hi = hi;
>
> - D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
> - vaddr, tlb_v, env->pc);
> - if (tlb_v) {
> + D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
> + vaddr, tlb_v, env->pc);
> + if (tlb_v) {
> tlb_flush_page(CPU(cpu), vaddr);
> - }
> - }
> - }
> + }
> + }
> + }
> #endif
> }
>
> void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
> {
> - uint32_t srs;
> - env->pregs[PR_SRS] &= 3;
> - srs = env->pregs[PR_SRS];
> -
> + uint32_t srs;
> + env->pregs[PR_SRS] &= 3;
> + srs = env->pregs[PR_SRS];
> +
> #if !defined(CONFIG_USER_ONLY)
> - if (srs == 1 || srs == 2)
> - {
> - uint32_t set;
> - uint32_t idx;
> - uint32_t lo, hi;
> + if (srs == 1 || srs == 2) {
> + uint32_t set;
> + uint32_t idx;
> + uint32_t lo, hi;
>
> - idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
> - set >>= 4;
> - set &= 3;
> - idx &= 15;
> + idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
> + set >>= 4;
> + set &= 3;
> + idx &= 15;
>
> - /* Update the mirror regs. */
> - hi = env->tlbsets[srs - 1][set][idx].hi;
> - lo = env->tlbsets[srs - 1][set][idx].lo;
> - env->sregs[SFR_RW_MM_TLB_HI] = hi;
> - env->sregs[SFR_RW_MM_TLB_LO] = lo;
> - }
> + /* Update the mirror regs. */
> + hi = env->tlbsets[srs - 1][set][idx].hi;
> + lo = env->tlbsets[srs - 1][set][idx].lo;
> + env->sregs[SFR_RW_MM_TLB_HI] = hi;
> + env->sregs[SFR_RW_MM_TLB_LO] = lo;
> + }
> #endif
> - env->regs[reg] = env->sregs[srs][sreg];
> + env->regs[reg] = env->sregs[srs][sreg];
> }
>
> static void cris_ccs_rshift(CPUCRISState *env)
> {
> - uint32_t ccs;
> + uint32_t ccs;
>
> - /* Apply the ccs shift. */
> - ccs = env->pregs[PR_CCS];
> - ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
> - if (ccs & U_FLAG)
> - {
> - /* Enter user mode. */
> - env->ksp = env->regs[R_SP];
> - env->regs[R_SP] = env->pregs[PR_USP];
> - }
> + /* Apply the ccs shift. */
> + ccs = env->pregs[PR_CCS];
> + ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
> + if (ccs & U_FLAG) {
> + /* Enter user mode. */
> + env->ksp = env->regs[R_SP];
> + env->regs[R_SP] = env->pregs[PR_USP];
> + }
>
> - env->pregs[PR_CCS] = ccs;
> + env->pregs[PR_CCS] = ccs;
> }
>
> void helper_rfe(CPUCRISState *env)
> {
> - int rflag = env->pregs[PR_CCS] & R_FLAG;
> + int rflag = env->pregs[PR_CCS] & R_FLAG;
>
> - D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
> - env->pregs[PR_ERP], env->pregs[PR_PID],
> - env->pregs[PR_CCS],
> - env->btarget);
> + D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
> + env->pregs[PR_ERP], env->pregs[PR_PID],
> + env->pregs[PR_CCS],
> + env->btarget);
>
> - cris_ccs_rshift(env);
> + cris_ccs_rshift(env);
>
> - /* RFE sets the P_FLAG only if the R_FLAG is not set. */
> - if (!rflag)
> - env->pregs[PR_CCS] |= P_FLAG;
> + /* RFE sets the P_FLAG only if the R_FLAG is not set. */
> + if (!rflag) {
> + env->pregs[PR_CCS] |= P_FLAG;
> + }
> }
>
> void helper_rfn(CPUCRISState *env)
> {
> - int rflag = env->pregs[PR_CCS] & R_FLAG;
> + int rflag = env->pregs[PR_CCS] & R_FLAG;
>
> - D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
> - env->pregs[PR_ERP], env->pregs[PR_PID],
> - env->pregs[PR_CCS],
> - env->btarget);
> + D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
> + env->pregs[PR_ERP], env->pregs[PR_PID],
> + env->pregs[PR_CCS],
> + env->btarget);
>
> - cris_ccs_rshift(env);
> + cris_ccs_rshift(env);
>
> - /* Set the P_FLAG only if the R_FLAG is not set. */
> - if (!rflag)
> - env->pregs[PR_CCS] |= P_FLAG;
> + /* Set the P_FLAG only if the R_FLAG is not set. */
> + if (!rflag) {
> + env->pregs[PR_CCS] |= P_FLAG;
> + }
>
> - /* Always set the M flag. */
> - env->pregs[PR_CCS] |= M_FLAG_V32;
> + /* Always set the M flag. */
> + env->pregs[PR_CCS] |= M_FLAG_V32;
> }
>
> uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
> {
> - /* FIXME: clean this up. */
> + /* FIXME: clean this up. */
>
> - /* des ref:
> - The N flag is set according to the selected bit in the dest reg.
> - The Z flag is set if the selected bit and all bits to the right are
> - zero.
> - The X flag is cleared.
> - Other flags are left untouched.
> - The destination reg is not affected.*/
> - unsigned int fz, sbit, bset, mask, masked_t0;
> + /*
> + * des ref:
> + * The N flag is set according to the selected bit in the dest reg.
> + * The Z flag is set if the selected bit and all bits to the right are
> + * zero.
> + * The X flag is cleared.
> + * Other flags are left untouched.
> + * The destination reg is not affected.
> + */
> + unsigned int fz, sbit, bset, mask, masked_t0;
>
> - sbit = t1 & 31;
> - bset = !!(t0 & (1 << sbit));
> - mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
> - masked_t0 = t0 & mask;
> - fz = !(masked_t0 | bset);
> + sbit = t1 & 31;
> + bset = !!(t0 & (1 << sbit));
> + mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
> + masked_t0 = t0 & mask;
> + fz = !(masked_t0 | bset);
>
> - /* Clear the X, N and Z flags. */
> - ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
> - if (env->pregs[PR_VR] < 32)
> - ccs &= ~(V_FLAG | C_FLAG);
> - /* Set the N and Z flags accordingly. */
> - ccs |= (bset << 3) | (fz << 2);
> - return ccs;
> + /* Clear the X, N and Z flags. */
> + ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
> + if (env->pregs[PR_VR] < 32) {
> + ccs &= ~(V_FLAG | C_FLAG);
> + }
> + /* Set the N and Z flags accordingly. */
> + ccs |= (bset << 3) | (fz << 2);
> + return ccs;
> }
>
> static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
> uint32_t flags, uint32_t ccs)
> {
> - unsigned int x, z, mask;
> + unsigned int x, z, mask;
>
> - /* Extended arithmetics, leave the z flag alone. */
> - x = env->cc_x;
> - mask = env->cc_mask | X_FLAG;
> - if (x) {
> - z = flags & Z_FLAG;
> - mask = mask & ~z;
> - }
> - flags &= mask;
> + /* Extended arithmetics, leave the z flag alone. */
> + x = env->cc_x;
> + mask = env->cc_mask | X_FLAG;
> + if (x) {
> + z = flags & Z_FLAG;
> + mask = mask & ~z;
> + }
> + flags &= mask;
>
> - /* all insn clear the x-flag except setf or clrf. */
> - ccs &= ~mask;
> - ccs |= flags;
> - return ccs;
> + /* all insn clear the x-flag except setf or clrf. */
> + ccs &= ~mask;
> + ccs |= flags;
> + return ccs;
> }
>
> uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
> uint32_t ccs, uint32_t res, uint32_t mof)
> {
> - uint32_t flags = 0;
> - int64_t tmp;
> - int dneg;
> + uint32_t flags = 0;
> + int64_t tmp;
> + int dneg;
>
> - dneg = ((int32_t)res) < 0;
> + dneg = ((int32_t)res) < 0;
>
> - tmp = mof;
> - tmp <<= 32;
> - tmp |= res;
> - if (tmp == 0)
> - flags |= Z_FLAG;
> - else if (tmp < 0)
> - flags |= N_FLAG;
> - if ((dneg && mof != -1)
> - || (!dneg && mof != 0))
> - flags |= V_FLAG;
> - return evaluate_flags_writeback(env, flags, ccs);
> + tmp = mof;
> + tmp <<= 32;
> + tmp |= res;
> + if (tmp == 0) {
> + flags |= Z_FLAG;
> + } else if (tmp < 0) {
> + flags |= N_FLAG;
> + }
> + if ((dneg && mof != -1) || (!dneg && mof != 0)) {
> + flags |= V_FLAG;
> + }
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
> uint32_t ccs, uint32_t res, uint32_t mof)
> {
> - uint32_t flags = 0;
> - uint64_t tmp;
> + uint32_t flags = 0;
> + uint64_t tmp;
>
> - tmp = mof;
> - tmp <<= 32;
> - tmp |= res;
> - if (tmp == 0)
> - flags |= Z_FLAG;
> - else if (tmp >> 63)
> - flags |= N_FLAG;
> - if (mof)
> - flags |= V_FLAG;
> + tmp = mof;
> + tmp <<= 32;
> + tmp |= res;
> + if (tmp == 0) {
> + flags |= Z_FLAG;
> + } else if (tmp >> 63) {
> + flags |= N_FLAG;
> + }
> + if (mof) {
> + flags |= V_FLAG;
> + }
>
> - return evaluate_flags_writeback(env, flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
> uint32_t src, uint32_t dst, uint32_t res)
> {
> - uint32_t flags = 0;
> + uint32_t flags = 0;
>
> - src = src & 0x80000000;
> - dst = dst & 0x80000000;
> + src = src & 0x80000000;
> + dst = dst & 0x80000000;
>
> - if ((res & 0x80000000L) != 0L)
> - {
> - flags |= N_FLAG;
> - if (!src && !dst)
> - flags |= V_FLAG;
> - else if (src & dst)
> - flags |= R_FLAG;
> - }
> - else
> - {
> - if (res == 0L)
> - flags |= Z_FLAG;
> - if (src & dst)
> - flags |= V_FLAG;
> - if (dst | src)
> - flags |= R_FLAG;
> - }
> + if ((res & 0x80000000L) != 0L) {
> + flags |= N_FLAG;
> + if (!src && !dst) {
> + flags |= V_FLAG;
> + } else if (src & dst) {
> + flags |= R_FLAG;
> + }
> + } else {
> + if (res == 0L) {
> + flags |= Z_FLAG;
> + }
> + if (src & dst) {
> + flags |= V_FLAG;
> + }
> + if (dst | src) {
> + flags |= R_FLAG;
> + }
> + }
>
> - return evaluate_flags_writeback(env, flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
> uint32_t src, uint32_t dst, uint32_t res)
> {
> - uint32_t flags = 0;
> + uint32_t flags = 0;
>
> - src = src & 0x80000000;
> - dst = dst & 0x80000000;
> + src = src & 0x80000000;
> + dst = dst & 0x80000000;
>
> - if ((res & 0x80000000L) != 0L)
> - {
> - flags |= N_FLAG;
> - if (!src && !dst)
> - flags |= V_FLAG;
> - else if (src & dst)
> - flags |= C_FLAG;
> - }
> - else
> - {
> - if (res == 0L)
> - flags |= Z_FLAG;
> - if (src & dst)
> - flags |= V_FLAG;
> - if (dst | src)
> - flags |= C_FLAG;
> - }
> + if ((res & 0x80000000L) != 0L) {
> + flags |= N_FLAG;
> + if (!src && !dst) {
> + flags |= V_FLAG;
> + } else if (src & dst) {
> + flags |= C_FLAG;
> + }
> + } else {
> + if (res == 0L) {
> + flags |= Z_FLAG;
> + }
> + if (src & dst) {
> + flags |= V_FLAG;
> + }
> + if (dst | src) {
> + flags |= C_FLAG;
> + }
> + }
>
> - return evaluate_flags_writeback(env, flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
> uint32_t src, uint32_t dst, uint32_t res)
> {
> - uint32_t flags = 0;
> + uint32_t flags = 0;
>
> - src = (~src) & 0x80000000;
> - dst = dst & 0x80000000;
> + src = (~src) & 0x80000000;
> + dst = dst & 0x80000000;
>
> - if ((res & 0x80000000L) != 0L)
> - {
> - flags |= N_FLAG;
> - if (!src && !dst)
> - flags |= V_FLAG;
> - else if (src & dst)
> - flags |= C_FLAG;
> - }
> - else
> - {
> - if (res == 0L)
> - flags |= Z_FLAG;
> - if (src & dst)
> - flags |= V_FLAG;
> - if (dst | src)
> - flags |= C_FLAG;
> - }
> + if ((res & 0x80000000L) != 0L) {
> + flags |= N_FLAG;
> + if (!src && !dst) {
> + flags |= V_FLAG;
> + } else if (src & dst) {
> + flags |= C_FLAG;
> + }
> + } else {
> + if (res == 0L) {
> + flags |= Z_FLAG;
> + }
> + if (src & dst) {
> + flags |= V_FLAG;
> + }
> + if (dst | src) {
> + flags |= C_FLAG;
> + }
> + }
>
> - flags ^= C_FLAG;
> - return evaluate_flags_writeback(env, flags, ccs);
> + flags ^= C_FLAG;
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
> uint32_t ccs, uint32_t res)
> {
> - uint32_t flags = 0;
> + uint32_t flags = 0;
>
> - if ((int32_t)res < 0)
> - flags |= N_FLAG;
> - else if (res == 0L)
> - flags |= Z_FLAG;
> + if ((int32_t)res < 0) {
> + flags |= N_FLAG;
> + } else if (res == 0L) {
> + flags |= Z_FLAG;
> + }
>
> - return evaluate_flags_writeback(env, flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
> +
> uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
> uint32_t ccs, uint32_t res)
> {
> - uint32_t flags = 0;
> + uint32_t flags = 0;
>
> - if ((int16_t)res < 0L)
> - flags |= N_FLAG;
> - else if (res == 0)
> - flags |= Z_FLAG;
> + if ((int16_t)res < 0L) {
> + flags |= N_FLAG;
> + } else if (res == 0) {
> + flags |= Z_FLAG;
> + }
>
> - return evaluate_flags_writeback(env, flags, ccs);
> + return evaluate_flags_writeback(env, flags, ccs);
> }
>
> -/* TODO: This is expensive. We could split things up and only evaluate part of
> - CCR on a need to know basis. For now, we simply re-evaluate everything. */
> +/*
> + * TODO: This is expensive. We could split things up and only evaluate part of
> + * CCR on a need to know basis. For now, we simply re-evaluate everything.
> + */
> void helper_evaluate_flags(CPUCRISState *env)
> {
> - uint32_t src, dst, res;
> - uint32_t flags = 0;
> + uint32_t src, dst, res;
> + uint32_t flags = 0;
>
> - src = env->cc_src;
> - dst = env->cc_dest;
> - res = env->cc_result;
> + src = env->cc_src;
> + dst = env->cc_dest;
> + res = env->cc_result;
>
> - if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
> - src = ~src;
> + if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) {
> + src = ~src;
> + }
>
> - /* Now, evaluate the flags. This stuff is based on
> - Per Zander's CRISv10 simulator. */
> - switch (env->cc_size)
> - {
> - case 1:
> - if ((res & 0x80L) != 0L)
> - {
> - flags |= N_FLAG;
> - if (((src & 0x80L) == 0L)
> - && ((dst & 0x80L) == 0L))
> - {
> - flags |= V_FLAG;
> - }
> - else if (((src & 0x80L) != 0L)
> - && ((dst & 0x80L) != 0L))
> - {
> - flags |= C_FLAG;
> - }
> - }
> - else
> - {
> - if ((res & 0xFFL) == 0L)
> - {
> - flags |= Z_FLAG;
> - }
> - if (((src & 0x80L) != 0L)
> - && ((dst & 0x80L) != 0L))
> - {
> - flags |= V_FLAG;
> - }
> - if ((dst & 0x80L) != 0L
> - || (src & 0x80L) != 0L)
> - {
> - flags |= C_FLAG;
> - }
> - }
> - break;
> - case 2:
> - if ((res & 0x8000L) != 0L)
> - {
> - flags |= N_FLAG;
> - if (((src & 0x8000L) == 0L)
> - && ((dst & 0x8000L) == 0L))
> - {
> - flags |= V_FLAG;
> - }
> - else if (((src & 0x8000L) != 0L)
> - && ((dst & 0x8000L) != 0L))
> - {
> - flags |= C_FLAG;
> - }
> - }
> - else
> - {
> - if ((res & 0xFFFFL) == 0L)
> - {
> - flags |= Z_FLAG;
> - }
> - if (((src & 0x8000L) != 0L)
> - && ((dst & 0x8000L) != 0L))
> - {
> - flags |= V_FLAG;
> - }
> - if ((dst & 0x8000L) != 0L
> - || (src & 0x8000L) != 0L)
> - {
> - flags |= C_FLAG;
> - }
> - }
> - break;
> - case 4:
> - if ((res & 0x80000000L) != 0L)
> - {
> - flags |= N_FLAG;
> - if (((src & 0x80000000L) == 0L)
> - && ((dst & 0x80000000L) == 0L))
> - {
> - flags |= V_FLAG;
> - }
> - else if (((src & 0x80000000L) != 0L) &&
> - ((dst & 0x80000000L) != 0L))
> - {
> - flags |= C_FLAG;
> - }
> - }
> - else
> - {
> - if (res == 0L)
> - flags |= Z_FLAG;
> - if (((src & 0x80000000L) != 0L)
> - && ((dst & 0x80000000L) != 0L))
> - flags |= V_FLAG;
> - if ((dst & 0x80000000L) != 0L
> - || (src & 0x80000000L) != 0L)
> - flags |= C_FLAG;
> - }
> - break;
> - default:
> - break;
> - }
> + /*
> + * Now, evaluate the flags. This stuff is based on
> + * Per Zander's CRISv10 simulator.
> + */
> + switch (env->cc_size) {
> + case 1:
> + if ((res & 0x80L) != 0L) {
> + flags |= N_FLAG;
> + if (((src & 0x80L) == 0L) && ((dst & 0x80L) == 0L)) {
> + flags |= V_FLAG;
> + } else if (((src & 0x80L) != 0L) && ((dst & 0x80L) != 0L)) {
> + flags |= C_FLAG;
> + }
> + } else {
> + if ((res & 0xFFL) == 0L) {
> + flags |= Z_FLAG;
> + }
> + if (((src & 0x80L) != 0L) && ((dst & 0x80L) != 0L)) {
> + flags |= V_FLAG;
> + }
> + if ((dst & 0x80L) != 0L || (src & 0x80L) != 0L) {
> + flags |= C_FLAG;
> + }
> + }
> + break;
> + case 2:
> + if ((res & 0x8000L) != 0L) {
> + flags |= N_FLAG;
> + if (((src & 0x8000L) == 0L) && ((dst & 0x8000L) == 0L)) {
> + flags |= V_FLAG;
> + } else if (((src & 0x8000L) != 0L) && ((dst & 0x8000L) != 0L)) {
> + flags |= C_FLAG;
> + }
> + } else {
> + if ((res & 0xFFFFL) == 0L) {
> + flags |= Z_FLAG;
> + }
> + if (((src & 0x8000L) != 0L) && ((dst & 0x8000L) != 0L)) {
> + flags |= V_FLAG;
> + }
> + if ((dst & 0x8000L) != 0L || (src & 0x8000L) != 0L) {
> + flags |= C_FLAG;
> + }
> + }
> + break;
> + case 4:
> + if ((res & 0x80000000L) != 0L) {
> + flags |= N_FLAG;
> + if (((src & 0x80000000L) == 0L) && ((dst & 0x80000000L) == 0L)) {
> + flags |= V_FLAG;
> + } else if (((src & 0x80000000L) != 0L) &&
> + ((dst & 0x80000000L) != 0L)) {
> + flags |= C_FLAG;
> + }
> + } else {
> + if (res == 0L) {
> + flags |= Z_FLAG;
> + }
> + if (((src & 0x80000000L) != 0L) && ((dst & 0x80000000L) != 0L)) {
> + flags |= V_FLAG;
> + }
> + if ((dst & 0x80000000L) != 0L || (src & 0x80000000L) != 0L) {
> + flags |= C_FLAG;
> + }
> + }
> + break;
> + default:
> + break;
> + }
>
> - if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
> - flags ^= C_FLAG;
> + if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) {
> + flags ^= C_FLAG;
> + }
>
> - env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
> - env->pregs[PR_CCS]);
> + env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
> + env->pregs[PR_CCS]);
> }
>
> void helper_top_evaluate_flags(CPUCRISState *env)
> {
> - switch (env->cc_op)
> - {
> - case CC_OP_MCP:
> - env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
> - env->pregs[PR_CCS], env->cc_src,
> - env->cc_dest, env->cc_result);
> - break;
> - case CC_OP_MULS:
> - env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
> - env->pregs[PR_CCS], env->cc_result,
> - env->pregs[PR_MOF]);
> - break;
> - case CC_OP_MULU:
> - env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
> - env->pregs[PR_CCS], env->cc_result,
> - env->pregs[PR_MOF]);
> - break;
> - case CC_OP_MOVE:
> - case CC_OP_AND:
> - case CC_OP_OR:
> - case CC_OP_XOR:
> - case CC_OP_ASR:
> - case CC_OP_LSR:
> - case CC_OP_LSL:
> - switch (env->cc_size)
> - {
> - case 4:
> - env->pregs[PR_CCS] =
> - helper_evaluate_flags_move_4(env,
> - env->pregs[PR_CCS],
> - env->cc_result);
> - break;
> - case 2:
> - env->pregs[PR_CCS] =
> - helper_evaluate_flags_move_2(env,
> - env->pregs[PR_CCS],
> - env->cc_result);
> - break;
> - default:
> - helper_evaluate_flags(env);
> - break;
> - }
> - break;
> - case CC_OP_FLAGS:
> - /* live. */
> - break;
> - case CC_OP_SUB:
> - case CC_OP_CMP:
> - if (env->cc_size == 4)
> - env->pregs[PR_CCS] =
> - helper_evaluate_flags_sub_4(env,
> - env->pregs[PR_CCS],
> - env->cc_src, env->cc_dest,
> - env->cc_result);
> - else
> - helper_evaluate_flags(env);
> - break;
> - default:
> - {
> - switch (env->cc_size)
> - {
> - case 4:
> - env->pregs[PR_CCS] =
> - helper_evaluate_flags_alu_4(env,
> - env->pregs[PR_CCS],
> - env->cc_src, env->cc_dest,
> - env->cc_result);
> - break;
> - default:
> - helper_evaluate_flags(env);
> - break;
> - }
> - }
> - break;
> - }
> + switch (env->cc_op) {
> + case CC_OP_MCP:
> + env->pregs[PR_CCS]
> + = helper_evaluate_flags_mcp(env, env->pregs[PR_CCS],
> + env->cc_src, env->cc_dest,
> + env->cc_result);
> + break;
> + case CC_OP_MULS:
> + env->pregs[PR_CCS]
> + = helper_evaluate_flags_muls(env, env->pregs[PR_CCS],
> + env->cc_result, env->pregs[PR_MOF]);
> + break;
> + case CC_OP_MULU:
> + env->pregs[PR_CCS]
> + = helper_evaluate_flags_mulu(env, env->pregs[PR_CCS],
> + env->cc_result, env->pregs[PR_MOF]);
> + break;
> + case CC_OP_MOVE:
> + case CC_OP_AND:
> + case CC_OP_OR:
> + case CC_OP_XOR:
> + case CC_OP_ASR:
> + case CC_OP_LSR:
> + case CC_OP_LSL:
> + switch (env->cc_size) {
> + case 4:
> + env->pregs[PR_CCS] =
> + helper_evaluate_flags_move_4(env,
> + env->pregs[PR_CCS],
> + env->cc_result);
> + break;
> + case 2:
> + env->pregs[PR_CCS] =
> + helper_evaluate_flags_move_2(env,
> + env->pregs[PR_CCS],
> + env->cc_result);
> + break;
> + default:
> + helper_evaluate_flags(env);
> + break;
> + }
> + break;
> + case CC_OP_FLAGS:
> + /* live. */
> + break;
> + case CC_OP_SUB:
> + case CC_OP_CMP:
> + if (env->cc_size == 4) {
> + env->pregs[PR_CCS] =
> + helper_evaluate_flags_sub_4(env,
> + env->pregs[PR_CCS],
> + env->cc_src, env->cc_dest,
> + env->cc_result);
> + } else {
> + helper_evaluate_flags(env);
> + }
> + break;
> + default:
> + switch (env->cc_size) {
> + case 4:
> + env->pregs[PR_CCS] =
> + helper_evaluate_flags_alu_4(env,
> + env->pregs[PR_CCS],
> + env->cc_src, env->cc_dest,
> + env->cc_result);
> + break;
> + default:
> + helper_evaluate_flags(env);
> + break;
> + }
> + break;
> + }
> }
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 12/39] target/cris: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 12/39] target/cris: Use env_cpu, env_archcpu Richard Henderson
@ 2019-05-09 18:04 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:04 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:10 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/cris/cpu.h | 5 -----
> linux-user/cris/cpu_loop.c | 2 +-
> target/cris/mmu.c | 3 +--
> target/cris/op_helper.c | 10 +++-------
> target/cris/translate.c | 2 +-
> 5 files changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index 883799b463..7f244ad545 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -183,11 +183,6 @@ struct CRISCPU {
> CPUCRISState env;
> };
>
> -static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
> -{
> - return container_of(env, CRISCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(CRISCPU, env)
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c
> index 7ec36cb0b5..86e711108d 100644
> --- a/linux-user/cris/cpu_loop.c
> +++ b/linux-user/cris/cpu_loop.c
> @@ -23,7 +23,7 @@
>
> void cpu_loop(CPUCRISState *env)
> {
> - CPUState *cs = CPU(cris_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr, ret;
> target_siginfo_t info;
>
> diff --git a/target/cris/mmu.c b/target/cris/mmu.c
> index 9cb73bbfec..2acbcfd1c7 100644
> --- a/target/cris/mmu.c
> +++ b/target/cris/mmu.c
> @@ -288,7 +288,6 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
>
> void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> - CRISCPU *cpu = cris_env_get_cpu(env);
> target_ulong vaddr;
> unsigned int idx;
> uint32_t lo, hi;
> @@ -312,7 +311,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> if (tlb_v && !tlb_g && (tlb_pid == pid)) {
> vaddr = tlb_vpn << TARGET_PAGE_BITS;
> D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
> - tlb_flush_page(CPU(cpu), vaddr);
> + tlb_flush_page(env_cpu(env), vaddr);
> }
> }
> }
> diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
> index d4479167a5..0e323c1dd7 100644
> --- a/target/cris/op_helper.c
> +++ b/target/cris/op_helper.c
> @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
>
> void helper_raise_exception(CPUCRISState *env, uint32_t index)
> {
> - CPUState *cs = CPU(cris_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = index;
> cpu_loop_exit(cs);
> @@ -86,8 +86,7 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> {
> #if !defined(CONFIG_USER_ONLY)
> - CRISCPU *cpu = cris_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> tlb_flush_page(cs, env->pregs[PR_SPC]);
> tlb_flush_page(cs, new_spc);
> @@ -100,9 +99,6 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
>
> void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> {
> -#if !defined(CONFIG_USER_ONLY)
> - CRISCPU *cpu = cris_env_get_cpu(env);
> -#endif
> uint32_t srs;
> srs = env->pregs[PR_SRS];
> srs &= 3;
> @@ -140,7 +136,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
> vaddr, tlb_v, env->pc);
> if (tlb_v) {
> - tlb_flush_page(CPU(cpu), vaddr);
> + tlb_flush_page(env_cpu(env), vaddr);
> }
> }
> }
> diff --git a/target/cris/translate.c b/target/cris/translate.c
> index b005a5c20e..c0af9665fc 100644
> --- a/target/cris/translate.c
> +++ b/target/cris/translate.c
> @@ -3104,7 +3104,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
> * delayslot, like in real hw.
> */
> pc_start = tb->pc & ~1;
> - dc->cpu = cris_env_get_cpu(env);
> + dc->cpu = env_archcpu(env);
> dc->tb = tb;
>
> dc->is_jmp = DISAS_NEXT;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 13/39] target/hppa: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 13/39] target/hppa: " Richard Henderson
@ 2019-05-09 18:05 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:21 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Combined uses of CPU(hppa_env_get_cpu()) were failures to use
> the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/hppa/cpu.h | 5 -----
> linux-user/hppa/cpu_loop.c | 2 +-
> target/hppa/helper.c | 3 +--
> target/hppa/int_helper.c | 4 ++--
> target/hppa/mem_helper.c | 10 ++++------
> target/hppa/op_helper.c | 8 +++-----
> 6 files changed, 11 insertions(+), 21 deletions(-)
>
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 887e10398a..a5ddc53bf1 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -222,11 +222,6 @@ struct HPPACPU {
> QEMUTimer *alarm_timer;
> };
>
> -static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
> -{
> - return container_of(env, HPPACPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(HPPACPU, env)
>
> typedef CPUHPPAState CPUArchState;
> diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
> index 880955fdef..9915456a1d 100644
> --- a/linux-user/hppa/cpu_loop.c
> +++ b/linux-user/hppa/cpu_loop.c
> @@ -105,7 +105,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env)
>
> void cpu_loop(CPUHPPAState *env)
> {
> - CPUState *cs = CPU(hppa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_siginfo_t info;
> abi_ulong ret;
> int trapnr;
> diff --git a/target/hppa/helper.c b/target/hppa/helper.c
> index 11c61b3ca2..0dcd105b88 100644
> --- a/target/hppa/helper.c
> +++ b/target/hppa/helper.c
> @@ -71,8 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
> /* If PSW_P changes, it affects how we translate addresses. */
> if ((psw ^ old_psw) & PSW_P) {
> #ifndef CONFIG_USER_ONLY
> - CPUState *src = CPU(hppa_env_get_cpu(env));
> - tlb_flush_by_mmuidx(src, 0xf);
> + tlb_flush_by_mmuidx(env_cpu(env), 0xf);
> #endif
> }
> }
> diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
> index 8d5edd3a20..89241c31e7 100644
> --- a/target/hppa/int_helper.c
> +++ b/target/hppa/int_helper.c
> @@ -77,7 +77,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
> {
> env->cr[CR_EIRR] &= ~val;
> qemu_mutex_lock_iothread();
> - eval_interrupt(hppa_env_get_cpu(env));
> + eval_interrupt(env_archcpu(env));
> qemu_mutex_unlock_iothread();
> }
>
> @@ -85,7 +85,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
> {
> env->cr[CR_EIEM] = val;
> qemu_mutex_lock_iothread();
> - eval_interrupt(hppa_env_get_cpu(env));
> + eval_interrupt(env_archcpu(env));
> qemu_mutex_unlock_iothread();
> }
> #endif /* !CONFIG_USER_ONLY */
> diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
> index 77fb544838..e2f464c78c 100644
> --- a/target/hppa/mem_helper.c
> +++ b/target/hppa/mem_helper.c
> @@ -55,7 +55,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
>
> static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
> {
> - CPUState *cs = CPU(hppa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> unsigned i, n = 1 << (2 * ent->page_size);
> uint64_t addr = ent->va_b;
>
> @@ -323,7 +323,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
>
> void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
> {
> - CPUState *src = CPU(hppa_env_get_cpu(env));
> + CPUState *src = env_cpu(env);
> CPUState *cpu;
> trace_hppa_tlb_ptlb(env);
> run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr);
> @@ -340,17 +340,15 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
> number of pages/entries (we choose all), and is local to the cpu. */
> void HELPER(ptlbe)(CPUHPPAState *env)
> {
> - CPUState *src = CPU(hppa_env_get_cpu(env));
> trace_hppa_tlb_ptlbe(env);
> memset(env->tlb, 0, sizeof(env->tlb));
> - tlb_flush_by_mmuidx(src, 0xf);
> + tlb_flush_by_mmuidx(env_cpu(env), 0xf);
> }
>
> void cpu_hppa_change_prot_id(CPUHPPAState *env)
> {
> if (env->psw & PSW_P) {
> - CPUState *src = CPU(hppa_env_get_cpu(env));
> - tlb_flush_by_mmuidx(src, 0xf);
> + tlb_flush_by_mmuidx(env_cpu(env), 0xf);
> }
> }
>
> diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
> index 952e97a7d7..04d23c1b22 100644
> --- a/target/hppa/op_helper.c
> +++ b/target/hppa/op_helper.c
> @@ -29,8 +29,7 @@
>
> void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
> {
> - HPPACPU *cpu = hppa_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> cpu_loop_exit(cs);
> @@ -38,8 +37,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
>
> void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
> {
> - HPPACPU *cpu = hppa_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> cpu_loop_exit_restore(cs, ra);
> @@ -630,7 +628,7 @@ target_ureg HELPER(read_interval_timer)(void)
> #ifndef CONFIG_USER_ONLY
> void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
> {
> - HPPACPU *cpu = hppa_env_get_cpu(env);
> + HPPACPU *cpu = env_archcpu(env);
> uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> uint64_t timeout;
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 14/39] target/i386: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 14/39] target/i386: " Richard Henderson
@ 2019-05-09 18:07 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:19 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Combined uses of CPU(x86_env_get_cpu()) were failures to use
> the more proper, ENV_GET_CPU macro, now replaced by env_cpu.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/i386/cpu.h | 5 -----
> bsd-user/main.c | 3 +--
> hw/i386/kvmvapic.c | 4 ++--
> hw/i386/pc.c | 2 +-
> linux-user/i386/cpu_loop.c | 2 +-
> linux-user/i386/signal.c | 2 +-
> linux-user/vm86.c | 18 +++++++++---------
> target/i386/bpt_helper.c | 4 ++--
> target/i386/cpu.c | 4 ++--
> target/i386/excp_helper.c | 2 +-
> target/i386/fpu_helper.c | 2 +-
> target/i386/helper.c | 16 ++++++----------
> target/i386/misc_helper.c | 24 +++++++++++-------------
> target/i386/seg_helper.c | 14 +++++++-------
> target/i386/smm_helper.c | 4 ++--
> target/i386/svm_helper.c | 22 +++++++++++-----------
> 16 files changed, 58 insertions(+), 70 deletions(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 2546ffa4d4..e7f94437b1 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1479,11 +1479,6 @@ struct X86CPU {
> int32_t hv_max_vps;
> };
>
> -static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
> -{
> - return container_of(env, X86CPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(X86CPU, env)
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/bsd-user/main.c b/bsd-user/main.c
> index 6192e9d91e..bfdcae4269 100644
> --- a/bsd-user/main.c
> +++ b/bsd-user/main.c
> @@ -140,8 +140,7 @@ static void set_idt(int n, unsigned int dpl)
>
> void cpu_loop(CPUX86State *env)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(cpu);
> int trapnr;
> abi_ulong pc;
> //target_siginfo_t info;
> diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
> index 70f6f26a94..fe5b12ef6e 100644
> --- a/hw/i386/kvmvapic.c
> +++ b/hw/i386/kvmvapic.c
> @@ -152,7 +152,7 @@ static void update_guest_rom_state(VAPICROMState *s)
>
> static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> hwaddr paddr;
> target_ulong addr;
>
> @@ -279,7 +279,7 @@ instruction_ok:
>
> static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> hwaddr paddr;
> uint32_t rom_state_vaddr;
> uint32_t pos, patch, offset;
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index d98b737b8f..6a3a0678fc 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -408,7 +408,7 @@ uint64_t cpu_get_tsc(CPUX86State *env)
> /* IRQ handling */
> int cpu_get_pic_interrupt(CPUX86State *env)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
> int intno;
>
> if (!kvm_irqchip_in_kernel()) {
> diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
> index 51cfa006c9..71da24384f 100644
> --- a/linux-user/i386/cpu_loop.c
> +++ b/linux-user/i386/cpu_loop.c
> @@ -82,7 +82,7 @@ static void set_idt(int n, unsigned int dpl)
>
> void cpu_loop(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> abi_ulong pc;
> abi_ulong ret;
> diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c
> index fecb4c99c3..97a39204cc 100644
> --- a/linux-user/i386/signal.c
> +++ b/linux-user/i386/signal.c
> @@ -198,7 +198,7 @@ static void setup_sigcontext(struct target_sigcontext *sc,
> struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask,
> abi_ulong fpstate_addr)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> #ifndef TARGET_X86_64
> uint16_t magic;
>
> diff --git a/linux-user/vm86.c b/linux-user/vm86.c
> index 9c393df424..2fa7a89edc 100644
> --- a/linux-user/vm86.c
> +++ b/linux-user/vm86.c
> @@ -72,7 +72,7 @@ static inline unsigned int vm_getl(CPUX86State *env,
>
> void save_v86_state(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> struct target_vm86plus_struct * target_v86;
>
> @@ -132,7 +132,7 @@ static inline void return_to_32bit(CPUX86State *env, int retval)
>
> static inline int set_IF(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
>
> ts->v86flags |= VIF_MASK;
> @@ -145,7 +145,7 @@ static inline int set_IF(CPUX86State *env)
>
> static inline void clear_IF(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
>
> ts->v86flags &= ~VIF_MASK;
> @@ -163,7 +163,7 @@ static inline void clear_AC(CPUX86State *env)
>
> static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
>
> set_flags(ts->v86flags, eflags, ts->v86mask);
> @@ -177,7 +177,7 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
>
> static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
>
> set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
> @@ -191,7 +191,7 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
>
> static inline unsigned int get_vflags(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> unsigned int flags;
>
> @@ -208,7 +208,7 @@ static inline unsigned int get_vflags(CPUX86State *env)
> support TSS interrupt revectoring, so this code is always executed) */
> static void do_int(CPUX86State *env, int intno)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> uint32_t int_addr, segoffs, ssp;
> unsigned int sp;
> @@ -267,7 +267,7 @@ void handle_vm86_trap(CPUX86State *env, int trapno)
>
> void handle_vm86_fault(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> uint32_t csp, ssp;
> unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
> @@ -392,7 +392,7 @@ void handle_vm86_fault(CPUX86State *env)
>
> int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> struct target_vm86plus_struct * target_v86;
> int ret;
> diff --git a/target/i386/bpt_helper.c b/target/i386/bpt_helper.c
> index b3efdc77ec..c3a8ea73c9 100644
> --- a/target/i386/bpt_helper.c
> +++ b/target/i386/bpt_helper.c
> @@ -53,7 +53,7 @@ static inline int hw_breakpoint_len(unsigned long dr7, int index)
>
> static int hw_breakpoint_insert(CPUX86State *env, int index)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong dr7 = env->dr[7];
> target_ulong drN = env->dr[index];
> int err = 0;
> @@ -97,7 +97,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int index)
>
> static void hw_breakpoint_remove(CPUX86State *env, int index)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> switch (hw_breakpoint_type(env->dr[7], index)) {
> case DR7_TYPE_BP_INST:
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 722c5514d4..5b84629f91 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4221,8 +4221,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> uint32_t *eax, uint32_t *ebx,
> uint32_t *ecx, uint32_t *edx)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + X86CPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
> uint32_t pkg_offset;
> uint32_t limit;
> uint32_t signature[3];
> diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c
> index 49231f6b69..371792ce8b 100644
> --- a/target/i386/excp_helper.c
> +++ b/target/i386/excp_helper.c
> @@ -90,7 +90,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
> int next_eip_addend,
> uintptr_t retaddr)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> if (!is_int) {
> cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
> diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c
> index ea5a0c4861..005f1f68f8 100644
> --- a/target/i386/fpu_helper.c
> +++ b/target/i386/fpu_helper.c
> @@ -1477,7 +1477,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
> env->pkru = 0;
> }
> if (env->pkru != old_pkru) {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> tlb_flush(cs);
> }
> }
> diff --git a/target/i386/helper.c b/target/i386/helper.c
> index 96336055f3..ff3a60c7cf 100644
> --- a/target/i386/helper.c
> +++ b/target/i386/helper.c
> @@ -622,7 +622,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
>
> void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
> int pe_state;
>
> qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
> @@ -664,19 +664,16 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
> the PDPT */
> void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> -
> env->cr[3] = new_cr3;
> if (env->cr[0] & CR0_PG_MASK) {
> qemu_log_mask(CPU_LOG_MMU,
> "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> }
>
> void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> uint32_t hflags;
>
> #if defined(DEBUG_MMU)
> @@ -685,7 +682,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
> if ((new_cr4 ^ env->cr[4]) &
> (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
> CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> /* Clear bits we're going to recompute. */
> @@ -977,8 +974,8 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
>
> void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + X86CPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
>
> if (kvm_enabled() || whpx_enabled()) {
> env->tpr_access_type = access;
> @@ -996,8 +993,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
> target_ulong *base, unsigned int *limit,
> unsigned int *flags)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> SegmentCache *dt;
> target_ulong ptr;
> uint32_t e1, e2;
> diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
> index 78f2020ef2..3eff6885f8 100644
> --- a/target/i386/misc_helper.c
> +++ b/target/i386/misc_helper.c
> @@ -133,7 +133,7 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
> break;
> case 8:
> if (!(env->hflags2 & HF2_VINTR_MASK)) {
> - val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
> + val = cpu_get_apic_tpr(env_archcpu(env)->apic_state);
> } else {
> val = env->v_tpr;
> }
> @@ -158,7 +158,7 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
> case 8:
> if (!(env->hflags2 & HF2_VINTR_MASK)) {
> qemu_mutex_lock_iothread();
> - cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
> + cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0);
> qemu_mutex_unlock_iothread();
> }
> env->v_tpr = t0 & 0x0f;
> @@ -180,7 +180,7 @@ void helper_lmsw(CPUX86State *env, target_ulong t0)
>
> void helper_invlpg(CPUX86State *env, target_ulong addr)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
> tlb_flush_page(CPU(cpu), addr);
> @@ -247,7 +247,7 @@ void helper_wrmsr(CPUX86State *env)
> env->sysenter_eip = val;
> break;
> case MSR_IA32_APICBASE:
> - cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
> + cpu_set_apic_base(env_archcpu(env)->apic_state, val);
> break;
> case MSR_EFER:
> {
> @@ -404,7 +404,7 @@ void helper_rdmsr(CPUX86State *env)
> val = env->sysenter_eip;
> break;
> case MSR_IA32_APICBASE:
> - val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
> + val = cpu_get_apic_base(env_archcpu(env)->apic_state);
> break;
> case MSR_EFER:
> val = env->efer;
> @@ -561,7 +561,7 @@ static void do_hlt(X86CPU *cpu)
>
> void helper_hlt(CPUX86State *env, int next_eip_addend)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
> env->eip += next_eip_addend;
> @@ -580,8 +580,8 @@ void helper_monitor(CPUX86State *env, target_ulong ptr)
>
> void helper_mwait(CPUX86State *env, int next_eip_addend)
> {
> - CPUState *cs;
> - X86CPU *cpu;
> + CPUState *cs = env_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
>
> if ((uint32_t)env->regs[R_ECX] != 0) {
> raise_exception_ra(env, EXCP0D_GPF, GETPC());
> @@ -589,8 +589,6 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
> cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
> env->eip += next_eip_addend;
>
> - cpu = x86_env_get_cpu(env);
> - cs = CPU(cpu);
> /* XXX: not complete but not completely erroneous */
> if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
> do_pause(cpu);
> @@ -601,7 +599,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
>
> void helper_pause(CPUX86State *env, int next_eip_addend)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC());
> env->eip += next_eip_addend;
> @@ -611,7 +609,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend)
>
> void helper_debug(CPUX86State *env)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = EXCP_DEBUG;
> cpu_loop_exit(cs);
> @@ -631,7 +629,7 @@ uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
>
> void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> if ((env->cr[4] & CR4_PKE_MASK) == 0) {
> raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
> diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c
> index 63e265cb38..87a627f9dc 100644
> --- a/target/i386/seg_helper.c
> +++ b/target/i386/seg_helper.c
> @@ -137,7 +137,7 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
> uint32_t *esp_ptr, int dpl,
> uintptr_t retaddr)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
> int type, index, shift;
>
> #if 0
> @@ -830,7 +830,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
>
> static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
> int index;
>
> #if 0
> @@ -972,7 +972,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
> #if defined(CONFIG_USER_ONLY)
> void helper_syscall(CPUX86State *env, int next_eip_addend)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = EXCP_SYSCALL;
> env->exception_next_eip = env->eip + next_eip_addend;
> @@ -1172,7 +1172,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
> static void handle_even_inj(CPUX86State *env, int intno, int is_int,
> int error_code, int is_hw, int rm)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
> control.event_inj));
>
> @@ -1312,7 +1312,7 @@ void x86_cpu_do_interrupt(CPUState *cs)
>
> void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
> {
> - do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
> + do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
> }
>
> bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> @@ -1763,7 +1763,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
> target_ulong ssp, old_ssp, offset, sp;
>
> LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=%d\n", new_cs, new_eip, shift);
> - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
> + LOG_PCALL_STATE(env_cpu(env));
> if ((new_cs & 0xfffc) == 0) {
> raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
> }
> @@ -2167,7 +2167,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift,
> }
> LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
> new_cs, new_eip, shift, addend);
> - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
> + LOG_PCALL_STATE(env_cpu(env));
> if ((new_cs & 0xfffc) == 0) {
> raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr);
> }
> diff --git a/target/i386/smm_helper.c b/target/i386/smm_helper.c
> index c1c34a75db..eb5aa6eb3d 100644
> --- a/target/i386/smm_helper.c
> +++ b/target/i386/smm_helper.c
> @@ -204,8 +204,8 @@ void do_smm_enter(X86CPU *cpu)
>
> void helper_rsm(CPUX86State *env)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + X86CPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
> target_ulong sm_state;
> int i, offset;
> uint32_t val;
> diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c
> index 9fd22a883b..7b8105a1c3 100644
> --- a/target/i386/svm_helper.c
> +++ b/target/i386/svm_helper.c
> @@ -84,7 +84,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
> static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
> const SegmentCache *sc)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector),
> sc->selector);
> @@ -99,7 +99,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
> static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
> SegmentCache *sc)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> unsigned int flags;
>
> sc->selector = x86_lduw_phys(cs,
> @@ -122,7 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
>
> void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong addr;
> uint64_t nested_ctl;
> uint32_t event_inj;
> @@ -314,7 +314,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> env->hflags2 |= HF2_GIF_MASK;
>
> if (int_ctl & V_IRQ_MASK) {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
> }
> @@ -379,7 +379,7 @@ void helper_vmmcall(CPUX86State *env)
>
> void helper_vmload(CPUX86State *env, int aflag)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong addr;
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC());
> @@ -419,7 +419,7 @@ void helper_vmload(CPUX86State *env, int aflag)
>
> void helper_vmsave(CPUX86State *env, int aflag)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong addr;
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC());
> @@ -482,7 +482,7 @@ void helper_skinit(CPUX86State *env)
>
> void helper_invlpga(CPUX86State *env, int aflag)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> + X86CPU *cpu = env_archcpu(env);
> target_ulong addr;
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC());
> @@ -501,7 +501,7 @@ void helper_invlpga(CPUX86State *env, int aflag)
> void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,
> uint64_t param, uintptr_t retaddr)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> if (likely(!(env->hflags & HF_GUEST_MASK))) {
> return;
> @@ -583,7 +583,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
> void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
> uint32_t next_eip_addend)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) {
> /* FIXME: this should be read in at vmrun (faster this way?) */
> @@ -604,7 +604,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param,
> void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1,
> uintptr_t retaddr)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cpu_restore_state(cs, retaddr, true);
>
> @@ -625,7 +625,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1,
>
> void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
> {
> - CPUState *cs = CPU(x86_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t int_ctl;
>
> if (env->hflags & HF_INHIBIT_IRQ_MASK) {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 15/39] target/lm32: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 15/39] target/lm32: " Richard Henderson
@ 2019-05-09 18:08 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:17 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/lm32/cpu.h | 5 -----
> target/lm32/helper.c | 19 ++++++-------------
> target/lm32/op_helper.c | 6 +++---
> target/lm32/translate.c | 2 +-
> 4 files changed, 10 insertions(+), 22 deletions(-)
>
> diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
> index c6b252f90a..8e7b70a275 100644
> --- a/target/lm32/cpu.h
> +++ b/target/lm32/cpu.h
> @@ -195,11 +195,6 @@ struct LM32CPU {
> uint32_t features;
> };
>
> -static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
> -{
> - return container_of(env, LM32CPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(LM32CPU, env)
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/target/lm32/helper.c b/target/lm32/helper.c
> index a039a993ff..674cbd7fe4 100644
> --- a/target/lm32/helper.c
> +++ b/target/lm32/helper.c
> @@ -58,28 +58,23 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>
> void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> -
> - cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
> + cpu_breakpoint_insert(env_cpu(env), address, BP_CPU,
> &env->cpu_breakpoint[idx]);
> }
>
> void lm32_breakpoint_remove(CPULM32State *env, int idx)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> -
> if (!env->cpu_breakpoint[idx]) {
> return;
> }
>
> - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
> + cpu_breakpoint_remove_by_ref(env_cpu(env), env->cpu_breakpoint[idx]);
> env->cpu_breakpoint[idx] = NULL;
> }
>
> void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
> lm32_wp_t wp_type)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> int flags = 0;
>
> switch (wp_type) {
> @@ -98,26 +93,24 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
> }
>
> if (flags != 0) {
> - cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
> - &env->cpu_watchpoint[idx]);
> + cpu_watchpoint_insert(env_cpu(env), address, 1, flags,
> + &env->cpu_watchpoint[idx]);
> }
> }
>
> void lm32_watchpoint_remove(CPULM32State *env, int idx)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> -
> if (!env->cpu_watchpoint[idx]) {
> return;
> }
>
> - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
> + cpu_watchpoint_remove_by_ref(env_cpu(env), env->cpu_watchpoint[idx]);
> env->cpu_watchpoint[idx] = NULL;
> }
>
> static bool check_watchpoints(CPULM32State *env)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> + LM32CPU *cpu = env_archcpu(env);
> int i;
>
> for (i = 0; i < cpu->num_watchpoints; i++) {
> diff --git a/target/lm32/op_helper.c b/target/lm32/op_helper.c
> index 234d55e056..ebff4c4518 100644
> --- a/target/lm32/op_helper.c
> +++ b/target/lm32/op_helper.c
> @@ -16,7 +16,7 @@
> #if !defined(CONFIG_USER_ONLY)
> void raise_exception(CPULM32State *env, int index)
> {
> - CPUState *cs = CPU(lm32_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = index;
> cpu_loop_exit(cs);
> @@ -29,7 +29,7 @@ void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
>
> void HELPER(hlt)(CPULM32State *env)
> {
> - CPUState *cs = CPU(lm32_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> @@ -39,7 +39,7 @@ void HELPER(hlt)(CPULM32State *env)
> void HELPER(ill)(CPULM32State *env)
> {
> #ifndef CONFIG_USER_ONLY
> - CPUState *cs = CPU(lm32_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> fprintf(stderr, "VM paused due to illegal instruction. "
> "Connect a debugger or switch to the monitor console "
> "to find out more.\n");
> diff --git a/target/lm32/translate.c b/target/lm32/translate.c
> index f0e0e7058e..b9f2f2c4a7 100644
> --- a/target/lm32/translate.c
> +++ b/target/lm32/translate.c
> @@ -1053,7 +1053,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
> void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
> {
> CPULM32State *env = cs->env_ptr;
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> + LM32CPU *cpu = env_archcpu(env);
> struct DisasContext ctx, *dc = &ctx;
> uint32_t pc_start;
> uint32_t page_start;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 16/39] target/m68k: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 16/39] target/m68k: " Richard Henderson
@ 2019-05-09 18:16 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:16 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> linux-user/m68k/target_cpu.h | 2 +-
> target/m68k/cpu.h | 5 -----
> linux-user/m68k-sim.c | 3 +--
> linux-user/m68k/cpu_loop.c | 2 +-
> target/m68k/helper.c | 33 ++++++++++++---------------------
> target/m68k/m68k-semi.c | 4 ++--
> target/m68k/op_helper.c | 12 ++++++------
> target/m68k/translate.c | 4 +---
> 8 files changed, 24 insertions(+), 41 deletions(-)
>
> diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h
> index 7a26f3c3fc..bc7446fbaf 100644
> --- a/linux-user/m68k/target_cpu.h
> +++ b/linux-user/m68k/target_cpu.h
> @@ -31,7 +31,7 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp)
>
> static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls)
> {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
>
> ts->tp_value = newtls;
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 43ef30b7cb..f8d5a0819b 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -163,11 +163,6 @@ struct M68kCPU {
> CPUM68KState env;
> };
>
> -static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
> -{
> - return container_of(env, M68kCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(M68kCPU, env)
>
> void m68k_cpu_do_interrupt(CPUState *cpu);
> diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c
> index 34d332d8b1..9bc6ff3d3a 100644
> --- a/linux-user/m68k-sim.c
> +++ b/linux-user/m68k-sim.c
> @@ -91,7 +91,6 @@ static int translate_openflags(int flags)
> #define ARG(x) tswap32(args[x])
> void do_m68k_simcall(CPUM68KState *env, int nr)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> uint32_t *args;
>
> args = (uint32_t *)(unsigned long)(env->aregs[7] + 4);
> @@ -159,6 +158,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr)
> check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2)));
> break;
> default:
> - cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr);
> + cpu_abort(env_cpu(env), "Unsupported m68k sim syscall %d\n", nr);
> }
> }
> diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
> index 42d8d841ea..f2c33057b3 100644
> --- a/linux-user/m68k/cpu_loop.c
> +++ b/linux-user/m68k/cpu_loop.c
> @@ -23,7 +23,7 @@
>
> void cpu_loop(CPUM68KState *env)
> {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> unsigned int n;
> target_siginfo_t info;
> diff --git a/target/m68k/helper.c b/target/m68k/helper.c
> index d958a34959..6699f056a4 100644
> --- a/target/m68k/helper.c
> +++ b/target/m68k/helper.c
> @@ -168,8 +168,6 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
>
> void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> -
> switch (reg) {
> case M68K_CR_CACR:
> env->cacr = val;
> @@ -186,7 +184,7 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
> break;
> /* TODO: Implement control registers. */
> default:
> - cpu_abort(CPU(cpu),
> + cpu_abort(env_cpu(env),
> "Unimplemented control register write 0x%x = 0x%x\n",
> reg, val);
> }
> @@ -194,8 +192,6 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
>
> void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> -
> switch (reg) {
> /* MC680[1234]0 */
> case M68K_CR_SFC:
> @@ -248,14 +244,13 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
> env->mmu.ttr[M68K_DTTR1] = val;
> return;
> }
> - cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n",
> + cpu_abort(env_cpu(env),
> + "Unimplemented control register write 0x%x = 0x%x\n",
> reg, val);
> }
>
> uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> -
> switch (reg) {
> /* MC680[1234]0 */
> case M68K_CR_SFC:
> @@ -292,7 +287,7 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
> case M68K_CR_DTT1:
> return env->mmu.ttr[M68K_DTTR1];
> }
> - cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n",
> + cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
> reg);
> }
>
> @@ -401,8 +396,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer)
> uint32_t last_logical, last_physical;
> int32_t size;
> int last_attr = -1, attr = -1;
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
> /* 8k page */
> @@ -635,8 +629,7 @@ static int get_physical_address(CPUM68KState *env, hwaddr *physical,
> int *prot, target_ulong address,
> int access_type, target_ulong *page_size)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> uint32_t entry;
> uint32_t next;
> target_ulong page_mask;
> @@ -1128,7 +1121,7 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc)
> z = n; \
> break; \
> default: \
> - cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); \
> + cpu_abort(env_cpu(env), "Bad CC_OP %d", op); \
> } \
> } while (0)
>
> @@ -1311,8 +1304,6 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc)
> #if defined(CONFIG_SOFTMMU)
> void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> hwaddr physical;
> int access_type;
> int prot;
> @@ -1337,7 +1328,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
> if (ret == 0) {
> addr &= TARGET_PAGE_MASK;
> physical += addr & (page_size - 1);
> - tlb_set_page(cs, addr, physical,
> + tlb_set_page(env_cpu(env), addr, physical,
> prot, access_type & ACCESS_SUPER ?
> MMU_KERNEL_IDX : MMU_USER_IDX, page_size);
> }
> @@ -1345,18 +1336,18 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
>
> void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> + CPUState *cs = env_cpu(env);
>
> switch (opmode) {
> case 0: /* Flush page entry if not global */
> case 1: /* Flush page entry */
> - tlb_flush_page(CPU(cpu), addr);
> + tlb_flush_page(cs, addr);
> break;
> case 2: /* Flush all except global entries */
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> break;
> case 3: /* Flush all entries */
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> break;
> }
> }
> diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c
> index 1402145c8f..6716b93b5a 100644
> --- a/target/m68k/m68k-semi.c
> +++ b/target/m68k/m68k-semi.c
> @@ -421,7 +421,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
> case HOSTED_INIT_SIM:
> #if defined(CONFIG_USER_ONLY)
> {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> TaskState *ts = cs->opaque;
> /* Allocate the heap using sbrk. */
> if (!ts->heap_limit) {
> @@ -454,7 +454,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
> #endif
> return;
> default:
> - cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr);
> + cpu_abort(env_cpu(env), "Unsupported semihosting syscall %d\n", nr);
> result = 0;
> }
> failed:
> diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
> index 13fcaa74ef..39aa9310e1 100644
> --- a/target/m68k/op_helper.c
> +++ b/target/m68k/op_helper.c
> @@ -211,7 +211,7 @@ static const char *m68k_exception_name(int index)
>
> static void cf_interrupt_all(CPUM68KState *env, int is_hw)
> {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t sp;
> uint32_t sr;
> uint32_t fmt;
> @@ -289,7 +289,7 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
> {
> if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) {
> /* all except 68000 */
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> switch (format) {
> case 4:
> *sp -= 4;
> @@ -314,7 +314,7 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
>
> static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
> {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t sp;
> uint32_t retaddr;
> uint32_t vector;
> @@ -526,7 +526,7 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>
> static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
> {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = tt;
> cpu_loop_exit_restore(cs, raddr);
> @@ -1056,7 +1056,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub)
> env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0;
>
> if (val < 0 || val > ub) {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> /* Recover PC and CC_OP for the beginning of the insn. */
> cpu_restore_state(cs, GETPC(), true);
> @@ -1087,7 +1087,7 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub)
> env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb;
>
> if (env->cc_c) {
> - CPUState *cs = CPU(m68k_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> /* Recover PC and CC_OP for the beginning of the insn. */
> cpu_restore_state(cs, GETPC(), true);
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index 58596278c2..e206b5e78a 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -4778,14 +4778,12 @@ DISAS_INSN(wddata)
>
> DISAS_INSN(wdebug)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> -
> if (IS_USER(s)) {
> gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
> return;
> }
> /* TODO: Implement wdebug. */
> - cpu_abort(CPU(cpu), "WDEBUG not implemented");
> + cpu_abort(env_cpu(env), "WDEBUG not implemented");
> }
> #endif
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 19/39] target/moxie: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 19/39] target/moxie: " Richard Henderson
@ 2019-05-09 18:19 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:19 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:20 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/moxie/cpu.h | 5 -----
> target/moxie/helper.c | 6 +++---
> target/moxie/translate.c | 2 +-
> 3 files changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
> index 5b9aae95d2..a481a92833 100644
> --- a/target/moxie/cpu.h
> +++ b/target/moxie/cpu.h
> @@ -90,11 +90,6 @@ typedef struct MoxieCPU {
> CPUMoxieState env;
> } MoxieCPU;
>
> -static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
> -{
> - return container_of(env, MoxieCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(MoxieCPU, env)
>
> void moxie_cpu_do_interrupt(CPUState *cs);
> diff --git a/target/moxie/helper.c b/target/moxie/helper.c
> index 287a45232c..a18b21c4c0 100644
> --- a/target/moxie/helper.c
> +++ b/target/moxie/helper.c
> @@ -42,7 +42,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
>
> void helper_raise_exception(CPUMoxieState *env, int ex)
> {
> - CPUState *cs = CPU(moxie_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = ex;
> /* Stash the exception type. */
> @@ -79,7 +79,7 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
>
> void helper_debug(CPUMoxieState *env)
> {
> - CPUState *cs = CPU(moxie_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = EXCP_DEBUG;
> cpu_loop_exit(cs);
> @@ -89,7 +89,7 @@ void helper_debug(CPUMoxieState *env)
>
> void moxie_cpu_do_interrupt(CPUState *cs)
> {
> - CPUState *cs = CPU(moxie_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = -1;
> }
> diff --git a/target/moxie/translate.c b/target/moxie/translate.c
> index c668178f2c..c87e9ec2b1 100644
> --- a/target/moxie/translate.c
> +++ b/target/moxie/translate.c
> @@ -816,7 +816,7 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
> void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
> {
> CPUMoxieState *env = cs->env_ptr;
> - MoxieCPU *cpu = moxie_env_get_cpu(env);
> + MoxieCPU *cpu = env_archcpu(env);
> DisasContext ctx;
> target_ulong pc_start;
> int num_insns;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 20/39] target/nios2: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 20/39] target/nios2: " Richard Henderson
@ 2019-05-09 18:20 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:22 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/nios2/cpu.h | 5 -----
> hw/nios2/cpu_pic.c | 5 +----
> target/nios2/mmu.c | 10 +++++-----
> 3 files changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index b14095b8dc..f2ffc1469f 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -193,11 +193,6 @@ typedef struct Nios2CPU {
> uint32_t fast_tlb_miss_addr;
> } Nios2CPU;
>
> -static inline Nios2CPU *nios2_env_get_cpu(CPUNios2State *env)
> -{
> - return NIOS2_CPU(container_of(env, Nios2CPU, env));
> -}
> -
> #define ENV_OFFSET offsetof(Nios2CPU, env)
>
> void nios2_tcg_init(void);
> diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c
> index 6bccce2f32..9e39955bd1 100644
> --- a/hw/nios2/cpu_pic.c
> +++ b/hw/nios2/cpu_pic.c
> @@ -54,12 +54,9 @@ static void nios2_pic_cpu_handler(void *opaque, int irq, int level)
>
> void nios2_check_interrupts(CPUNios2State *env)
> {
> - Nios2CPU *cpu = nios2_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> -
> if (env->irq_pending) {
> env->irq_pending = 0;
> - cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
> }
> }
>
> diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
> index 33382bad1b..61eaa06b3e 100644
> --- a/target/nios2/mmu.c
> +++ b/target/nios2/mmu.c
> @@ -73,7 +73,7 @@ unsigned int mmu_translate(CPUNios2State *env,
> Nios2MMULookup *lu,
> target_ulong vaddr, int rw, int mmu_idx)
> {
> - Nios2CPU *cpu = nios2_env_get_cpu(env);
> + Nios2CPU *cpu = env_archcpu(env);
> int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
> int vpn = vaddr >> 12;
>
> @@ -115,7 +115,7 @@ unsigned int mmu_translate(CPUNios2State *env,
> static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
> {
> CPUState *cs = env_cpu(env);
> - Nios2CPU *cpu = nios2_env_get_cpu(env);
> + Nios2CPU *cpu = env_archcpu(env);
> int idx;
> MMU_LOG(qemu_log("TLB Flush PID %d\n", pid));
>
> @@ -139,7 +139,7 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
> void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
> {
> CPUState *cs = env_cpu(env);
> - Nios2CPU *cpu = nios2_env_get_cpu(env);
> + Nios2CPU *cpu = env_archcpu(env);
>
> MMU_LOG(qemu_log("mmu_write %08X = %08X\n", rn, v));
>
> @@ -256,7 +256,7 @@ void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
>
> void mmu_init(CPUNios2State *env)
> {
> - Nios2CPU *cpu = nios2_env_get_cpu(env);
> + Nios2CPU *cpu = env_archcpu(env);
> Nios2MMU *mmu = &env->mmu;
>
> MMU_LOG(qemu_log("mmu_init\n"));
> @@ -267,7 +267,7 @@ void mmu_init(CPUNios2State *env)
>
> void dump_mmu(CPUNios2State *env)
> {
> - Nios2CPU *cpu = nios2_env_get_cpu(env);
> + Nios2CPU *cpu = env_archcpu(env);
> int i;
>
> qemu_printf("MMU: ways %d, entries %d, pid bits %d\n",
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 21/39] target/openrisc: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 21/39] target/openrisc: " Richard Henderson
@ 2019-05-09 18:20 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:22 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/openrisc/cpu.h | 5 -----
> linux-user/openrisc/cpu_loop.c | 2 +-
> target/openrisc/exception_helper.c | 5 ++---
> target/openrisc/sys_helper.c | 8 ++++----
> 4 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 0ba4ae3356..91ba667139 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -317,11 +317,6 @@ typedef struct OpenRISCCPU {
>
> } OpenRISCCPU;
>
> -static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
> -{
> - return container_of(env, OpenRISCCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(OpenRISCCPU, env)
>
> void cpu_openrisc_list(void);
> diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c
> index f496e4b48a..4b8165b261 100644
> --- a/linux-user/openrisc/cpu_loop.c
> +++ b/linux-user/openrisc/cpu_loop.c
> @@ -23,7 +23,7 @@
>
> void cpu_loop(CPUOpenRISCState *env)
> {
> - CPUState *cs = CPU(openrisc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> abi_long ret;
> target_siginfo_t info;
> diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception_helper.c
> index 6073a5b21c..dd639ba5f2 100644
> --- a/target/openrisc/exception_helper.c
> +++ b/target/openrisc/exception_helper.c
> @@ -25,15 +25,14 @@
>
> void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
> {
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> + OpenRISCCPU *cpu = env_archcpu(env);
>
> raise_exception(cpu, excp);
> }
>
> static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc)
> {
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = EXCP_RANGE;
> cpu_loop_exit_restore(cs, pc);
> diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
> index 05f66c455b..8f11cb8202 100644
> --- a/target/openrisc/sys_helper.c
> +++ b/target/openrisc/sys_helper.c
> @@ -30,8 +30,8 @@
> void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
> {
> #ifndef CONFIG_USER_ONLY
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + OpenRISCCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
> target_ulong mr;
> int idx;
>
> @@ -194,8 +194,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
> target_ulong spr)
> {
> #ifndef CONFIG_USER_ONLY
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + OpenRISCCPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
> int idx;
>
> switch (spr) {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 22/39] target/ppc: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 22/39] target/ppc: " Richard Henderson
@ 2019-05-09 18:28 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:27 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/ppc/cpu.h | 7 +-
> target/ppc/helper_regs.h | 4 +-
> hw/ppc/ppc.c | 18 ++---
> hw/ppc/ppc405_uc.c | 2 +-
> hw/ppc/ppc_booke.c | 4 +-
> linux-user/ppc/cpu_loop.c | 2 +-
> target/ppc/excp_helper.c | 14 ++--
> target/ppc/fpu_helper.c | 14 ++--
> target/ppc/kvm.c | 5 +-
> target/ppc/misc_helper.c | 22 ++----
> target/ppc/mmu-hash64.c | 14 ++--
> target/ppc/mmu_helper.c | 115 +++++++++++++-------------------
> target/ppc/translate_init.inc.c | 85 ++++++++++++-----------
> 13 files changed, 134 insertions(+), 172 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 3449b0b085..ef00a3415d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1203,11 +1203,6 @@ struct PowerPCCPU {
> int32_t mig_slb_nr;
> };
>
> -static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
> -{
> - return container_of(env, PowerPCCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(PowerPCCPU, env)
>
> PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
> @@ -2451,7 +2446,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
> }
> }
>
> - cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
> + cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
> return 0;
> }
>
> diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
> index 922da76c6c..85dfe7687f 100644
> --- a/target/ppc/helper_regs.h
> +++ b/target/ppc/helper_regs.h
> @@ -116,7 +116,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> {
> int excp;
> #if !defined(CONFIG_USER_ONLY)
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> #endif
>
> excp = 0;
> @@ -175,7 +175,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> #if !defined(CONFIG_USER_ONLY)
> static inline void check_tlb_flush(CPUPPCState *env, bool global)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> /* Handle global flushes first */
> if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index ad20584f26..debcdab993 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -385,7 +385,7 @@ void ppc40x_system_reset(PowerPCCPU *cpu)
>
> void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
>
> switch ((val >> 28) & 0x3) {
> case 0x0:
> @@ -785,7 +785,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env)
>
> target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> ppc_tb_t *tb_env = env->tb_env;
> uint64_t hdecr;
> @@ -923,7 +923,7 @@ static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr,
>
> void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> int nr_bits = 32;
>
> @@ -955,7 +955,7 @@ static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr,
>
> void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>
> _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value,
> @@ -980,7 +980,7 @@ static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
> static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
> {
> CPUPPCState *env = opaque;
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> ppc_tb_t *tb_env = env->tb_env;
>
> tb_env->tb_freq = freq;
> @@ -1095,7 +1095,7 @@ const VMStateDescription vmstate_ppc_timebase = {
> /* Set up (once) timebase frequency (in Hz) */
> clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> ppc_tb_t *tb_env;
>
> tb_env = g_malloc0(sizeof(ppc_tb_t));
> @@ -1165,7 +1165,7 @@ static void cpu_4xx_fit_cb (void *opaque)
> uint64_t now, next;
>
> env = opaque;
> - cpu = ppc_env_get_cpu(env);
> + cpu = env_archcpu(env);
> tb_env = env->tb_env;
> ppc40x_timer = tb_env->opaque;
> now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> @@ -1235,7 +1235,7 @@ static void cpu_4xx_pit_cb (void *opaque)
> ppc40x_timer_t *ppc40x_timer;
>
> env = opaque;
> - cpu = ppc_env_get_cpu(env);
> + cpu = env_archcpu(env);
> tb_env = env->tb_env;
> ppc40x_timer = tb_env->opaque;
> env->spr[SPR_40x_TSR] |= 1 << 27;
> @@ -1261,7 +1261,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
> uint64_t now, next;
>
> env = opaque;
> - cpu = ppc_env_get_cpu(env);
> + cpu = env_archcpu(env);
> tb_env = env->tb_env;
> ppc40x_timer = tb_env->opaque;
> now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 3ae7f6d4df..018dcca888 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -49,7 +49,7 @@
> ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
> uint32_t flags)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> ram_addr_t bdloc;
> int i, n;
>
> diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c
> index 4f11e00a17..323413e074 100644
> --- a/hw/ppc/ppc_booke.c
> +++ b/hw/ppc/ppc_booke.c
> @@ -249,7 +249,7 @@ static void booke_wdt_cb(void *opaque)
>
> void store_booke_tsr(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> ppc_tb_t *tb_env = env->tb_env;
> booke_timer_t *booke_timer = tb_env->opaque;
>
> @@ -277,7 +277,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val)
>
> void store_booke_tcr(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> ppc_tb_t *tb_env = env->tb_env;
> booke_timer_t *booke_timer = tb_env->opaque;
>
> diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
> index 801f5ace29..24dfdba854 100644
> --- a/linux-user/ppc/cpu_loop.c
> +++ b/linux-user/ppc/cpu_loop.c
> @@ -67,7 +67,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
>
> void cpu_loop(CPUPPCState *env)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_siginfo_t info;
> int trapnr;
> target_ulong ret;
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index ec2c177091..50b004d00d 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -49,7 +49,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
>
> static void ppc_hw_interrupt(CPUPPCState *env)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
> @@ -792,7 +792,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
>
> static void ppc_hw_interrupt(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> bool async_deliver;
>
> /* External reset */
> @@ -931,7 +931,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
> * It generally means a discrepancy between the wakup conditions in the
> * processor has_work implementation and the logic in this function.
> */
> - cpu_abort(CPU(ppc_env_get_cpu(env)),
> + cpu_abort(env_cpu(env),
> "Wakeup from PM state but interrupt Undelivered");
> }
> }
> @@ -974,7 +974,7 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
> void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
> uint32_t error_code, uintptr_t raddr)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = exception;
> env->error_code = error_code;
> @@ -1015,7 +1015,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)
> uint32_t excp = hreg_store_msr(env, val, 0);
>
> if (excp != 0) {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> cpu_interrupt_exittb(cs);
> raise_exception(env, excp);
> }
> @@ -1026,7 +1026,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
> {
> CPUState *cs;
>
> - cs = CPU(ppc_env_get_cpu(env));
> + cs = env_cpu(env);
> cs->halted = 1;
>
> /*
> @@ -1043,7 +1043,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
>
> static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> /* MSR:POW cannot be set by any form of rfi */
> msr &= ~(1ULL << MSR_POW);
> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> index 0b7308f539..ffbd19afa1 100644
> --- a/target/ppc/fpu_helper.c
> +++ b/target/ppc/fpu_helper.c
> @@ -271,7 +271,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
> env->fpscr |= FP_FX;
> /* We must update the target FPR before raising the exception */
> if (fpscr_ve != 0) {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = POWERPC_EXCP_PROGRAM;
> env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
> @@ -315,7 +315,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
>
> static inline void float_overflow_excp(CPUPPCState *env)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->fpscr |= 1 << FPSCR_OX;
> /* Update the floating-point exception summary */
> @@ -335,7 +335,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
>
> static inline void float_underflow_excp(CPUPPCState *env)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->fpscr |= 1 << FPSCR_UX;
> /* Update the floating-point exception summary */
> @@ -352,7 +352,7 @@ static inline void float_underflow_excp(CPUPPCState *env)
>
> static inline void float_inexact_excp(CPUPPCState *env)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->fpscr |= 1 << FPSCR_FI;
> env->fpscr |= 1 << FPSCR_XX;
> @@ -442,7 +442,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
>
> void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int prev;
>
> prev = (env->fpscr >> bit) & 1;
> @@ -574,7 +574,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
>
> void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong prev, new;
> int i;
>
> @@ -612,7 +612,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
>
> static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int status = get_float_exception_flags(&env->fp_status);
> bool inexact_happened = false;
>
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 02e22e2017..4228cddcdc 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -1989,9 +1989,8 @@ static int kvmppc_get_dec_bits(void)
> }
>
> static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
> - {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> +{
> + CPUState *cs = env_cpu(env);
>
> if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
> !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 0a81e98ee9..49a8a02363 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -81,28 +81,24 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
>
> void helper_store_sdr1(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> if (env->spr[SPR_SDR1] != val) {
> ppc_store_sdr1(env, val);
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> }
>
> #if defined(TARGET_PPC64)
> void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> if (env->spr[SPR_PTCR] != val) {
> ppc_store_ptcr(env, val);
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> }
>
> void helper_store_pcr(CPUPPCState *env, target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>
> env->spr[SPR_PCR] = value & pcc->pcr_mask;
> @@ -111,16 +107,12 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value)
>
> void helper_store_pidr(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> env->spr[SPR_BOOKS_PID] = val;
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void helper_store_lpidr(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> env->spr[SPR_LPIDR] = val;
>
> /*
> @@ -129,7 +121,7 @@ void helper_store_lpidr(CPUPPCState *env, target_ulong val)
> * potentially access and cache entries for the current LPID as
> * well.
> */
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
> @@ -151,12 +143,10 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
>
> void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> if (likely(env->pb[num] != value)) {
> env->pb[num] = value;
> /* Should be optimized */
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> }
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 7899eb2918..da8966ccf5 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -96,7 +96,7 @@ void dump_slb(PowerPCCPU *cpu)
>
> void helper_slbia(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> int n;
>
> /* XXX: Warning: slbia never invalidates the first segment */
> @@ -118,7 +118,7 @@ void helper_slbia(CPUPPCState *env)
> static void __helper_slbie(CPUPPCState *env, target_ulong addr,
> target_ulong global)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> ppc_slb_t *slb;
>
> slb = slb_lookup(cpu, addr);
> @@ -251,7 +251,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
>
> void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
>
> if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
> raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
> @@ -261,7 +261,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
>
> target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> target_ulong rt = 0;
>
> if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
> @@ -273,7 +273,7 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
>
> target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> target_ulong rt = 0;
>
> if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
> @@ -285,7 +285,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
>
> target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> target_ulong rt = 0;
>
> if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
> @@ -1163,7 +1163,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
>
> void helper_store_lpcr(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
>
> ppc_store_lpcr(cpu, val);
> }
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index b32693f24e..44afcee461 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -239,7 +239,6 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
>
> static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppc6xx_tlb_t *tlb;
> int nr, max;
>
> @@ -253,7 +252,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
> tlb = &env->tlb.tlb6[nr];
> pte_invalidate(&tlb->pte0);
> }
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> @@ -261,7 +260,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> int is_code, int match_epn)
> {
> #if !defined(FLUSH_ALL_TLBS)
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> ppc6xx_tlb_t *tlb;
> int way, nr;
>
> @@ -474,7 +473,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
> static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
> target_ulong eaddr, int rw, int type)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> hwaddr hash;
> target_ulong vsid;
> int ds, pr, target_page_bits;
> @@ -670,7 +669,6 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
> /* Helpers specific to PowerPC 40x implementations */
> static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppcemb_tlb_t *tlb;
> int i;
>
> @@ -678,7 +676,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
> tlb = &env->tlb.tlbe[i];
> tlb->prot &= ~PAGE_VALID;
> }
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> @@ -749,11 +747,10 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>
> void store_40x_sler(CPUPPCState *env, uint32_t val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> /* XXX: TO BE FIXED */
> if (val != 0x00000000) {
> - cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n");
> + cpu_abort(env_cpu(env),
> + "Little-endian regions are not supported by now\n");
> }
> env->spr[SPR_405_SLER] = val;
> }
> @@ -863,7 +860,6 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> static void booke206_flush_tlb(CPUPPCState *env, int flags,
> const int check_iprot)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int tlb_size;
> int i, j;
> ppcmas_tlb_t *tlb = env->tlb.tlbm;
> @@ -880,7 +876,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
> tlb += booke206_tlb_size(env, i);
> }
>
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
> @@ -1275,7 +1271,7 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type)
>
> static void mmu6xx_dump_mmu(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> ppc6xx_tlb_t *tlb;
> target_ulong sr;
> int type, way, entry, i;
> @@ -1347,13 +1343,13 @@ void dump_mmu(CPUPPCState *env)
> case POWERPC_MMU_2_03:
> case POWERPC_MMU_2_06:
> case POWERPC_MMU_2_07:
> - dump_slb(ppc_env_get_cpu(env));
> + dump_slb(env_archcpu(env));
> break;
> case POWERPC_MMU_3_00:
> - if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
> + if (ppc64_v3_radix(env_archcpu(env))) {
> /* TODO - Unsupported */
> } else {
> - dump_slb(ppc_env_get_cpu(env));
> + dump_slb(env_archcpu(env));
> break;
> }
> #endif
> @@ -1419,7 +1415,6 @@ static int get_physical_address_wtlb(
> target_ulong eaddr, int rw, int access_type,
> int mmu_idx)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int ret = -1;
> bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
> || (access_type != ACCESS_CODE && msr_dr == 0);
> @@ -1460,18 +1455,18 @@ static int get_physical_address_wtlb(
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_REAL:
> if (real_mode) {
> ret = check_physical(env, ctx, eaddr, rw);
> } else {
> - cpu_abort(CPU(cpu),
> + cpu_abort(env_cpu(env),
> "PowerPC in real mode do not do any translation\n");
> }
> return -1;
> default:
> - cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n");
> + cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n");
> return -1;
> }
>
> @@ -1583,7 +1578,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
> static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> int rw, int mmu_idx)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> mmu_ctx_t ctx;
> int access_type;
> @@ -1815,7 +1810,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
> target_ulong mask)
> {
> - CPUState *cs = CPU(ppc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong base, end, page;
>
> base = BATu & ~0x0001FFFF;
> @@ -1847,7 +1842,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
> {
> target_ulong mask;
> #if defined(FLUSH_ALL_TLBS)
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> #endif
>
> dump_store_bat(env, 'I', 0, nr, value);
> @@ -1868,7 +1863,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
> #if !defined(FLUSH_ALL_TLBS)
> do_invalidate_BAT(env, env->IBAT[0][nr], mask);
> #else
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> #endif
> }
> }
> @@ -1883,7 +1878,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
> {
> target_ulong mask;
> #if defined(FLUSH_ALL_TLBS)
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> #endif
>
> dump_store_bat(env, 'D', 0, nr, value);
> @@ -1904,7 +1899,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value)
> #if !defined(FLUSH_ALL_TLBS)
> do_invalidate_BAT(env, env->DBAT[0][nr], mask);
> #else
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> #endif
> }
> }
> @@ -1919,7 +1914,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
> {
> target_ulong mask;
> #if defined(FLUSH_ALL_TLBS)
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> int do_inval;
> #endif
>
> @@ -1953,7 +1948,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
> }
> #if defined(FLUSH_ALL_TLBS)
> if (do_inval) {
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> #endif
> }
> @@ -1964,7 +1959,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
> #if !defined(FLUSH_ALL_TLBS)
> target_ulong mask;
> #else
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> int do_inval;
> #endif
>
> @@ -1993,7 +1988,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
> env->DBAT[1][nr] = value;
> #if defined(FLUSH_ALL_TLBS)
> if (do_inval) {
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> #endif
> }
> @@ -2003,12 +1998,10 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
> /* TLB management */
> void ppc_tlb_invalidate_all(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> #if defined(TARGET_PPC64)
> if (env->mmu_model & POWERPC_MMU_64) {
> env->tlb_need_flush = 0;
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> } else
> #endif /* defined(TARGET_PPC64) */
> switch (env->mmu_model) {
> @@ -2021,14 +2014,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> ppc4xx_tlb_invalidate_all(env);
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
> + cpu_abort(env_cpu(env), "No TLB for PowerPC 4xx in real mode\n");
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE:
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> break;
> case POWERPC_MMU_BOOKE206:
> booke206_flush_tlb(env, -1, 0);
> @@ -2036,11 +2029,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> case POWERPC_MMU_32B:
> case POWERPC_MMU_601:
> env->tlb_need_flush = 0;
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> break;
> default:
> /* XXX: TODO */
> - cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model);
> + cpu_abort(env_cpu(env), "Unknown MMU model %x\n", env->mmu_model);
> break;
> }
> }
> @@ -2091,7 +2084,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> /* Special registers manipulation */
> void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
> assert(!cpu->vhyp);
> #if defined(TARGET_PPC64)
> @@ -2118,7 +2111,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> #if defined(TARGET_PPC64)
> void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
> target_ulong patbsize = value & PTCR_PATS;
>
> @@ -2163,7 +2156,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
> (int)srnum, value, env->sr[srnum]);
> #if defined(TARGET_PPC64)
> if (env->mmu_model & POWERPC_MMU_64) {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + PowerPCCPU *cpu = env_archcpu(env);
> uint64_t esid, vsid;
>
> /* ESID = srnum */
> @@ -2190,7 +2183,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
> page = (16 << 20) * srnum;
> end = page + (16 << 20);
> for (; page != end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(CPU(cpu), page);
> + tlb_flush_page(env_cpu(env), page);
> }
> }
> #else
> @@ -2212,12 +2205,10 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr)
>
> void helper_tlbiva(CPUPPCState *env, target_ulong addr)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> /* tlbiva instruction only exists on BookE */
> assert(env->mmu_model == POWERPC_MMU_BOOKE);
> /* XXX: TODO */
> - cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
> + cpu_abort(env_cpu(env), "BookE MMU model is not implemented\n");
> }
>
> /* Software driven TLBs management */
> @@ -2433,8 +2424,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry)
> void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> ppcemb_tlb_t *tlb;
> target_ulong page, end;
>
> @@ -2529,7 +2519,6 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
> void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
> target_ulong value)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppcemb_tlb_t *tlb;
> target_ulong EPN, RPN, size;
> int do_flush_tlbs;
> @@ -2565,13 +2554,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
> }
> tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
> if (do_flush_tlbs) {
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> break;
> case 1:
> RPN = value & 0xFFFFFC0F;
> if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> tlb->RPN = RPN;
> break;
> @@ -2665,7 +2654,6 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address)
>
> static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg = 0;
> int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT;
> int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK);
> @@ -2675,7 +2663,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
> tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb];
>
> if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) {
> - cpu_abort(CPU(cpu), "we don't support HES yet\n");
> + cpu_abort(env_cpu(env), "we don't support HES yet\n");
> }
>
> return booke206_get_tlbm(env, tlb, ea, esel);
> @@ -2683,40 +2671,33 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
>
> void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> env->spr[pidn] = pid;
> /* changing PIDs mean we're in a different address space now */
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void helper_booke_set_eplc(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> env->spr[SPR_BOOKE_EPLC] = val & EPID_MASK;
> - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD);
> + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_LOAD);
> }
> void helper_booke_set_epsc(CPUPPCState *env, target_ulong val)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> env->spr[SPR_BOOKE_EPSC] = val & EPID_MASK;
> - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE);
> + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_STORE);
> }
>
> static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> -
> if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
> - tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
> + tlb_flush_page(env_cpu(env), tlb->mas2 & MAS2_EPN_MASK);
> } else {
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> }
>
> void helper_booke206_tlbwe(CPUPPCState *env)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg, tlbn;
> ppcmas_tlb_t *tlb;
> uint32_t size_tlb, size_ps;
> @@ -2770,7 +2751,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
> }
>
> if (msr_gs) {
> - cpu_abort(CPU(cpu), "missing HV implementation\n");
> + cpu_abort(env_cpu(env), "missing HV implementation\n");
> }
>
> if (tlb->mas1 & MAS1_VALID) {
> @@ -2968,7 +2949,6 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address)
>
> void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int i, j;
> int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
> ppcmas_tlb_t *tlb = env->tlb.tlbm;
> @@ -2985,12 +2965,11 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
> }
> tlb += booke206_tlb_size(env, i);
> }
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int i, j;
> ppcmas_tlb_t *tlb;
> int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
> @@ -3026,7 +3005,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
> tlb->mas1 &= ~MAS1_VALID;
> }
> }
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type)
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 0394a9ddad..6343e25624 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -3432,7 +3432,7 @@ static void init_proc_401(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(12, 16, 20, 24);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3486,7 +3486,7 @@ static void init_proc_401x2(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(12, 16, 20, 24);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3538,7 +3538,7 @@ static void init_proc_401x3(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(12, 16, 20, 24);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3597,7 +3597,7 @@ static void init_proc_IOP480(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(8, 12, 16, 20);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3648,7 +3648,7 @@ static void init_proc_403(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(8, 12, 16, 20);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3714,7 +3714,7 @@ static void init_proc_403GCX(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(8, 12, 16, 20);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3780,7 +3780,7 @@ static void init_proc_405(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(8, 12, 16, 20);
> SET_WDT_PERIOD(16, 20, 24, 28);
> @@ -3878,7 +3878,7 @@ static void init_proc_440EP(CPUPPCState *env)
> init_excp_BookE(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(12, 16, 20, 24);
> SET_WDT_PERIOD(20, 24, 28, 32);
> @@ -4186,7 +4186,7 @@ static void init_proc_440x5(CPUPPCState *env)
> init_excp_BookE(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> - ppc40x_irq_init(ppc_env_get_cpu(env));
> + ppc40x_irq_init(env_archcpu(env));
>
> SET_FIT_PERIOD(12, 16, 20, 24);
> SET_WDT_PERIOD(20, 24, 28, 32);
> @@ -4392,7 +4392,7 @@ static void init_proc_G2(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
> @@ -4472,7 +4472,7 @@ static void init_proc_G2LE(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
> @@ -4727,7 +4727,7 @@ static void init_proc_e300(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
> @@ -4805,7 +4805,6 @@ enum fsl_e500_version {
>
> static void init_proc_e500(CPUPPCState *env, int version)
> {
> - PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg[2];
> uint64_t ivor_mask;
> uint64_t ivpr_mask = 0xFFFF0000ULL;
> @@ -4877,7 +4876,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
> tlbncfg[1] = 0x40028040;
> break;
> default:
> - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
> + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> }
> #endif
> @@ -4902,7 +4901,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
> l1cfg1 |= 0x0B83820;
> break;
> default:
> - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n",
> + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
> env->spr[SPR_PVR]);
> }
> gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
> @@ -5018,7 +5017,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
>
> init_excp_e200(env, ivpr_mask);
> /* Allocate hardware IRQ controller */
> - ppce500_irq_init(ppc_env_get_cpu(env));
> + ppce500_irq_init(env_archcpu(env));
> }
>
> static void init_proc_e500v1(CPUPPCState *env)
> @@ -5291,7 +5290,7 @@ static void init_proc_601(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 64;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
> @@ -5396,7 +5395,7 @@ static void init_proc_602(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
> @@ -5466,7 +5465,7 @@ static void init_proc_603(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
> @@ -5533,7 +5532,7 @@ static void init_proc_603E(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
> @@ -5594,7 +5593,7 @@ static void init_proc_604(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
> @@ -5678,7 +5677,7 @@ static void init_proc_604E(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
> @@ -5749,7 +5748,7 @@ static void init_proc_740(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
> @@ -5829,7 +5828,7 @@ static void init_proc_750(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
> @@ -5993,7 +5992,7 @@ static void init_proc_750cl(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
> @@ -6115,7 +6114,7 @@ static void init_proc_750cx(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
> @@ -6203,7 +6202,7 @@ static void init_proc_750fx(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
> @@ -6291,7 +6290,7 @@ static void init_proc_750gx(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
> @@ -6370,7 +6369,7 @@ static void init_proc_745(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
> @@ -6457,7 +6456,7 @@ static void init_proc_755(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
> @@ -6527,7 +6526,7 @@ static void init_proc_7400(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
> @@ -6612,7 +6611,7 @@ static void init_proc_7410(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
> @@ -6723,7 +6722,7 @@ static void init_proc_7440(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
> @@ -6857,7 +6856,7 @@ static void init_proc_7450(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
> @@ -6994,7 +6993,7 @@ static void init_proc_7445(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
> @@ -7133,7 +7132,7 @@ static void init_proc_7455(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
> @@ -7296,7 +7295,7 @@ static void init_proc_7457(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
> @@ -7434,7 +7433,7 @@ static void init_proc_e600(CPUPPCState *env)
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> /* Allocate hardware IRQ controller */
> - ppc6xx_irq_init(ppc_env_get_cpu(env));
> + ppc6xx_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
> @@ -8298,7 +8297,7 @@ static void init_proc_970(CPUPPCState *env)
>
> /* Allocate hardware IRQ controller */
> init_excp_970(env);
> - ppc970_irq_init(ppc_env_get_cpu(env));
> + ppc970_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> @@ -8372,7 +8371,7 @@ static void init_proc_power5plus(CPUPPCState *env)
>
> /* Allocate hardware IRQ controller */
> init_excp_970(env);
> - ppc970_irq_init(ppc_env_get_cpu(env));
> + ppc970_irq_init(env_archcpu(env));
> }
>
> POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> @@ -8487,7 +8486,7 @@ static void init_proc_POWER7(CPUPPCState *env)
>
> /* Allocate hardware IRQ controller */
> init_excp_POWER7(env);
> - ppcPOWER7_irq_init(ppc_env_get_cpu(env));
> + ppcPOWER7_irq_init(env_archcpu(env));
> }
>
> static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
> @@ -8639,7 +8638,7 @@ static void init_proc_POWER8(CPUPPCState *env)
>
> /* Allocate hardware IRQ controller */
> init_excp_POWER8(env);
> - ppcPOWER7_irq_init(ppc_env_get_cpu(env));
> + ppcPOWER7_irq_init(env_archcpu(env));
> }
>
> static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
> @@ -8838,7 +8837,7 @@ static void init_proc_POWER9(CPUPPCState *env)
>
> /* Allocate hardware IRQ controller */
> init_excp_POWER9(env);
> - ppcPOWER9_irq_init(ppc_env_get_cpu(env));
> + ppcPOWER9_irq_init(env_archcpu(env));
> }
>
> static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 24/39] target/s390x: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 24/39] target/s390x: " Richard Henderson
@ 2019-05-09 18:31 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 18:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:23 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/s390x/cpu.h | 5 ----
> linux-user/s390x/cpu_loop.c | 2 +-
> target/s390x/cc_helper.c | 5 ++--
> target/s390x/diag.c | 2 +-
> target/s390x/excp_helper.c | 6 ++---
> target/s390x/fpu_helper.c | 4 +--
> target/s390x/helper.c | 7 +++---
> target/s390x/int_helper.c | 3 +--
> target/s390x/interrupt.c | 6 ++---
> target/s390x/mem_helper.c | 28 ++++++++-------------
> target/s390x/misc_helper.c | 50 ++++++++++++++++++-------------------
> target/s390x/mmu_helper.c | 8 +++---
> target/s390x/sigp.c | 4 +--
> 13 files changed, 56 insertions(+), 74 deletions(-)
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 9cdd831a77..eefed6f509 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -163,11 +163,6 @@ struct S390CPU {
> uint32_t irqstate_saved_size;
> };
>
> -static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
> -{
> - return container_of(env, S390CPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(S390CPU, env)
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c
> index b8bd1c956c..8211022ceb 100644
> --- a/linux-user/s390x/cpu_loop.c
> +++ b/linux-user/s390x/cpu_loop.c
> @@ -26,7 +26,7 @@
>
> void cpu_loop(CPUS390XState *env)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr, n, sig;
> target_siginfo_t info;
> target_ulong addr;
> diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
> index 0e467bf2b6..e9732500ad 100644
> --- a/target/s390x/cc_helper.c
> +++ b/target/s390x/cc_helper.c
> @@ -405,7 +405,6 @@ static uint32_t cc_calc_lcbb(uint64_t dst)
> static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
> uint64_t src, uint64_t dst, uint64_t vr)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> uint32_t r = 0;
>
> switch (cc_op) {
> @@ -526,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
> break;
>
> default:
> - cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op));
> + cpu_abort(env_cpu(env), "Unknown CC operation: %s\n", cc_name(cc_op));
> }
>
> HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
> @@ -550,7 +549,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src,
> void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr)
> {
> load_psw(env, mask, addr);
> - cpu_loop_exit(CPU(s390_env_get_cpu(env)));
> + cpu_loop_exit(env_cpu(env));
> }
>
> void HELPER(sacf)(CPUS390XState *env, uint64_t a1)
> diff --git a/target/s390x/diag.c b/target/s390x/diag.c
> index aafa740f61..65eabf0461 100644
> --- a/target/s390x/diag.c
> +++ b/target/s390x/diag.c
> @@ -55,7 +55,7 @@ int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3)
>
> void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint64_t addr = env->regs[r1];
> uint64_t subcode = env->regs[r3];
> IplParameterBlock *iplb;
> diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
> index f84bfb1284..b83c1e6559 100644
> --- a/target/s390x/excp_helper.c
> +++ b/target/s390x/excp_helper.c
> @@ -36,7 +36,7 @@
> void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code,
> int ilen, uintptr_t ra)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cpu_restore_state(cs, ra, true);
> qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
> @@ -51,7 +51,7 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
> g_assert(dxc <= 0xff);
> #if !defined(CONFIG_USER_ONLY)
> /* Store the DXC into the lowcore */
> - stl_phys(CPU(s390_env_get_cpu(env))->as,
> + stl_phys(env_cpu(env)->as,
> env->psa + offsetof(LowCore, data_exc_code), dxc);
> #endif
>
> @@ -261,7 +261,7 @@ static void do_svc_interrupt(CPUS390XState *env)
> static void do_ext_interrupt(CPUS390XState *env)
> {
> QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic());
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> uint64_t mask, addr;
> uint16_t cpu_addr;
> LowCore *lowcore;
> diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
> index 1be68bafea..906fa8ce99 100644
> --- a/target/s390x/fpu_helper.c
> +++ b/target/s390x/fpu_helper.c
> @@ -114,8 +114,6 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
>
> static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> -
> switch (float_compare) {
> case float_relation_equal:
> return 0;
> @@ -126,7 +124,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
> case float_relation_unordered:
> return 3;
> default:
> - cpu_abort(CPU(cpu), "unknown return value for float compare\n");
> + cpu_abort(env_cpu(env), "unknown return value for float compare\n");
> }
> }
>
> diff --git a/target/s390x/helper.c b/target/s390x/helper.c
> index f957a2c830..52399bf7f4 100644
> --- a/target/s390x/helper.c
> +++ b/target/s390x/helper.c
> @@ -111,11 +111,11 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
> env->cc_op = (mask >> 44) & 3;
>
> if ((old_mask ^ mask) & PSW_MASK_PER) {
> - s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env)));
> + s390_cpu_recompute_watchpoints(env_cpu(env));
> }
>
> if (mask & PSW_MASK_WAIT) {
> - s390_handle_wait(s390_env_get_cpu(env));
> + s390_handle_wait(env_archcpu(env));
> }
> }
>
> @@ -137,14 +137,13 @@ uint64_t get_psw_mask(CPUS390XState *env)
>
> LowCore *cpu_map_lowcore(CPUS390XState *env)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> LowCore *lowcore;
> hwaddr len = sizeof(LowCore);
>
> lowcore = cpu_physical_memory_map(env->psa, &len, 1);
>
> if (len < sizeof(LowCore)) {
> - cpu_abort(CPU(cpu), "Could not map lowcore\n");
> + cpu_abort(env_cpu(env), "Could not map lowcore\n");
> }
>
> return lowcore;
> diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c
> index abbbc20d9c..d13cc49be6 100644
> --- a/target/s390x/int_helper.c
> +++ b/target/s390x/int_helper.c
> @@ -109,10 +109,9 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al,
> s390_program_interrupt(env, PGM_FIXPT_DIVIDE, ILEN_AUTO, GETPC());
> }
> #else
> - S390CPU *cpu = s390_env_get_cpu(env);
> /* 32-bit hosts would need special wrapper functionality - just abort if
> we encounter such a case; it's very unlikely anyways. */
> - cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n");
> + cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n");
> #endif
> }
> return ret;
> diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c
> index a17eff5ebc..a8f9b38795 100644
> --- a/target/s390x/interrupt.c
> +++ b/target/s390x/interrupt.c
> @@ -23,7 +23,7 @@
> /* Ensure to exit the TB after this call! */
> void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = EXCP_PGM;
> env->int_pgm_code = code;
> @@ -33,10 +33,8 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen)
> void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
> uintptr_t ra)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> -
> if (kvm_enabled()) {
> - kvm_s390_program_interrupt(cpu, code);
> + kvm_s390_program_interrupt(env_archcpu(env), code);
> } else if (tcg_enabled()) {
> tcg_s390_program_interrupt(env, code, ilen, ra);
> } else {
> diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
> index e2992deb2f..f02eb85d30 100644
> --- a/target/s390x/mem_helper.c
> +++ b/target/s390x/mem_helper.c
> @@ -1633,7 +1633,6 @@ uint32_t HELPER(csst_parallel)(CPUS390XState *env, uint32_t r3, uint64_t a1,
> void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> {
> uintptr_t ra = GETPC();
> - S390CPU *cpu = s390_env_get_cpu(env);
> bool PERchanged = false;
> uint64_t src = a2;
> uint32_t i;
> @@ -1658,16 +1657,15 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> }
>
> if (PERchanged && env->psw.mask & PSW_MASK_PER) {
> - s390_cpu_recompute_watchpoints(CPU(cpu));
> + s390_cpu_recompute_watchpoints(env_cpu(env));
> }
>
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> {
> uintptr_t ra = GETPC();
> - S390CPU *cpu = s390_env_get_cpu(env);
> bool PERchanged = false;
> uint64_t src = a2;
> uint32_t i;
> @@ -1691,10 +1689,10 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> }
>
> if (PERchanged && env->psw.mask & PSW_MASK_PER) {
> - s390_cpu_recompute_watchpoints(CPU(cpu));
> + s390_cpu_recompute_watchpoints(env_cpu(env));
> }
>
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> @@ -1753,8 +1751,8 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr)
>
> uint32_t HELPER(tprot)(CPUS390XState *env, uint64_t a1, uint64_t a2)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + S390CPU *cpu = env_archcpu(env);
> + CPUState *cs = env_cpu(env);
>
> /*
> * TODO: we currently don't handle all access protection types
> @@ -1922,7 +1920,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
>
> void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> const uintptr_t ra = GETPC();
> uint64_t table, entry, raddr;
> uint16_t entries, i, index = 0;
> @@ -1974,7 +1972,7 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
> void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
> uint32_t m4)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> const uintptr_t ra = GETPC();
> uint64_t page = vaddr & TARGET_PAGE_MASK;
> uint64_t pte_addr, pte;
> @@ -2014,17 +2012,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
> /* flush local tlb */
> void HELPER(ptlb)(CPUS390XState *env)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> -
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
>
> /* flush global tlb */
> void HELPER(purge)(CPUS390XState *env)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> -
> - tlb_flush_all_cpus_synced(CPU(cpu));
> + tlb_flush_all_cpus_synced(env_cpu(env));
> }
>
> /* load using real address */
> @@ -2068,7 +2062,7 @@ void HELPER(sturg)(CPUS390XState *env, uint64_t addr, uint64_t v1)
> /* load real address */
> uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t cc = 0;
> uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> uint64_t ret;
> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
> index ee67c1fa0c..c806c3ec00 100644
> --- a/target/s390x/misc_helper.c
> +++ b/target/s390x/misc_helper.c
> @@ -55,7 +55,7 @@
> /* Raise an exception statically from a TB. */
> void HELPER(exception)(CPUS390XState *env, uint32_t excp)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> HELPER_LOG("%s: exception %d\n", __func__, excp);
> cs->exception_index = excp;
> @@ -150,7 +150,7 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num)
> /* Set Prefix */
> void HELPER(spx)(CPUS390XState *env, uint64_t a1)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t prefix = a1 & 0x7fffe000;
>
> env->psa = prefix;
> @@ -256,7 +256,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1)
> const uint32_t sel2 = r1 & STSI_R1_SEL2_MASK;
> const MachineState *ms = MACHINE(qdev_get_machine());
> uint16_t total_cpus = 0, conf_cpus = 0, reserved_cpus = 0;
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> SysIB sysib = { };
> int i, cc = 0;
>
> @@ -411,7 +411,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
> #ifndef CONFIG_USER_ONLY
> void HELPER(xsch)(CPUS390XState *env, uint64_t r1)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_xsch(cpu, r1, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -419,7 +419,7 @@ void HELPER(xsch)(CPUS390XState *env, uint64_t r1)
>
> void HELPER(csch)(CPUS390XState *env, uint64_t r1)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_csch(cpu, r1, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -427,7 +427,7 @@ void HELPER(csch)(CPUS390XState *env, uint64_t r1)
>
> void HELPER(hsch)(CPUS390XState *env, uint64_t r1)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_hsch(cpu, r1, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -435,7 +435,7 @@ void HELPER(hsch)(CPUS390XState *env, uint64_t r1)
>
> void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_msch(cpu, r1, inst >> 16, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -443,7 +443,7 @@ void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
>
> void HELPER(rchp)(CPUS390XState *env, uint64_t r1)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_rchp(cpu, r1, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -451,7 +451,7 @@ void HELPER(rchp)(CPUS390XState *env, uint64_t r1)
>
> void HELPER(rsch)(CPUS390XState *env, uint64_t r1)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_rsch(cpu, r1, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -459,7 +459,7 @@ void HELPER(rsch)(CPUS390XState *env, uint64_t r1)
>
> void HELPER(sal)(CPUS390XState *env, uint64_t r1)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> ioinst_handle_sal(cpu, r1, GETPC());
> @@ -468,7 +468,7 @@ void HELPER(sal)(CPUS390XState *env, uint64_t r1)
>
> void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> ioinst_handle_schm(cpu, r1, r2, inst >> 16, GETPC());
> @@ -477,7 +477,7 @@ void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst)
>
> void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_ssch(cpu, r1, inst >> 16, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -485,7 +485,7 @@ void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
>
> void HELPER(stcrw)(CPUS390XState *env, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> ioinst_handle_stcrw(cpu, inst >> 16, GETPC());
> @@ -494,7 +494,7 @@ void HELPER(stcrw)(CPUS390XState *env, uint64_t inst)
>
> void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_stsch(cpu, r1, inst >> 16, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -503,7 +503,7 @@ void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
> uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr)
> {
> const uintptr_t ra = GETPC();
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
> QEMUS390FlicIO *io = NULL;
> LowCore *lowcore;
> @@ -555,7 +555,7 @@ uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr)
>
> void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_tsch(cpu, r1, inst >> 16, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -563,7 +563,7 @@ void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
>
> void HELPER(chsc)(CPUS390XState *env, uint64_t inst)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> qemu_mutex_lock_iothread();
> ioinst_handle_chsc(cpu, inst >> 16, GETPC());
> qemu_mutex_unlock_iothread();
> @@ -618,7 +618,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr)
> /* If the instruction has to be nullified, trigger the
> exception immediately. */
> if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> env->per_perc_atmid |= PER_CODE_EVENT_NULLIFICATION;
> env->int_pgm_code = PGM_PER;
> @@ -695,7 +695,7 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr)
> */
> void HELPER(clp)(CPUS390XState *env, uint32_t r2)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> clp_service_call(cpu, r2, GETPC());
> @@ -704,7 +704,7 @@ void HELPER(clp)(CPUS390XState *env, uint32_t r2)
>
> void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> pcilg_service_call(cpu, r1, r2, GETPC());
> @@ -713,7 +713,7 @@ void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
>
> void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> pcistg_service_call(cpu, r1, r2, GETPC());
> @@ -723,7 +723,7 @@ void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2)
> void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba,
> uint32_t ar)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> stpcifc_service_call(cpu, r1, fiba, ar, GETPC());
> @@ -745,7 +745,7 @@ void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint64_t r3)
>
> void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> rpcit_service_call(cpu, r1, r2, GETPC());
> @@ -755,7 +755,7 @@ void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2)
> void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3,
> uint64_t gaddr, uint32_t ar)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> pcistb_service_call(cpu, r1, r3, gaddr, ar, GETPC());
> @@ -765,7 +765,7 @@ void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3,
> void HELPER(mpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba,
> uint32_t ar)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> qemu_mutex_lock_iothread();
> mpcifc_service_call(cpu, r1, fiba, ar, GETPC());
> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
> index 145b62a7ef..9669bae393 100644
> --- a/target/s390x/mmu_helper.c
> +++ b/target/s390x/mmu_helper.c
> @@ -58,12 +58,12 @@
> static void trigger_access_exception(CPUS390XState *env, uint32_t type,
> uint32_t ilen, uint64_t tec)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> if (kvm_enabled()) {
> kvm_s390_access_exception(cpu, type, tec);
> } else {
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> if (type != PGM_ADDRESSING) {
> stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
> }
> @@ -185,7 +185,7 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
> target_ulong *raddr, int *flags, int rw,
> bool exc)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint64_t origin, offs, pt_entry;
>
> if (st_entry & SEGMENT_ENTRY_RO) {
> @@ -214,7 +214,7 @@ static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
> target_ulong *raddr, int *flags, int rw,
> bool exc)
> {
> - CPUState *cs = CPU(s390_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint64_t origin, offs, new_entry;
> const int pchks[4] = {
> PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
> diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
> index c1f9245797..ea5f69d5d8 100644
> --- a/target/s390x/sigp.c
> +++ b/target/s390x/sigp.c
> @@ -454,7 +454,7 @@ int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3)
> {
> uint64_t *status_reg = &env->regs[r1];
> uint64_t param = (r1 % 2) ? env->regs[r1] : env->regs[r1 + 1];
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
> S390CPU *dst_cpu = NULL;
> int ret;
>
> @@ -492,7 +492,7 @@ int s390_cpu_restart(S390CPU *cpu)
>
> void do_stop_interrupt(CPUS390XState *env)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> + S390CPU *cpu = env_archcpu(env);
>
> if (s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu) == 0) {
> qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 25/39] target/sh4: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 25/39] target/sh4: " Richard Henderson
@ 2019-05-09 20:14 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:14 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:24 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/sh4/cpu.h | 5 -----
> linux-user/sh4/cpu_loop.c | 2 +-
> target/sh4/helper.c | 26 ++++++++++++--------------
> target/sh4/op_helper.c | 9 +++------
> 4 files changed, 16 insertions(+), 26 deletions(-)
>
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index c1a9e4f981..2ed942ca47 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -207,11 +207,6 @@ struct SuperHCPU {
> CPUSH4State env;
> };
>
> -static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
> -{
> - return container_of(env, SuperHCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(SuperHCPU, env)
>
> void superh_cpu_do_interrupt(CPUState *cpu);
> diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
> index 59cbbeda7e..add8817d86 100644
> --- a/linux-user/sh4/cpu_loop.c
> +++ b/linux-user/sh4/cpu_loop.c
> @@ -23,7 +23,7 @@
>
> void cpu_loop(CPUSH4State *env)
> {
> - CPUState *cs = CPU(sh_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr, ret;
> target_siginfo_t info;
>
> diff --git a/target/sh4/helper.c b/target/sh4/helper.c
> index 2ff0cf4060..5240da715e 100644
> --- a/target/sh4/helper.c
> +++ b/target/sh4/helper.c
> @@ -238,8 +238,6 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
>
> static int itlb_replacement(CPUSH4State * env)
> {
> - SuperHCPU *cpu = sh_env_get_cpu(env);
> -
> if ((env->mmucr & 0xe0000000) == 0xe0000000) {
> return 0;
> }
> @@ -252,7 +250,7 @@ static int itlb_replacement(CPUSH4State * env)
> if ((env->mmucr & 0x2c000000) == 0x00000000) {
> return 3;
> }
> - cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
> + cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
> }
>
> /* Find the corresponding entry in the right TLB
> @@ -308,7 +306,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
> itlb = itlb_replacement(env);
> ientry = &env->itlb[itlb];
> if (ientry->v) {
> - tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
> + tlb_flush_page(env_cpu(env), ientry->vpn << 10);
> }
> *ientry = env->utlb[utlb];
> update_itlb_use(env, itlb);
> @@ -533,14 +531,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>
> void cpu_load_tlb(CPUSH4State * env)
> {
> - SuperHCPU *cpu = sh_env_get_cpu(env);
> + CPUState *cs = env_cpu(env);
> int n = cpu_mmucr_urc(env->mmucr);
> tlb_t * entry = &env->utlb[n];
>
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(CPU(cpu), address);
> + tlb_flush_page(cs, address);
> }
>
> /* Take values into cpu status from registers. */
> @@ -563,7 +561,7 @@ void cpu_load_tlb(CPUSH4State * env)
> entry->size = 1024 * 1024; /* 1M */
> break;
> default:
> - cpu_abort(CPU(cpu), "Unhandled load_tlb");
> + cpu_abort(cs, "Unhandled load_tlb");
> break;
> }
> entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
> @@ -590,7 +588,7 @@ void cpu_load_tlb(CPUSH4State * env)
> entry->v = 0;
> }
>
> - tlb_flush(CPU(sh_env_get_cpu(s)));
> + tlb_flush(env_cpu(s));
> }
>
> uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
> @@ -616,7 +614,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in itlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> + tlb_flush_page(env_cpu(s), address);
> }
> entry->asid = asid;
> entry->vpn = vpn;
> @@ -658,7 +656,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> + tlb_flush_page(env_cpu(s), address);
> }
> entry->ppn = (mem_value & 0x1ffffc00) >> 10;
> entry->v = (mem_value & 0x00000100) >> 8;
> @@ -711,7 +709,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
> if (entry->vpn == vpn
> && (!use_asid || entry->asid == asid || entry->sh)) {
> if (utlb_match_entry) {
> - CPUState *cs = CPU(sh_env_get_cpu(s));
> + CPUState *cs = env_cpu(s);
>
> /* Multiple TLB Exception */
> cs->exception_index = 0x140;
> @@ -743,14 +741,14 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
> }
>
> if (needs_tlb_flush) {
> - tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
> + tlb_flush_page(env_cpu(s), vpn << 10);
> }
>
> } else {
> int index = (addr & 0x00003f00) >> 8;
> tlb_t * entry = &s->utlb[index];
> if (entry->v) {
> - CPUState *cs = CPU(sh_env_get_cpu(s));
> + CPUState *cs = env_cpu(s);
>
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> @@ -805,7 +803,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> + tlb_flush_page(env_cpu(s), address);
> }
> entry->ppn = (mem_value & 0x1ffffc00) >> 10;
> entry->v = (mem_value & 0x00000100) >> 8;
> diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
> index 12fba6fc78..11cb68cc1c 100644
> --- a/target/sh4/op_helper.c
> +++ b/target/sh4/op_helper.c
> @@ -58,10 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
> void helper_ldtlb(CPUSH4State *env)
> {
> #ifdef CONFIG_USER_ONLY
> - SuperHCPU *cpu = sh_env_get_cpu(env);
> -
> - /* XXXXX */
> - cpu_abort(CPU(cpu), "Unhandled ldtlb");
> + cpu_abort(env_cpu(env), "Unhandled ldtlb");
> #else
> cpu_load_tlb(env);
> #endif
> @@ -70,7 +67,7 @@ void helper_ldtlb(CPUSH4State *env)
> static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
> uintptr_t retaddr)
> {
> - CPUState *cs = CPU(sh_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = index;
> cpu_loop_exit_restore(cs, retaddr);
> @@ -103,7 +100,7 @@ void helper_debug(CPUSH4State *env)
>
> void helper_sleep(CPUSH4State *env)
> {
> - CPUState *cs = CPU(sh_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->halted = 1;
> env->in_sleep = 1;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 26/39] target/sparc: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 26/39] target/sparc: " Richard Henderson
@ 2019-05-09 20:15 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:15 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:25 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/sparc/cpu.h | 5 -----
> bsd-user/main.c | 2 +-
> hw/sparc/leon3.c | 4 ++--
> hw/sparc/sun4m.c | 4 ++--
> hw/sparc64/sparc64.c | 2 +-
> linux-user/sparc/cpu_loop.c | 2 +-
> target/sparc/fop_helper.c | 2 +-
> target/sparc/helper.c | 8 ++++----
> target/sparc/ldst_helper.c | 33 +++++++++++++++------------------
> target/sparc/mmu_helper.c | 10 +++++-----
> 10 files changed, 32 insertions(+), 40 deletions(-)
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index 5a10680d8f..1442232cef 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -532,11 +532,6 @@ struct SPARCCPU {
> CPUSPARCState env;
> };
>
> -static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
> -{
> - return container_of(env, SPARCCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(SPARCCPU, env)
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/bsd-user/main.c b/bsd-user/main.c
> index bfdcae4269..f6f76f1a64 100644
> --- a/bsd-user/main.c
> +++ b/bsd-user/main.c
> @@ -486,7 +486,7 @@ static void flush_windows(CPUSPARCState *env)
>
> void cpu_loop(CPUSPARCState *env)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr, ret, syscall_nr;
> //target_siginfo_t info;
>
> diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
> index 774639af33..ef74bc81c2 100644
> --- a/hw/sparc/leon3.c
> +++ b/hw/sparc/leon3.c
> @@ -91,7 +91,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
>
> env->interrupt_index = TT_EXTINT | i;
> if (old_interrupt != env->interrupt_index) {
> - cs = CPU(sparc_env_get_cpu(env));
> + cs = env_cpu(env);
> trace_leon3_set_irq(i);
> cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> }
> @@ -99,7 +99,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
> }
> }
> } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
> - cs = CPU(sparc_env_get_cpu(env));
> + cs = env_cpu(env);
> trace_leon3_reset_irq(env->interrupt_index & 15);
> env->interrupt_index = 0;
> cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
> index ca1e3825d5..a87bef6d4f 100644
> --- a/hw/sparc/sun4m.c
> +++ b/hw/sparc/sun4m.c
> @@ -147,7 +147,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>
> env->interrupt_index = TT_EXTINT | i;
> if (old_interrupt != env->interrupt_index) {
> - cs = CPU(sparc_env_get_cpu(env));
> + cs = env_cpu(env);
> trace_sun4m_cpu_interrupt(i);
> cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> }
> @@ -155,7 +155,7 @@ void cpu_check_irqs(CPUSPARCState *env)
> }
> }
> } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
> - cs = CPU(sparc_env_get_cpu(env));
> + cs = env_cpu(env);
> trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
> env->interrupt_index = 0;
> cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index 408388945e..689801f37d 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -46,7 +46,7 @@ void cpu_check_irqs(CPUSPARCState *env)
> if (env->ivec_status & 0x20) {
> return;
> }
> - cs = CPU(sparc_env_get_cpu(env));
> + cs = env_cpu(env);
> /* check if TM or SM in SOFTINT are set
> setting these also causes interrupt 14 */
> if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
> diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
> index 9e357229c0..d85359037c 100644
> --- a/linux-user/sparc/cpu_loop.c
> +++ b/linux-user/sparc/cpu_loop.c
> @@ -145,7 +145,7 @@ static void flush_windows(CPUSPARCState *env)
>
> void cpu_loop (CPUSPARCState *env)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
> abi_long ret;
> target_siginfo_t info;
> diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
> index b6642fd1d7..9eb9b75718 100644
> --- a/target/sparc/fop_helper.c
> +++ b/target/sparc/fop_helper.c
> @@ -53,7 +53,7 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
> }
>
> if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> /* Unmasked exception, generate a trap. Note that while
> the helper is marked as NO_WG, we can get away with
> diff --git a/target/sparc/helper.c b/target/sparc/helper.c
> index 46232788c8..1a52061fbf 100644
> --- a/target/sparc/helper.c
> +++ b/target/sparc/helper.c
> @@ -26,7 +26,7 @@
>
> void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = tt;
> cpu_loop_exit_restore(cs, ra);
> @@ -34,7 +34,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra)
>
> void helper_raise_exception(CPUSPARCState *env, int tt)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = tt;
> cpu_loop_exit(cs);
> @@ -42,7 +42,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt)
>
> void helper_debug(CPUSPARCState *env)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = EXCP_DEBUG;
> cpu_loop_exit(cs);
> @@ -243,7 +243,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
> #ifndef TARGET_SPARC64
> void helper_power_down(CPUSPARCState *env)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
> index a7fcb84ac0..a2d033a61f 100644
> --- a/target/sparc/ldst_helper.c
> +++ b/target/sparc/ldst_helper.c
> @@ -122,13 +122,13 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
>
> static void replace_tlb_entry(SparcTLBEntry *tlb,
> uint64_t tlb_tag, uint64_t tlb_tte,
> - CPUSPARCState *env1)
> + CPUSPARCState *env)
> {
> target_ulong mask, size, va, offset;
>
> /* flush page range if translation is valid */
> if (TTE_IS_VALID(tlb->tte)) {
> - CPUState *cs = CPU(sparc_env_get_cpu(env1));
> + CPUState *cs = env_cpu(env);
>
> size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte);
> mask = 1ULL + ~size;
> @@ -499,7 +499,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
> {
> int size = 1 << (memop & MO_SIZE);
> int sign = memop & MO_SIGN;
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint64_t ret = 0;
> #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
> uint32_t last_addr = addr;
> @@ -725,8 +725,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
> int asi, uint32_t memop)
> {
> int size = 1 << (memop & MO_SIZE);
> - SPARCCPU *cpu = sparc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> do_check_align(env, addr, size - 1, GETPC());
> switch (asi) {
> @@ -874,13 +873,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
> DPRINTF_MMU("mmu flush level %d\n", mmulev);
> switch (mmulev) {
> case 0: /* flush page */
> - tlb_flush_page(CPU(cpu), addr & 0xfffff000);
> + tlb_flush_page(cs, addr & 0xfffff000);
> break;
> case 1: /* flush segment (256k) */
> case 2: /* flush region (16M) */
> case 3: /* flush context (4G) */
> case 4: /* flush entire */
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> break;
> default:
> break;
> @@ -905,7 +904,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
> are invalid in normal mode. */
> if ((oldreg ^ env->mmuregs[reg])
> & (MMU_NF | env->def.mmu_bm)) {
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> }
> break;
> case 1: /* Context Table Pointer Register */
> @@ -916,7 +915,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
> if (oldreg != env->mmuregs[reg]) {
> /* we flush when the MMU context changes because
> QEMU has no MMU context support */
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> }
> break;
> case 3: /* Synchronous Fault Status Register with Clear */
> @@ -1027,8 +1026,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
> case ASI_USERTXT: /* User code access, XXX */
> case ASI_KERNELTXT: /* Supervisor code access, XXX */
> default:
> - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
> - addr, true, false, asi, size);
> + cpu_unassigned_access(cs, addr, true, false, asi, size);
> break;
>
> case ASI_USERDATA: /* User data access */
> @@ -1175,7 +1173,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
> {
> int size = 1 << (memop & MO_SIZE);
> int sign = memop & MO_SIGN;
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint64_t ret = 0;
> #if defined(DEBUG_ASI)
> target_ulong last_addr = addr;
> @@ -1481,8 +1479,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> int asi, uint32_t memop)
> {
> int size = 1 << (memop & MO_SIZE);
> - SPARCCPU *cpu = sparc_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
>
> #ifdef DEBUG_ASI
> dump_asi("write", addr, asi, size, val);
> @@ -1686,13 +1683,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> env->dmmu.mmu_primary_context = val;
> /* can be optimized to only flush MMU_USER_IDX
> and MMU_KERNEL_IDX entries */
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> break;
> case 2: /* Secondary context */
> env->dmmu.mmu_secondary_context = val;
> /* can be optimized to only flush MMU_USER_SECONDARY_IDX
> and MMU_KERNEL_SECONDARY_IDX entries */
> - tlb_flush(CPU(cpu));
> + tlb_flush(cs);
> break;
> case 5: /* TSB access */
> DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
> @@ -1768,13 +1765,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> case 1:
> env->dmmu.mmu_primary_context = val;
> env->immu.mmu_primary_context = val;
> - tlb_flush_by_mmuidx(CPU(cpu),
> + tlb_flush_by_mmuidx(cs,
> (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
> break;
> case 2:
> env->dmmu.mmu_secondary_context = val;
> env->immu.mmu_secondary_context = val;
> - tlb_flush_by_mmuidx(CPU(cpu),
> + tlb_flush_by_mmuidx(cs,
> (1 << MMU_USER_SECONDARY_IDX) |
> (1 << MMU_KERNEL_SECONDARY_IDX));
> break;
> diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
> index afcc5b617d..2cfcb6a976 100644
> --- a/target/sparc/mmu_helper.c
> +++ b/target/sparc/mmu_helper.c
> @@ -96,7 +96,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
> uint32_t pde;
> int error_code = 0, is_dirty, is_user;
> unsigned long page_offset;
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> is_user = mmu_idx == MMU_USER_IDX;
>
> @@ -256,7 +256,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
>
> target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> hwaddr pde_ptr;
> uint32_t pde;
>
> @@ -323,7 +323,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
>
> void dump_mmu(CPUSPARCState *env)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_ulong va, va1, va2;
> unsigned int n, m, o;
> hwaddr pde_ptr, pa;
> @@ -482,7 +482,7 @@ static int get_physical_address_data(CPUSPARCState *env,
> hwaddr *physical, int *prot,
> target_ulong address, int rw, int mmu_idx)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> unsigned int i;
> uint64_t context;
> uint64_t sfsr = 0;
> @@ -600,7 +600,7 @@ static int get_physical_address_code(CPUSPARCState *env,
> hwaddr *physical, int *prot,
> target_ulong address, int mmu_idx)
> {
> - CPUState *cs = CPU(sparc_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> unsigned int i;
> uint64_t context;
> bool is_user = false;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 27/39] target/tilegx: Use env_cpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 27/39] target/tilegx: Use env_cpu Richard Henderson
@ 2019-05-09 20:16 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:28 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/tilegx/cpu.h | 5 -----
> linux-user/tilegx/cpu_loop.c | 2 +-
> target/tilegx/helper.c | 2 +-
> 3 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
> index 135df63523..7f8fe7c513 100644
> --- a/target/tilegx/cpu.h
> +++ b/target/tilegx/cpu.h
> @@ -138,11 +138,6 @@ typedef struct TileGXCPU {
> CPUTLGState env;
> } TileGXCPU;
>
> -static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
> -{
> - return container_of(env, TileGXCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(TileGXCPU, env)
>
> /* TILE-Gx memory attributes */
> diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c
> index 4f39eb9ad3..d4abe29dcd 100644
> --- a/linux-user/tilegx/cpu_loop.c
> +++ b/linux-user/tilegx/cpu_loop.c
> @@ -206,7 +206,7 @@ static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
>
> void cpu_loop(CPUTLGState *env)
> {
> - CPUState *cs = CPU(tilegx_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int trapnr;
>
> while (1) {
> diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c
> index 4964bb9111..a57a679825 100644
> --- a/target/tilegx/helper.c
> +++ b/target/tilegx/helper.c
> @@ -28,7 +28,7 @@
>
> void helper_exception(CPUTLGState *env, uint32_t excp)
> {
> - CPUState *cs = CPU(tilegx_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> cpu_loop_exit(cs);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 28/39] target/tricore: Use env_cpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 28/39] target/tricore: " Richard Henderson
@ 2019-05-09 20:16 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:31 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/tricore/cpu.h | 5 -----
> target/tricore/op_helper.c | 4 ++--
> 2 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index 4c997b6d30..fc3328fdf5 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -208,11 +208,6 @@ struct TriCoreCPU {
> CPUTriCoreState env;
> };
>
> -static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env)
> -{
> - return TRICORE_CPU(container_of(env, TriCoreCPU, env));
> -}
> -
> #define ENV_OFFSET offsetof(TriCoreCPU, env)
>
> hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
> index ed9dc0c83e..ba2f21a6c3 100644
> --- a/target/tricore/op_helper.c
> +++ b/target/tricore/op_helper.c
> @@ -29,7 +29,7 @@ static void QEMU_NORETURN
> raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin,
> uintptr_t pc, uint32_t fcd_pc)
> {
> - CPUState *cs = CPU(tricore_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> /* in case we come from a helper-call we need to restore the PC */
> cpu_restore_state(cs, pc, true);
>
> @@ -2800,7 +2800,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
> int error_code,
> uintptr_t pc)
> {
> - CPUState *cs = CPU(tricore_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> cs->exception_index = exception;
> env->error_code = error_code;
> /* now we have a real cpu fault */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu Richard Henderson
@ 2019-05-09 20:17 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:17 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:30 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/unicore32/cpu.h | 5 -----
> hw/unicore32/puv3.c | 2 +-
> target/unicore32/helper.c | 8 ++------
> target/unicore32/op_helper.c | 2 +-
> target/unicore32/softmmu.c | 11 ++++-------
> target/unicore32/translate.c | 26 ++------------------------
> target/unicore32/ucf64_helper.c | 2 +-
> 7 files changed, 11 insertions(+), 45 deletions(-)
>
> diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
> index 22e22345dc..2dd1b34765 100644
> --- a/target/unicore32/cpu.h
> +++ b/target/unicore32/cpu.h
> @@ -76,11 +76,6 @@ struct UniCore32CPU {
> CPUUniCore32State env;
> };
>
> -static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
> -{
> - return container_of(env, UniCore32CPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(UniCore32CPU, env)
>
> void uc32_cpu_do_interrupt(CPUState *cpu);
> diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
> index b42e600f74..132e6086ee 100644
> --- a/hw/unicore32/puv3.c
> +++ b/hw/unicore32/puv3.c
> @@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
>
> /* Initialize interrupt controller */
> cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler,
> - uc32_env_get_cpu(env), 0);
> + env_archcpu(env), 0);
> dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc);
> for (i = 0; i < PUV3_IRQS_NR; i++) {
> irqs[i] = qdev_get_gpio_in(dev, i);
> diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c
> index a5ff2ddb74..19ba865482 100644
> --- a/target/unicore32/helper.c
> +++ b/target/unicore32/helper.c
> @@ -31,8 +31,6 @@
> void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
> uint32_t cop)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> /*
> * movc pp.nn, rn, #imm9
> * rn: UCOP_REG_D
> @@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
> case 6:
> if ((cop <= 6) && (cop >= 2)) {
> /* invalid all tlb */
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> return;
> }
> break;
> @@ -218,10 +216,8 @@ void helper_cp1_putc(target_ulong x)
> #ifdef CONFIG_USER_ONLY
> void switch_mode(CPUUniCore32State *env, int mode)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> if (mode != ASR_MODE_USER) {
> - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> + cpu_abort(env_cpu(env), "Tried to switch out of user mode\n");
> }
> }
>
> diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c
> index e0a15882d3..44ff84420e 100644
> --- a/target/unicore32/op_helper.c
> +++ b/target/unicore32/op_helper.c
> @@ -19,7 +19,7 @@
>
> void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
> {
> - CPUState *cs = CPU(uc32_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> cpu_loop_exit(cs);
> diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c
> index 00c7e0d028..2f31592faf 100644
> --- a/target/unicore32/softmmu.c
> +++ b/target/unicore32/softmmu.c
> @@ -36,8 +36,6 @@
> /* Map CPU modes onto saved register banks. */
> static inline int bank_number(CPUUniCore32State *env, int mode)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> switch (mode) {
> case ASR_MODE_USER:
> case ASR_MODE_SUSR:
> @@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode)
> case ASR_MODE_INTR:
> return 4;
> }
> - cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
> + cpu_abort(env_cpu(env), "Bad mode %x\n", mode);
> return -1;
> }
>
> @@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
> int access_type, int is_user, uint32_t *phys_ptr, int *prot,
> target_ulong *page_size)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> int code;
> uint32_t table;
> uint32_t desc;
> @@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
> *page_size = TARGET_PAGE_SIZE;
> break;
> default:
> - cpu_abort(CPU(cpu), "wrong page type!");
> + cpu_abort(cs, "wrong page type!");
> }
> break;
> default:
> - cpu_abort(CPU(cpu), "wrong page type!");
> + cpu_abort(cs, "wrong page type!");
> }
>
> *phys_ptr = phys_addr;
> diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
> index 89b02d1c3c..d27451eed3 100644
> --- a/target/unicore32/translate.c
> +++ b/target/unicore32/translate.c
> @@ -180,7 +180,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> #define UCOP_SET_L UCOP_SET(24)
> #define UCOP_SET_S UCOP_SET(24)
>
> -#define ILLEGAL cpu_abort(CPU(cpu), \
> +#define ILLEGAL cpu_abort(env_cpu(env), \
> "Illegal UniCore32 instruction %x at line %d!", \
> insn, __LINE__)
>
> @@ -188,7 +188,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp, tmp2, tmp3;
> if ((insn & 0xfe000000) == 0xe0000000) {
> tmp2 = new_tmp();
> @@ -214,7 +213,6 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
> static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
>
> if ((insn & 0xff003fff) == 0xe1000400) {
> @@ -682,7 +680,6 @@ static inline long ucf64_reg_offset(int reg)
> /* UniCore-F64 single load/store I_offset */
> static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int offset;
> TCGv tmp;
> TCGv addr;
> @@ -729,7 +726,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in
> /* UniCore-F64 load/store multiple words */
> static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int i;
> int j, n, freg;
> TCGv tmp;
> @@ -815,7 +811,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in
> /* UniCore-F64 mrc/mcr */
> static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
>
> if ((insn & 0xfe0003ff) == 0xe2000000) {
> @@ -880,8 +875,6 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins
> /* UniCore-F64 convert instructions */
> static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> if (UCOP_UCF64_FMT == 3) {
> ILLEGAL;
> }
> @@ -948,8 +941,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn
> /* UniCore-F64 compare instructions */
> static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> if (UCOP_SET(25)) {
> ILLEGAL;
> }
> @@ -1028,8 +1019,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn
> /* UniCore-F64 data processing */
> static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> if (UCOP_UCF64_FMT == 3) {
> ILLEGAL;
> }
> @@ -1063,8 +1052,6 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins
> /* Disassemble an F64 instruction */
> static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> if (!UCOP_SET(29)) {
> if (UCOP_SET(26)) {
> do_ucf64_ldst_m(env, s, insn);
> @@ -1162,8 +1149,6 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
> static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
> switch (UCOP_CPNUM) {
> #ifndef CONFIG_USER_ONLY
> case 0:
> @@ -1178,14 +1163,13 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
> break;
> default:
> /* Unknown coprocessor. */
> - cpu_abort(CPU(cpu), "Unknown coprocessor!");
> + cpu_abort(env_cpu(env), "Unknown coprocessor!");
> }
> }
>
> /* data processing instructions */
> static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
> TCGv tmp2;
> int logic_cc;
> @@ -1419,7 +1403,6 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* miscellaneous instructions */
> static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val;
> TCGv tmp;
>
> @@ -1545,7 +1528,6 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* SWP instruction */
> static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv addr;
> TCGv tmp;
> TCGv tmp2;
> @@ -1573,7 +1555,6 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* load/store hw/sb */
> static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv addr;
> TCGv tmp;
>
> @@ -1626,7 +1607,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* load/store multiple words */
> static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val, i, mmu_idx;
> int j, n, reg, user, loaded_base;
> TCGv tmp;
> @@ -1768,7 +1748,6 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* branch (and link) */
> static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val;
> int32_t offset;
> TCGv tmp;
> @@ -1798,7 +1777,6 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>
> static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int insn;
>
> insn = cpu_ldl_code(env, s->pc);
> diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helper.c
> index fad3fa6618..e078e84437 100644
> --- a/target/unicore32/ucf64_helper.c
> +++ b/target/unicore32/ucf64_helper.c
> @@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
>
> void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> + UniCore32CPU *cpu = env_archcpu(env);
> int i;
> uint32_t changed;
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 30/39] target/xtensa: Use env_cpu, env_archcpu
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 30/39] target/xtensa: " Richard Henderson
@ 2019-05-09 20:19 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:19 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:37 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
> so that the definition of env_cpu is available.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/xtensa/cpu.h | 17 ++++++-----------
> hw/xtensa/pic_cpu.c | 2 +-
> linux-user/xtensa/cpu_loop.c | 2 +-
> target/xtensa/dbg_helper.c | 4 ++--
> target/xtensa/exc_helper.c | 9 ++++-----
> target/xtensa/helper.c | 2 +-
> target/xtensa/mmu_helper.c | 11 ++++-------
> target/xtensa/xtensa-semi.c | 2 +-
> 8 files changed, 20 insertions(+), 29 deletions(-)
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index a20541b5d6..86c88eae40 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -529,11 +529,6 @@ struct XtensaCPU {
> CPUXtensaState env;
> };
>
> -static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
> -{
> - return container_of(env, XtensaCPU, env);
> -}
> -
> #define ENV_OFFSET offsetof(XtensaCPU, env)
>
>
> @@ -711,10 +706,15 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
> #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
> #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
>
> +typedef CPUXtensaState CPUArchState;
> +typedef XtensaCPU ArchCPU;
> +
> +#include "exec/cpu-all.h"
> +
> static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t *flags)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> *pc = env->pc;
> *cs_base = 0;
> @@ -784,9 +784,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
> }
> }
>
> -typedef CPUXtensaState CPUArchState;
> -typedef XtensaCPU ArchCPU;
> -
> -#include "exec/cpu-all.h"
> -
> #endif
> diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c
> index a8939f5e58..df3acbb541 100644
> --- a/hw/xtensa/pic_cpu.c
> +++ b/hw/xtensa/pic_cpu.c
> @@ -33,7 +33,7 @@
>
> void check_interrupts(CPUXtensaState *env)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int minlevel = xtensa_get_cintlevel(env);
> uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
> int level;
> diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c
> index bee78edb8a..64831c9199 100644
> --- a/linux-user/xtensa/cpu_loop.c
> +++ b/linux-user/xtensa/cpu_loop.c
> @@ -123,7 +123,7 @@ static void xtensa_underflow12(CPUXtensaState *env)
>
> void cpu_loop(CPUXtensaState *env)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> target_siginfo_t info;
> abi_ulong ret;
> int trapnr;
> diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
> index cd8fbd653a..be1f81107b 100644
> --- a/target/xtensa/dbg_helper.c
> +++ b/target/xtensa/dbg_helper.c
> @@ -71,7 +71,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
> static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
> uint32_t dbreakc)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
> uint32_t mask = dbreakc | ~DBREAKC_MASK;
>
> @@ -118,7 +118,7 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
> set_dbreak(env, i, env->sregs[DBREAKA + i], v);
> } else {
> if (env->cpu_watchpoint[i]) {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
> env->cpu_watchpoint[i] = NULL;
> diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
> index 4a1f7aef5d..601341d13a 100644
> --- a/target/xtensa/exc_helper.c
> +++ b/target/xtensa/exc_helper.c
> @@ -34,7 +34,7 @@
>
> void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> cs->exception_index = excp;
> if (excp == EXCP_YIELD) {
> @@ -100,7 +100,7 @@ void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
>
> void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
> {
> - CPUState *cpu;
> + CPUState *cpu = env_cpu(env);
>
> env->pc = pc;
> env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
> @@ -111,11 +111,10 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
> qemu_mutex_unlock_iothread();
>
> if (env->pending_irq_level) {
> - cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
> + cpu_loop_exit(cpu);
> return;
> }
>
> - cpu = CPU(xtensa_env_get_cpu(env));
> cpu->halted = 1;
> HELPER(exception)(env, EXCP_HLT);
> }
> @@ -165,7 +164,7 @@ static void handle_interrupt(CPUXtensaState *env)
> (env->config->level_mask[level] &
> env->sregs[INTSET] &
> env->sregs[INTENABLE])) {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
>
> if (level > 1) {
> env->sregs[EPC1 + level - 1] = env->pc;
> diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
> index 5f37f378a3..7e5c10e098 100644
> --- a/target/xtensa/helper.c
> +++ b/target/xtensa/helper.c
> @@ -316,7 +316,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
>
> void xtensa_runstall(CPUXtensaState *env, bool runstall)
> {
> - CPUState *cpu = CPU(xtensa_env_get_cpu(env));
> + CPUState *cpu = env_cpu(env);
>
> env->runstall = runstall;
> cpu->halted = runstall;
> diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
> index 79a10da231..2603f43807 100644
> --- a/target/xtensa/mmu_helper.c
> +++ b/target/xtensa/mmu_helper.c
> @@ -46,12 +46,10 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
>
> void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
> {
> - XtensaCPU *cpu = xtensa_env_get_cpu(env);
> -
> v = (v & 0xffffff00) | 0x1;
> if (v != env->sregs[RASID]) {
> env->sregs[RASID] = v;
> - tlb_flush(CPU(cpu));
> + tlb_flush(env_cpu(env));
> }
> }
>
> @@ -250,7 +248,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
> uint32_t wi;
> xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
> if (entry->variable && entry->asid) {
> - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
> + tlb_flush_page(env_cpu(env), entry->vaddr);
> entry->asid = 0;
> }
> }
> @@ -296,8 +294,7 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
> void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
> unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
> {
> - XtensaCPU *cpu = xtensa_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
>
> if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
> @@ -652,7 +649,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
>
> static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t paddr;
> uint32_t page_size;
> unsigned access;
> diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
> index 5f5ce4f344..bb29adc921 100644
> --- a/target/xtensa/xtensa-semi.c
> +++ b/target/xtensa/xtensa-semi.c
> @@ -197,7 +197,7 @@ void xtensa_sim_open_console(Chardev *chr)
>
> void HELPER(simcall)(CPUXtensaState *env)
> {
> - CPUState *cs = CPU(xtensa_env_get_cpu(env));
> + CPUState *cs = env_cpu(env);
> uint32_t *regs = env->regs;
>
> switch (regs[2]) {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 34/39] cpu: Move icount_decr to CPUNegativeOffsetState
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 34/39] cpu: Move icount_decr to CPUNegativeOffsetState Richard Henderson
@ 2019-05-09 20:26 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:35 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Amusingly, we had already ignored the comment to keep this value at the
> end of CPUState. This restores the minimum negative offset from TCG_AREG0
> for code generation.
>
> For the couple of uses within qom/cpu.c, add a pointer from the CPUState
> object to the IcountDecr object within CPUNegativeOffsetState.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-all.h | 1 +
> include/exec/cpu-defs.h | 3 ++-
> include/exec/gen-icount.h | 16 ++++++++++------
> include/qom/cpu.h | 40 ++++++++++++++++++---------------------
> accel/tcg/cpu-exec.c | 23 +++++++++++-----------
> accel/tcg/tcg-all.c | 6 ++----
> accel/tcg/translate-all.c | 8 ++++----
> cpus.c | 9 +++++----
> qom/cpu.c | 4 ++--
> 9 files changed, 56 insertions(+), 54 deletions(-)
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 5ae83405c8..253dd1d9a5 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -380,6 +380,7 @@ int cpu_exec(CPUState *cpu);
> static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
> {
> cpu->parent_obj.env_ptr = &cpu->env;
> + cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
> }
>
> /**
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index ad97991faf..3971910653 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -33,6 +33,7 @@
> #include "exec/hwaddr.h"
> #endif
> #include "exec/memattrs.h"
> +#include "qom/cpu.h"
>
> #include "cpu-param.h"
>
> @@ -232,7 +233,7 @@ typedef struct CPUTLB {
> * before CPUArchState, as a field named "neg".
> */
> typedef struct CPUNegativeOffsetState {
> - /* Empty */
> + IcountDecr icount_decr;
> } CPUNegativeOffsetState;
>
> #endif
> diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
> index 9cfa6ccce5..f7669b6841 100644
> --- a/include/exec/gen-icount.h
> +++ b/include/exec/gen-icount.h
> @@ -5,8 +5,6 @@
>
> /* Helpers for instruction counting code generation. */
>
> -#define ENV_OFFSET offsetof(ArchCPU, env)
> -
> static TCGOp *icount_start_insn;
>
> static inline void gen_tb_start(TranslationBlock *tb)
> @@ -21,7 +19,8 @@ static inline void gen_tb_start(TranslationBlock *tb)
> }
>
> tcg_gen_ld_i32(count, cpu_env,
> - -ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
> + offsetof(ArchCPU, neg.icount_decr.u32) -
> + offsetof(ArchCPU, env));
>
> if (tb_cflags(tb) & CF_USE_ICOUNT) {
> imm = tcg_temp_new_i32();
> @@ -39,7 +38,8 @@ static inline void gen_tb_start(TranslationBlock *tb)
>
> if (tb_cflags(tb) & CF_USE_ICOUNT) {
> tcg_gen_st16_i32(count, cpu_env,
> - -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
> + offsetof(ArchCPU, neg.icount_decr.u16.low) -
> + offsetof(ArchCPU, env));
> }
>
> tcg_temp_free_i32(count);
> @@ -60,14 +60,18 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
> static inline void gen_io_start(void)
> {
> TCGv_i32 tmp = tcg_const_i32(1);
> - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
> + tcg_gen_st_i32(tmp, cpu_env,
> + offsetof(ArchCPU, parent_obj.can_do_io) -
> + offsetof(ArchCPU, env));
> tcg_temp_free_i32(tmp);
> }
>
> static inline void gen_io_end(void)
> {
> TCGv_i32 tmp = tcg_const_i32(0);
> - tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
> + tcg_gen_st_i32(tmp, cpu_env,
> + offsetof(ArchCPU, parent_obj.can_do_io) -
> + offsetof(ArchCPU, env));
> tcg_temp_free_i32(tmp);
> }
>
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 08abcbd3fe..0d8fc1caa6 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -226,17 +226,25 @@ typedef struct CPUClass {
> bool gdb_stop_before_watchpoint;
> } CPUClass;
>
> +/*
> + * Low 16 bits: number of cycles left, used only in icount mode.
> + * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
> + * for this CPU and return to its top level loop (even in non-icount mode).
> + * This allows a single read-compare-cbranch-write sequence to test
> + * for both decrementer underflow and exceptions.
> + */
> +typedef union IcountDecr {
> + uint32_t u32;
> + struct {
> #ifdef HOST_WORDS_BIGENDIAN
> -typedef struct icount_decr_u16 {
> - uint16_t high;
> - uint16_t low;
> -} icount_decr_u16;
> + uint16_t high;
> + uint16_t low;
> #else
> -typedef struct icount_decr_u16 {
> - uint16_t low;
> - uint16_t high;
> -} icount_decr_u16;
> + uint16_t low;
> + uint16_t high;
> #endif
> + } u16;
> +} IcountDecr;
>
> typedef struct CPUBreakpoint {
> vaddr pc;
> @@ -308,11 +316,6 @@ struct qemu_work_item;
> * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
> * @singlestep_enabled: Flags for single-stepping.
> * @icount_extra: Instructions until next timer event.
> - * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode.
> - * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this
> - * CPU and return to its top level loop (even in non-icount mode).
> - * This allows a single read-compare-cbranch-write sequence to test
> - * for both decrementer underflow and exceptions.
> * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
> * requires that IO only be performed on the last instruction of a TB
> * so that interrupts take effect immediately.
> @@ -322,6 +325,7 @@ struct qemu_work_item;
> * @as: Pointer to the first AddressSpace, for the convenience of targets which
> * only have a single AddressSpace
> * @env_ptr: Pointer to subclass-specific CPUArchState field.
> + * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
> * @gdb_regs: Additional GDB registers.
> * @gdb_num_regs: Number of total registers accessible to GDB.
> * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
> @@ -380,6 +384,7 @@ struct CPUState {
> MemoryRegion *memory;
>
> void *env_ptr; /* CPUArchState */
> + IcountDecr *icount_decr_ptr;
>
> /* Accessed in parallel; all accesses must be atomic */
> struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
> @@ -434,15 +439,6 @@ struct CPUState {
>
> bool ignore_memory_transaction_failures;
>
> - /* Note that this is accessed at the start of every TB via a negative
> - offset from AREG0. Leave this field at the end so as to make the
> - (absolute value) offset as small as possible. This reduces code
> - size, especially for hosts without large memory offsets. */
> - union {
> - uint32_t u32;
> - icount_decr_u16 u16;
> - } icount_decr;
> -
> struct hax_vcpu_state *hax_vcpu;
>
> int hvf_fd;
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index 45ef41ebb2..032a62672e 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -54,7 +54,7 @@ typedef struct SyncClocks {
> #define MAX_DELAY_PRINT_RATE 2000000000LL
> #define MAX_NB_PRINTS 100
>
> -static void align_clocks(SyncClocks *sc, const CPUState *cpu)
> +static void align_clocks(SyncClocks *sc, CPUState *cpu)
> {
> int64_t cpu_icount;
>
> @@ -62,7 +62,7 @@ static void align_clocks(SyncClocks *sc, const CPUState *cpu)
> return;
> }
>
> - cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
> + cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
> sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
> sc->last_cpu_icount = cpu_icount;
>
> @@ -105,15 +105,15 @@ static void print_delay(const SyncClocks *sc)
> }
> }
>
> -static void init_delay_params(SyncClocks *sc,
> - const CPUState *cpu)
> +static void init_delay_params(SyncClocks *sc, CPUState *cpu)
> {
> if (!icount_align_option) {
> return;
> }
> sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
> sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
> - sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
> + sc->last_cpu_icount
> + = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
> if (sc->diff_clk < max_delay) {
> max_delay = sc->diff_clk;
> }
> @@ -467,7 +467,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
> if (cpu->exception_index < 0) {
> #ifndef CONFIG_USER_ONLY
> if (replay_has_exception()
> - && cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
> + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
> /* try to cause an exception pending in the log */
> cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
> }
> @@ -525,7 +525,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
> * Ensure zeroing happens before reading cpu->exit_request or
> * cpu->interrupt_request (see also smp_wmb in cpu_exit())
> */
> - atomic_mb_set(&cpu->icount_decr.u16.high, 0);
> + atomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0);
>
> if (unlikely(atomic_read(&cpu->interrupt_request))) {
> int interrupt_request;
> @@ -596,8 +596,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
> }
>
> /* Finally, check if we need to exit to the main loop. */
> - if (unlikely(atomic_read(&cpu->exit_request)
> - || (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra == 0))) {
> + if (unlikely(atomic_read(&cpu->exit_request))
> + || (use_icount
> + && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) {
> atomic_set(&cpu->exit_request, 0);
> if (cpu->exception_index == -1) {
> cpu->exception_index = EXCP_INTERRUPT;
> @@ -624,7 +625,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
> }
>
> *last_tb = NULL;
> - insns_left = atomic_read(&cpu->icount_decr.u32);
> + insns_left = atomic_read(&cpu_neg(cpu)->icount_decr.u32);
> if (insns_left < 0) {
> /* Something asked us to stop executing chained TBs; just
> * continue round the main loop. Whatever requested the exit
> @@ -643,7 +644,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
> cpu_update_icount(cpu);
> /* Refill decrementer and continue execution. */
> insns_left = MIN(0xffff, cpu->icount_budget);
> - cpu->icount_decr.u16.low = insns_left;
> + cpu_neg(cpu)->icount_decr.u16.low = insns_left;
> cpu->icount_extra = cpu->icount_budget - insns_left;
> if (!cpu->icount_extra) {
> /* Execute any remaining instructions, then let the main loop
> diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
> index 3d25bdcc17..9b215dcc5a 100644
> --- a/accel/tcg/tcg-all.c
> +++ b/accel/tcg/tcg-all.c
> @@ -28,13 +28,12 @@
> #include "sysemu/sysemu.h"
> #include "qom/object.h"
> #include "qemu-common.h"
> -#include "qom/cpu.h"
> +#include "cpu.h"
> #include "sysemu/cpus.h"
> #include "qemu/main-loop.h"
>
> unsigned long tcg_tb_size;
>
> -#ifndef CONFIG_USER_ONLY
> /* mask must never be zero, except for A20 change call */
> static void tcg_handle_interrupt(CPUState *cpu, int mask)
> {
> @@ -51,7 +50,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
> if (!qemu_cpu_is_self(cpu)) {
> qemu_cpu_kick(cpu);
> } else {
> - atomic_set(&cpu->icount_decr.u16.high, -1);
> + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
> if (use_icount &&
> !cpu->can_do_io
> && (mask & ~old_mask) != 0) {
> @@ -59,7 +58,6 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
> }
> }
> }
> -#endif
>
> static int tcg_init(MachineState *ms)
> {
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 52d94facf0..e24ee3a172 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -364,7 +364,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
> assert(use_icount);
> /* Reset the cycle counter to the start of the block
> and shift if to the number of actually executed instructions */
> - cpu->icount_decr.u16.low += num_insns - i;
> + cpu_neg(cpu)->icount_decr.u16.low += num_insns - i;
> }
> restore_state_to_opc(env, tb, data);
>
> @@ -2200,7 +2200,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> if ((env->hflags & MIPS_HFLAG_BMASK) != 0
> && env->active_tc.PC != tb->pc) {
> env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
> - cpu->icount_decr.u16.low++;
> + cpu_neg(cpu)->icount_decr.u16.low++;
> env->hflags &= ~MIPS_HFLAG_BMASK;
> n = 2;
> }
> @@ -2208,7 +2208,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
> && env->pc != tb->pc) {
> env->pc -= 2;
> - cpu->icount_decr.u16.low++;
> + cpu_neg(cpu)->icount_decr.u16.low++;
> env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
> n = 2;
> }
> @@ -2382,7 +2382,7 @@ void cpu_interrupt(CPUState *cpu, int mask)
> {
> g_assert(qemu_mutex_iothread_locked());
> cpu->interrupt_request |= mask;
> - atomic_set(&cpu->icount_decr.u16.high, -1);
> + atomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
> }
>
> /*
> diff --git a/cpus.c b/cpus.c
> index e58e7ab0f6..150f5dd047 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -238,7 +238,8 @@ void qemu_tcg_configure(QemuOpts *opts, Error **errp)
> */
> static int64_t cpu_get_icount_executed(CPUState *cpu)
> {
> - return cpu->icount_budget - (cpu->icount_decr.u16.low + cpu->icount_extra);
> + return (cpu->icount_budget -
> + (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra));
> }
>
> /*
> @@ -1386,12 +1387,12 @@ static void prepare_icount_for_run(CPUState *cpu)
> * each vCPU execution. However u16.high can be raised
> * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
> */
> - g_assert(cpu->icount_decr.u16.low == 0);
> + g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
> g_assert(cpu->icount_extra == 0);
>
> cpu->icount_budget = tcg_get_icount_limit();
> insns_left = MIN(0xffff, cpu->icount_budget);
> - cpu->icount_decr.u16.low = insns_left;
> + cpu_neg(cpu)->icount_decr.u16.low = insns_left;
> cpu->icount_extra = cpu->icount_budget - insns_left;
>
> replay_mutex_lock();
> @@ -1405,7 +1406,7 @@ static void process_icount_data(CPUState *cpu)
> cpu_update_icount(cpu);
>
> /* Reset the counters */
> - cpu->icount_decr.u16.low = 0;
> + cpu_neg(cpu)->icount_decr.u16.low = 0;
> cpu->icount_extra = 0;
> cpu->icount_budget = 0;
>
> diff --git a/qom/cpu.c b/qom/cpu.c
> index 3c5493c96c..6b4632abda 100644
> --- a/qom/cpu.c
> +++ b/qom/cpu.c
> @@ -115,7 +115,7 @@ void cpu_exit(CPUState *cpu)
> atomic_set(&cpu->exit_request, 1);
> /* Ensure cpu_exec will see the exit request after TCG has exited. */
> smp_wmb();
> - atomic_set(&cpu->icount_decr.u16.high, -1);
> + atomic_set(&cpu->icount_decr_ptr->u16.high, -1);
> }
>
> int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
> @@ -264,7 +264,7 @@ static void cpu_common_reset(CPUState *cpu)
> cpu->mem_io_pc = 0;
> cpu->mem_io_vaddr = 0;
> cpu->icount_extra = 0;
> - atomic_set(&cpu->icount_decr.u32, 0);
> + atomic_set(&cpu->icount_decr_ptr->u32, 0);
> cpu->can_do_io = 1;
> cpu->exception_index = -1;
> cpu->crash_occurred = false;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 32/39] cpu: Introduce cpu_set_cpustate_pointers
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 32/39] cpu: Introduce cpu_set_cpustate_pointers Richard Henderson
@ 2019-05-09 20:32 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:37 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Consolidate some boilerplate from foo_cpu_initfn.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-all.h | 11 +++++++++++
> target/alpha/cpu.c | 3 +--
> target/arm/cpu.c | 3 +--
> target/cris/cpu.c | 3 +--
> target/hppa/cpu.c | 2 +-
> target/i386/cpu.c | 3 +--
> target/lm32/cpu.c | 3 +--
> target/m68k/cpu.c | 4 +---
> target/microblaze/cpu.c | 3 +--
> target/mips/cpu.c | 3 +--
> target/moxie/cpu.c | 3 +--
> target/nios2/cpu.c | 6 ++----
> target/openrisc/cpu.c | 3 +--
> target/ppc/translate_init.inc.c | 3 +--
> target/riscv/cpu.c | 3 +--
> target/s390x/cpu.c | 9 +++++----
> target/sh4/cpu.c | 3 +--
> target/sparc/cpu.c | 3 +--
> target/tilegx/cpu.c | 4 +---
> target/tricore/cpu.c | 4 +---
> target/unicore32/cpu.c | 3 +--
> target/xtensa/cpu.c | 3 +--
> 22 files changed, 37 insertions(+), 48 deletions(-)
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index c62f07b354..71154070a7 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -371,6 +371,17 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
>
> int cpu_exec(CPUState *cpu);
>
> +/**
> + * cpu_set_cpustate_pointers(cpu)
> + * @cpu: The cpu object
> + *
> + * Set the generic pointers in CPUState into the outer object.
> + */
> +static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
> +{
> + cpu->parent_obj.env_ptr = &cpu->env;
> +}
> +
> /**
> * env_archcpu(env)
> * @env: The architecture environment
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index ad3588a44a..b771b9f3fe 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -191,11 +191,10 @@ static void ev67_cpu_initfn(Object *obj)
>
> static void alpha_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> AlphaCPU *cpu = ALPHA_CPU(obj);
> CPUAlphaState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> env->lock_addr = -1;
> #if defined(CONFIG_USER_ONLY)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index a181fa8dc1..79d5096270 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -698,10 +698,9 @@ static void cpreg_hashtable_data_destroy(gpointer data)
>
> static void arm_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> ARMCPU *cpu = ARM_CPU(obj);
>
> - cs->env_ptr = &cpu->env;
> + cpu_set_cpustate_pointers(cpu);
> cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
> g_free, cpreg_hashtable_data_destroy);
>
> diff --git a/target/cris/cpu.c b/target/cris/cpu.c
> index 75729bfdd5..070f8be363 100644
> --- a/target/cris/cpu.c
> +++ b/target/cris/cpu.c
> @@ -172,12 +172,11 @@ static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
>
> static void cris_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> CRISCPU *cpu = CRIS_CPU(obj);
> CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
> CPUCRISState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> env->pregs[PR_VR] = ccc->vr;
>
> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
> index e64f48581e..fdff057793 100644
> --- a/target/hppa/cpu.c
> +++ b/target/hppa/cpu.c
> @@ -134,7 +134,7 @@ static void hppa_cpu_initfn(Object *obj)
> HPPACPU *cpu = HPPA_CPU(obj);
> CPUHPPAState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> cs->exception_index = -1;
> cpu_hppa_loaded_fr0(env);
> cpu_hppa_put_psw(env, PSW_W);
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 5b84629f91..7eff4c4dea 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -5588,13 +5588,12 @@ static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
>
> static void x86_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> X86CPU *cpu = X86_CPU(obj);
> X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
> CPUX86State *env = &cpu->env;
> FeatureWord w;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> object_property_add(obj, "family", "int",
> x86_cpuid_version_get_family,
> diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
> index 282da19994..ebcbd2faa8 100644
> --- a/target/lm32/cpu.c
> +++ b/target/lm32/cpu.c
> @@ -142,11 +142,10 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void lm32_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> LM32CPU *cpu = LM32_CPU(obj);
> CPULM32State *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> env->flags = 0;
> }
> diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
> index 582e3a73b3..930e1be59f 100644
> --- a/target/m68k/cpu.c
> +++ b/target/m68k/cpu.c
> @@ -238,11 +238,9 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void m68k_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> M68kCPU *cpu = M68K_CPU(obj);
> - CPUM68KState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> }
>
> static const VMStateDescription vmstate_m68k_cpu = {
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 5596cd5485..db4dcdb4ad 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -221,11 +221,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void mb_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
> CPUMBState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index e217fb3e36..3d1b693eef 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -152,12 +152,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void mips_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> MIPSCPU *cpu = MIPS_CPU(obj);
> CPUMIPSState *env = &cpu->env;
> MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> env->cpu_model = mcc->cpu_def;
> }
>
> diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
> index 46434e65ba..316ee9c534 100644
> --- a/target/moxie/cpu.c
> +++ b/target/moxie/cpu.c
> @@ -74,10 +74,9 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void moxie_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> MoxieCPU *cpu = MOXIE_CPU(obj);
>
> - cs->env_ptr = &cpu->env;
> + cpu_set_cpustate_pointers(cpu);
> }
>
> static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
> diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
> index fbfaa2ce26..43677fa802 100644
> --- a/target/nios2/cpu.c
> +++ b/target/nios2/cpu.c
> @@ -66,14 +66,12 @@ static void nios2_cpu_reset(CPUState *cs)
>
> static void nios2_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> Nios2CPU *cpu = NIOS2_CPU(obj);
> - CPUNios2State *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> #if !defined(CONFIG_USER_ONLY)
> - mmu_init(env);
> + mmu_init(&cpu->env);
> #endif
> }
>
> diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
> index d125236977..5177575821 100644
> --- a/target/openrisc/cpu.c
> +++ b/target/openrisc/cpu.c
> @@ -92,10 +92,9 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void openrisc_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> OpenRISCCPU *cpu = OPENRISC_CPU(obj);
>
> - cs->env_ptr = &cpu->env;
> + cpu_set_cpustate_pointers(cpu);
> }
>
> /* CPU models */
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 6343e25624..739c14fd26 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -10473,12 +10473,11 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
>
> static void ppc_cpu_instance_init(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> PowerPCCPU *cpu = POWERPC_CPU(obj);
> PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> CPUPPCState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
>
> env->msr_mask = pcc->msr_mask;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bcf4eaeb8..35e69a9e12 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -315,10 +315,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>
> static void riscv_cpu_init(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> - cs->env_ptr = &cpu->env;
> + cpu_set_cpustate_pointers(cpu);
> }
>
> static const VMStateDescription vmstate_riscv_cpu = {
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index b58ef0a8ef..16bcb933ec 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -282,17 +282,18 @@ static void s390_cpu_initfn(Object *obj)
> {
> CPUState *cs = CPU(obj);
> S390CPU *cpu = S390_CPU(obj);
> - CPUS390XState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> object_property_add(obj, "crash-information", "GuestPanicInformation",
> s390_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
> s390_cpu_model_register_props(obj);
> #if !defined(CONFIG_USER_ONLY)
> - env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
> - env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
> + cpu->env.tod_timer =
> + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
> + cpu->env.cpu_timer =
> + timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
> s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
> #endif
> }
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index da2799082e..62a9123173 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -194,11 +194,10 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void superh_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> SuperHCPU *cpu = SUPERH_CPU(obj);
> CPUSH4State *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> env->movcal_backup_tail = &(env->movcal_backup);
> }
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 4654c2a6a0..90109754eb 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -774,12 +774,11 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void sparc_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> SPARCCPU *cpu = SPARC_CPU(obj);
> SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
> CPUSPARCState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> if (scc->cpu_def) {
> env->def = *scc->cpu_def;
> diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
> index b9d37105fa..0bfd4187b8 100644
> --- a/target/tilegx/cpu.c
> +++ b/target/tilegx/cpu.c
> @@ -99,11 +99,9 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void tilegx_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> TileGXCPU *cpu = TILEGX_CPU(obj);
> - CPUTLGState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> }
>
> static void tilegx_cpu_do_interrupt(CPUState *cs)
> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
> index e8d37e4040..fc3c3075b3 100644
> --- a/target/tricore/cpu.c
> +++ b/target/tricore/cpu.c
> @@ -104,11 +104,9 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void tricore_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> TriCoreCPU *cpu = TRICORE_CPU(obj);
> - CPUTriCoreState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> }
>
> static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
> diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
> index 2b49d1ca40..700c5c5585 100644
> --- a/target/unicore32/cpu.c
> +++ b/target/unicore32/cpu.c
> @@ -103,11 +103,10 @@ static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void uc32_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> UniCore32CPU *cpu = UNICORE32_CPU(obj);
> CPUUniCore32State *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
>
> #ifdef CONFIG_USER_ONLY
> env->uncached_asr = ASR_MODE_USER;
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index a54dbe4260..9461ebad02 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -138,12 +138,11 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
>
> static void xtensa_cpu_initfn(Object *obj)
> {
> - CPUState *cs = CPU(obj);
> XtensaCPU *cpu = XTENSA_CPU(obj);
> XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
> CPUXtensaState *env = &cpu->env;
>
> - cs->env_ptr = env;
> + cpu_set_cpustate_pointers(cpu);
> env->config = xcc->config;
>
> #ifndef CONFIG_USER_ONLY
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 33/39] cpu: Introduce CPUNegativeOffsetState
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 33/39] cpu: Introduce CPUNegativeOffsetState Richard Henderson
@ 2019-05-09 20:36 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-09 20:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:26 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Nothing in there so far, but all of the plumbing done
> within the target ArchCPU state.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-all.h | 24 ++++++++++++++++++++++++
> include/exec/cpu-defs.h | 8 ++++++++
> target/alpha/cpu.h | 1 +
> target/arm/cpu.h | 1 +
> target/cris/cpu.h | 1 +
> target/hppa/cpu.h | 1 +
> target/i386/cpu.h | 1 +
> target/lm32/cpu.h | 1 +
> target/m68k/cpu.h | 1 +
> target/microblaze/cpu.h | 5 +++--
> target/mips/cpu.h | 1 +
> target/moxie/cpu.h | 1 +
> target/nios2/cpu.h | 2 ++
> target/openrisc/cpu.h | 2 +-
> target/ppc/cpu.h | 2 ++
> target/riscv/cpu.h | 1 +
> target/s390x/cpu.h | 1 +
> target/sh4/cpu.h | 1 +
> target/sparc/cpu.h | 1 +
> target/tilegx/cpu.h | 1 +
> target/tricore/cpu.h | 1 +
> target/unicore32/cpu.h | 1 +
> target/xtensa/cpu.h | 1 +
> 23 files changed, 57 insertions(+), 3 deletions(-)
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index 71154070a7..5ae83405c8 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -404,4 +404,28 @@ static inline CPUState *env_cpu(CPUArchState *env)
> return &env_archcpu(env)->parent_obj;
> }
>
> +/**
> + * env_neg(env)
> + * @env: The architecture environment
> + *
> + * Return the CPUNegativeOffsetState associated with the environment.
> + */
> +static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
> +{
> + ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
> + return &arch_cpu->neg;
> +}
> +
> +/**
> + * cpu_neg(cpu)
> + * @cpu: The generic CPUState
> + *
> + * Return the CPUNegativeOffsetState associated with the cpu.
> + */
> +static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
> +{
> + ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
> + return &arch_cpu->neg;
> +}
> +
> #endif /* CPU_ALL_H */
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index fbe8945606..ad97991faf 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -227,4 +227,12 @@ typedef struct CPUTLB {
>
> #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> +/*
> + * This structure must be placed in ArchCPU immedately
> + * before CPUArchState, as a field named "neg".
> + */
> +typedef struct CPUNegativeOffsetState {
> + /* Empty */
> +} CPUNegativeOffsetState;
> +
> #endif
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index 66782cf5d4..f4bb67c101 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -267,6 +267,7 @@ struct AlphaCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUAlphaState env;
>
> /* This alarm doesn't exist in real hardware; we wish it did. */
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 23beb1de9a..909cb4604d 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -719,6 +719,7 @@ struct ARMCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUARMState env;
>
> /* Coprocessor information */
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index c19fdcec1e..eeab483dba 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -180,6 +180,7 @@ struct CRISCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUCRISState env;
> };
>
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 58b2bf2933..0661ff60c1 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -218,6 +218,7 @@ struct HPPACPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUHPPAState env;
> QEMUTimer *alarm_timer;
> };
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index a9cfb42b22..43bb6ab841 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1368,6 +1368,7 @@ struct X86CPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUX86State env;
>
> bool hyperv_vapic;
> diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
> index 4234a439a3..0ec898eb1d 100644
> --- a/target/lm32/cpu.h
> +++ b/target/lm32/cpu.h
> @@ -186,6 +186,7 @@ struct LM32CPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPULM32State env;
>
> uint32_t revision;
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 02fbff3625..096d1eb588 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -160,6 +160,7 @@ struct M68kCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUM68KState env;
> };
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 1becb9270b..732653caed 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -287,6 +287,9 @@ struct MicroBlazeCPU {
>
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> + CPUMBState env;
> +
> /* Microblaze Configuration Settings */
> struct {
> bool stackprot;
> @@ -306,8 +309,6 @@ struct MicroBlazeCPU {
> char *version;
> uint8_t pvr;
> } cfg;
> -
> - CPUMBState env;
> };
>
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 52286fcb0e..2d9c5f26eb 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1048,6 +1048,7 @@ struct MIPSCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUMIPSState env;
> };
>
> diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
> index ebe1c66f52..f5ee8a02f4 100644
> --- a/target/moxie/cpu.h
> +++ b/target/moxie/cpu.h
> @@ -87,6 +87,7 @@ typedef struct MoxieCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUMoxieState env;
> } MoxieCPU;
>
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index 96c8193179..cd06a2ef41 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -181,7 +181,9 @@ typedef struct Nios2CPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUNios2State env;
> +
> bool mmu_present;
> uint32_t pid_num_bits;
> uint32_t tlb_num_ways;
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 150227d450..e1acd48652 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -313,8 +313,8 @@ typedef struct OpenRISCCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUOpenRISCState env;
> -
> } OpenRISCCPU;
>
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index f970853556..bb57496212 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1184,7 +1184,9 @@ struct PowerPCCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUPPCState env;
> +
> int vcpu_id;
> uint32_t compat_pvr;
> PPCVirtualHypervisor *vhyp;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 818692dde5..30a01e8386 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -208,6 +208,7 @@ typedef struct RISCVCPU {
> /*< private >*/
> CPUState parent_obj;
> /*< public >*/
> + CPUNegativeOffsetState neg;
> CPURISCVState env;
> } RISCVCPU;
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 971dc0ccbd..ebcf7863e4 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -156,6 +156,7 @@ struct S390CPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUS390XState env;
> S390CPUModel *model;
> /* needed for live migration */
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index 3f2f4043e0..944854dbe0 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -204,6 +204,7 @@ struct SuperHCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUSH4State env;
> };
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index b170dd592e..ae9ac07a9d 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -529,6 +529,7 @@ struct SPARCCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUSPARCState env;
> };
>
> diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
> index 643b7dbd17..deb3e836ea 100644
> --- a/target/tilegx/cpu.h
> +++ b/target/tilegx/cpu.h
> @@ -135,6 +135,7 @@ typedef struct TileGXCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUTLGState env;
> } TileGXCPU;
>
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index 581e68e37c..43ef29b6bd 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -205,6 +205,7 @@ struct TriCoreCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUTriCoreState env;
> };
>
> diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
> index abb36b5d48..140c590ec1 100644
> --- a/target/unicore32/cpu.h
> +++ b/target/unicore32/cpu.h
> @@ -73,6 +73,7 @@ struct UniCore32CPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUUniCore32State env;
> };
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 748b6fca25..1bbb839bed 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -526,6 +526,7 @@ struct XtensaCPU {
> CPUState parent_obj;
> /*< public >*/
>
> + CPUNegativeOffsetState neg;
> CPUXtensaState env;
> };
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 21:53 ` Philippe Mathieu-Daudé
@ 2019-05-09 21:19 ` Aleksandar Markovic
0 siblings, 0 replies; 81+ messages in thread
From: Aleksandar Markovic @ 2019-05-09 21:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: Richard Henderson, qemu-devel
On May 8, 2019 11:53 PM, "Philippe Mathieu-Daudé" <philmd@redhat.com> wrote:
>
> Hi Richard, Aleksandar.
>
> On 5/8/19 4:32 PM, Richard Henderson wrote:
> > On 5/8/19 1:15 AM, Aleksandar Markovic wrote:
> >>
> >> On May 8, 2019 2:19 AM, "Richard Henderson" <
richard.henderson@linaro.org
> >> <mailto:richard.henderson@linaro.org>> wrote:
> >>>
> >>>
> >>>
> >>
> >> This commit message doesnˊt explain the reason for the change, and why
is this
> >> an improvement. The underlyng reason for distingishing between
env_cpu and
> >> env_archcpu cases is not explained too.
> >
> > It's certainly explained in the preceeding patches that introduce those
functions.
> >
> > Are you suggesting that it is beneficial to copy-and-paste a common
block
> > explanation into 21 commit messages for each of target/foo/?
>
>
> *) Richard:
>
> I tried to put myself in Aleksandar shoes. I believe Aleksandar is
> worried about his MIPS maintainer duty, wanting to Ack-by this patch.
>
> It is true that out of the context of the series, it is hard to see what
> is the problem you try to solve.
>
> You could copy/paste the explanation you used previously,
> with s/$arch/mips/:
>
> "Cleanup in the boilerplate that each target must define."
>
> "Combined uses of CPU(mips_env_get_cpu()) were failures to use
> the more proper, ENV_GET_CPU macro, now replaced by env_cpu."
>
> Now to clearly understand this patch we still need to look at the
> previous two arch-generic patches
> - "cpu: Replace ENV_GET_CPU with env_cpu" and
> - "cpu: Introduce env_archcpu".
>
> Also, it is tedious to copy/paste the same explanation, but thinking of
> forks or stable branch that cherry-pick not all but some commits of a
> series, it might be useful.
>
> Another guess is Aleksandar might have looked at the series cover, which
> is not well explained as your v2:
> https://lists.gnu.org/archive/html/qemu-devel/2019-03/msg07635.html
> I think you mistakenly copied the v1 blurb instead of the v2 one.
>
> So at some point I can understand Aleksandar frustation.
>
>
> *) Aleksandar:
>
> This series fall under the "Overall Guest CPU cores (TCG)" section
> maintained by Richard and Paolo. I think you have to see this series as
> a whole to understand the benefits of it.
>
> With the same reasoning, I believe you shouldn't worry to not give your
> Ack if you don't feel comfortable.
>
> I think Richard sent this v3 to simply address comments raised by the
> previous reviewer during v1/v2, where there was some discussions: I took
> it as "this is the last round before getting merged" (unless someone
> object).
>
> It is hard to make everybody happy on a such big project, with so many
> areas, lines of code, people, culture, etc... I believe we all try to
> give our best, neither the commiters nor the reviewers are perfect, but
> slowly we help this project to improve :)
>
>
> Best regards,
>
> Phil.
Richard, Philippe,
A commit message along the line that Philippe put together would be OK.
I can talk about this commit only - if other submaintainers are fine with
empty commit messages in key files for their target, that is their
business. I am certainly opposed to any empty commit messages in MIPS
files, and please, Richard, include a decent commit message for this
commit. I don't think I am asking much.
Thanks,
Aleksandar
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 35/39] cpu: Move the softmmu tlb to CPUNegativeOffsetState
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 35/39] cpu: Move the softmmu tlb " Richard Henderson
@ 2019-05-10 20:57 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-10 20:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:29 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We have for some time had code within the tcg backends to
> handle large positive offsets from env. This move makes
> sure that need not happen. Indeed, we are able to assert
> at build time that simple offsets suffice for all hosts.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-defs.h | 22 +++++++++++++-------
> tcg/aarch64/tcg-target.inc.c | 29 ++++++--------------------
> tcg/arm/tcg-target.inc.c | 40 ++++++++----------------------------
> tcg/i386/tcg-target.inc.c | 6 ++++--
> tcg/mips/tcg-target.inc.c | 39 ++++++++---------------------------
> tcg/ppc/tcg-target.inc.c | 30 ++++++++-------------------
> tcg/riscv/tcg-target.inc.c | 31 +++++++---------------------
> tcg/s390/tcg-target.inc.c | 11 +++++-----
> tcg/sparc/tcg-target.inc.c | 32 +++++++++--------------------
> 9 files changed, 74 insertions(+), 166 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 3971910653..4cde7d611c 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -178,13 +178,14 @@ typedef struct CPUTLBDesc {
>
> /*
> * Data elements that are per MMU mode, accessed by the fast path.
> + * The structure is aligned to aid loading the pair with one insn.
> */
> typedef struct CPUTLBDescFast {
> /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
> uintptr_t mask;
> /* The array of tlb entries itself. */
> CPUTLBEntry *table;
> -} CPUTLBDescFast;
> +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
>
> /*
> * Data elements that are shared between all MMU modes.
> @@ -211,28 +212,35 @@ typedef struct CPUTLBCommon {
> /*
> * The entire softmmu tlb, for all MMU modes.
> * The meaning of each of the MMU modes is defined in the target code.
> + * Since this is placed within CPUNegativeOffsetState, the smallest
> + * negative offsets are at the end of the struct.
> */
> typedef struct CPUTLB {
> - CPUTLBDescFast f[NB_MMU_MODES];
> - CPUTLBDesc d[NB_MMU_MODES];
> CPUTLBCommon c;
> + CPUTLBDesc d[NB_MMU_MODES];
> + CPUTLBDescFast f[NB_MMU_MODES];
> } CPUTLB;
>
> -/* There are target-specific members named "tlb". This is temporary. */
> -#define CPU_COMMON CPUTLB tlb_;
> -#define env_tlb(ENV) (&(ENV)->tlb_)
> +#define env_tlb(ENV) (&env_neg(ENV)->tlb)
> +
> +/* This will be used by TCG backends to compute offsets. */
> +#define TLB_MASK_TABLE_OFS(IDX) \
> + ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env))
>
> #else
>
> -#define CPU_COMMON /* Nothing */
> +typedef struct CPUTLB { } CPUTLB;
>
> #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> +#define CPU_COMMON /* Nothing */
> +
> /*
> * This structure must be placed in ArchCPU immedately
> * before CPUArchState, as a field named "neg".
> */
> typedef struct CPUNegativeOffsetState {
> + CPUTLB tlb;
> IcountDecr icount_decr;
> } CPUNegativeOffsetState;
>
> diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
> index 72cf4c5ff8..afac018301 100644
> --- a/tcg/aarch64/tcg-target.inc.c
> +++ b/tcg/aarch64/tcg-target.inc.c
> @@ -1455,9 +1455,9 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
> label->label_ptr[0] = label_ptr;
> }
>
> -/* We expect to use a 24-bit unsigned offset from ENV. */
> -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
> - > 0xffffff);
> +/* We expect to use a 7-bit scaled negative offset from ENV. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512);
>
> /* Load and compare a TLB entry, emitting the conditional jump to the
> slow path for the failure case, which will be patched later when finalizing
> @@ -1467,8 +1467,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
> tcg_insn_unit **label_ptr, int mem_index,
> bool is_read)
> {
> - int mask_ofs = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - int table_ofs = offsetof(CPUArchState, tlb_.f[mem_index].table);
> + int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
> + int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
> unsigned a_bits = get_alignment_bits(opc);
> unsigned s_bits = opc & MO_SIZE;
> unsigned a_mask = (1u << a_bits) - 1;
> @@ -1477,24 +1478,6 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
> TCGType mask_type;
> uint64_t compare_mask;
>
> - if (table_ofs > 0xfff) {
> - int table_hi = table_ofs & ~0xfff;
> - int mask_hi = mask_ofs & ~0xfff;
> -
> - table_base = TCG_REG_X1;
> - if (mask_hi == table_hi) {
> - mask_base = table_base;
> - } else if (mask_hi) {
> - mask_base = TCG_REG_X0;
> - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64,
> - mask_base, TCG_AREG0, mask_hi);
> - }
> - tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64,
> - table_base, TCG_AREG0, table_hi);
> - mask_ofs -= mask_hi;
> - table_ofs -= table_hi;
> - }
> -
> mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32
> ? TCG_TYPE_I64 : TCG_TYPE_I32);
>
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index 28b911e550..ad32b04e13 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -1220,9 +1220,9 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
>
> #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
>
> -/* We expect to use a 20-bit unsigned offset from ENV. */
> -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
> - > 0xfffff);
> +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
>
> /* Load and compare a TLB entry, leaving the flags set. Returns the register
> containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
> @@ -1232,39 +1232,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
> {
> int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
> : offsetof(CPUTLBEntry, addr_write));
> - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
> - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
> + int fast_off = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
> + int table_off = fast_off + offsetof(CPUTLBDescFast, table);
> unsigned s_bits = opc & MO_SIZE;
> unsigned a_bits = get_alignment_bits(opc);
>
> - if (table_off > 0xfff) {
> - int mask_hi = mask_off & ~0xfff;
> - int table_hi = table_off & ~0xfff;
> - int rot;
> -
> - table_base = TCG_REG_R2;
> - if (mask_hi == table_hi) {
> - mask_base = table_base;
> - } else if (mask_hi) {
> - mask_base = TCG_REG_TMP;
> - rot = encode_imm(mask_hi);
> - assert(rot >= 0);
> - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, mask_base, TCG_AREG0,
> - rotl(mask_hi, rot) | (rot << 7));
> - }
> - rot = encode_imm(table_hi);
> - assert(rot >= 0);
> - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, table_base, TCG_AREG0,
> - rotl(table_hi, rot) | (rot << 7));
> -
> - mask_off -= mask_hi;
> - table_off -= table_hi;
> - }
> -
> /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
> - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, mask_base, mask_off);
> - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, table_base, table_off);
> + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off);
> + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off);
>
> /* Extract the tlb index from the address into TMP. */
> tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrlo,
> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
> index b2e11a4b7c..fd6a9160ac 100644
> --- a/tcg/i386/tcg-target.inc.c
> +++ b/tcg/i386/tcg-target.inc.c
> @@ -1655,10 +1655,12 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
> TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
>
> tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
> - offsetof(CPUArchState, tlb_.f[mem_index].mask));
> + TLB_MASK_TABLE_OFS(mem_index) +
> + offsetof(CPUTLBDescFast, mask));
>
> tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
> - offsetof(CPUArchState, tlb_.f[mem_index].table));
> + TLB_MASK_TABLE_OFS(mem_index) +
> + offsetof(CPUTLBDescFast, table));
>
> /* If the required alignment is at least as large as the access, simply
> copy the address and mask. For lesser alignments, check that we don't
> diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
> index 45b26e596f..46f7749cbc 100644
> --- a/tcg/mips/tcg-target.inc.c
> +++ b/tcg/mips/tcg-target.inc.c
> @@ -1201,6 +1201,10 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
> return i;
> }
>
> +/* We expect to use a 16-bit negative offset from ENV. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
> +
> /*
> * Perform the tlb comparison operation.
> * The complete host address is placed in BASE.
> @@ -1214,42 +1218,17 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
> unsigned s_bits = opc & MO_SIZE;
> unsigned a_bits = get_alignment_bits(opc);
> int mem_index = get_mmuidx(oi);
> - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> + int fast_off = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
> + int table_off = fast_off + offsetof(CPUTLBDescFast, table);
> int add_off = offsetof(CPUTLBEntry, addend);
> int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
> : offsetof(CPUTLBEntry, addr_write));
> - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
> target_ulong mask;
>
> - if (table_off > 0x7fff) {
> - int mask_hi = mask_off - (int16_t)mask_off;
> - int table_hi = table_off - (int16_t)table_off;
> -
> - table_base = TCG_TMP1;
> - if (likely(mask_hi == table_hi)) {
> - mask_base = table_base;
> - tcg_out_opc_imm(s, OPC_LUI, mask_base, TCG_REG_ZERO, mask_hi >> 16);
> - tcg_out_opc_reg(s, ALIAS_PADD, mask_base, mask_base, TCG_AREG0);
> - mask_off -= mask_hi;
> - table_off -= mask_hi;
> - } else {
> - if (mask_hi != 0) {
> - mask_base = TCG_TMP0;
> - tcg_out_opc_imm(s, OPC_LUI,
> - mask_base, TCG_REG_ZERO, mask_hi >> 16);
> - tcg_out_opc_reg(s, ALIAS_PADD,
> - mask_base, mask_base, TCG_AREG0);
> - }
> - table_off -= mask_off;
> - mask_off -= mask_hi;
> - tcg_out_opc_imm(s, ALIAS_PADDI, table_base, mask_base, mask_off);
> - }
> - }
> -
> /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
> - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, mask_base, mask_off);
> - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, table_base, table_off);
> + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
> + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
>
> /* Extract the TLB index from the address into TMP3. */
> tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
> index a248603bc5..400cee31ce 100644
> --- a/tcg/ppc/tcg-target.inc.c
> +++ b/tcg/ppc/tcg-target.inc.c
> @@ -1497,6 +1497,10 @@ static void * const qemu_st_helpers[16] = {
> [MO_BEQ] = helper_be_stq_mmu,
> };
>
> +/* We expect to use a 16-bit negative offset from ENV. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
> +
> /* Perform the TLB load and compare. Places the result of the comparison
> in CR7, loads the addend of the TLB into R3, and returns the register
> containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
> @@ -1509,31 +1513,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
> = (is_read
> ? offsetof(CPUTLBEntry, addr_read)
> : offsetof(CPUTLBEntry, addr_write));
> - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
> - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
> + int fast_off = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
> + int table_off = fast_off + offsetof(CPUTLBDescFast, table);
> unsigned s_bits = opc & MO_SIZE;
> unsigned a_bits = get_alignment_bits(opc);
>
> - if (table_off > 0x7fff) {
> - int mask_hi = mask_off - (int16_t)mask_off;
> - int table_hi = table_off - (int16_t)table_off;
> -
> - table_base = TCG_REG_R4;
> - if (mask_hi == table_hi) {
> - mask_base = table_base;
> - } else if (mask_hi) {
> - mask_base = TCG_REG_R3;
> - tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16));
> - }
> - tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16));
> - mask_off -= mask_hi;
> - table_off -= table_hi;
> - }
> -
> /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
> - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off);
> - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off);
> + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off);
> + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off);
>
> /* Extract the page index, shifted into place for tlb index. */
> if (TCG_TARGET_REG_BITS == 32) {
> diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
> index 85acbb9514..029d9a0fb2 100644
> --- a/tcg/riscv/tcg-target.inc.c
> +++ b/tcg/riscv/tcg-target.inc.c
> @@ -961,6 +961,10 @@ static void * const qemu_st_helpers[16] = {
> /* We don't support oversize guests */
> QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS);
>
> +/* We expect to use a 12-bit negative offset from ENV. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11));
> +
> static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
> TCGReg addrh, TCGMemOpIdx oi,
> tcg_insn_unit **label_ptr, bool is_load)
> @@ -970,32 +974,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
> unsigned a_bits = get_alignment_bits(opc);
> tcg_target_long compare_mask;
> int mem_index = get_mmuidx(oi);
> - int mask_off, table_off;
> + int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
> + int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
> TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
>
> - mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
> - if (table_off > 0x7ff) {
> - int mask_hi = mask_off - sextreg(mask_off, 0, 12);
> - int table_hi = table_off - sextreg(table_off, 0, 12);
> -
> - if (likely(mask_hi == table_hi)) {
> - mask_base = table_base = TCG_REG_TMP1;
> - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi);
> - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0);
> - mask_off -= mask_hi;
> - table_off -= mask_hi;
> - } else {
> - mask_base = TCG_REG_TMP0;
> - table_base = TCG_REG_TMP1;
> - tcg_out_opc_upper(s, OPC_LUI, mask_base, mask_hi);
> - tcg_out_opc_reg(s, OPC_ADD, mask_base, mask_base, TCG_AREG0);
> - table_off -= mask_off;
> - mask_off -= mask_hi;
> - tcg_out_opc_imm(s, OPC_ADDI, table_base, mask_base, mask_off);
> - }
> - }
> -
> tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off);
> tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off);
>
> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
> index 1f578ea980..0ce129a369 100644
> --- a/tcg/s390/tcg-target.inc.c
> +++ b/tcg/s390/tcg-target.inc.c
> @@ -1537,9 +1537,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
> #if defined(CONFIG_SOFTMMU)
> #include "tcg-ldst.inc.c"
>
> -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */
> -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_.f[NB_MMU_MODES - 1].table)
> - > 0x7ffff);
> +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
>
> /* Load and compare a TLB entry, leaving the flags set. Loads the TLB
> addend into R2. Returns a register with the santitized guest address. */
> @@ -1550,8 +1550,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
> unsigned a_bits = get_alignment_bits(opc);
> unsigned s_mask = (1 << s_bits) - 1;
> unsigned a_mask = (1 << a_bits) - 1;
> - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
> + int fast_off = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
> + int table_off = fast_off + offsetof(CPUTLBDescFast, table);
> int ofs, a_off;
> uint64_t tlb_mask;
>
> diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
> index be10124e11..fe7524a802 100644
> --- a/tcg/sparc/tcg-target.inc.c
> +++ b/tcg/sparc/tcg-target.inc.c
> @@ -1061,6 +1061,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
> }
>
> #if defined(CONFIG_SOFTMMU)
> +
> +/* We expect to use a 13-bit negative offset from ENV. */
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12));
> +
> /* Perform the TLB load and compare.
>
> Inputs:
> @@ -1077,9 +1082,9 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
> static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
> TCGMemOp opc, int which)
> {
> - int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask);
> - int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table);
> - TCGReg base = TCG_AREG0;
> + int fast_off = TLB_MASK_TABLE_OFS(mem_index);
> + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
> + int table_off = fast_off + offsetof(CPUTLBDescFast, table);
> const TCGReg r0 = TCG_REG_O0;
> const TCGReg r1 = TCG_REG_O1;
> const TCGReg r2 = TCG_REG_O2;
> @@ -1087,26 +1092,9 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
> unsigned a_bits = get_alignment_bits(opc);
> tcg_target_long compare_mask;
>
> - if (!check_fit_i32(table_off, 13)) {
> - int table_hi;
> -
> - base = r1;
> - if (table_off <= 2 * 0xfff) {
> - table_hi = 0xfff;
> - tcg_out_arithi(s, base, TCG_AREG0, table_hi, ARITH_ADD);
> - } else {
> - table_hi = table_off & ~0x3ff;
> - tcg_out_sethi(s, base, table_hi);
> - tcg_out_arith(s, base, TCG_AREG0, base, ARITH_ADD);
> - }
> - mask_off -= table_hi;
> - table_off -= table_hi;
> - tcg_debug_assert(check_fit_i32(mask_off, 13));
> - }
> -
> /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
> - tcg_out_ld(s, TCG_TYPE_PTR, r0, base, mask_off);
> - tcg_out_ld(s, TCG_TYPE_PTR, r1, base, table_off);
> + tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off);
> + tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off);
>
> /* Extract the page index, shifted into place for tlb index. */
> tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON Richard Henderson
@ 2019-05-10 20:58 ` Alistair Francis
2019-05-11 13:21 ` Aleksandar Markovic
1 sibling, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-10 20:58 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:32 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This macro is now always empty, so remove it. This leaves the
> entire contents of CPUArchState under the control of the guest
> architecture.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu-defs.h | 2 --
> target/alpha/cpu.h | 3 ---
> target/arm/cpu.h | 4 +---
> target/cris/cpu.h | 2 --
> target/hppa/cpu.h | 3 ---
> target/i386/cpu.h | 4 +---
> target/lm32/cpu.h | 2 --
> target/m68k/cpu.h | 2 --
> target/microblaze/cpu.h | 2 --
> target/mips/cpu.h | 2 --
> target/moxie/cpu.h | 3 ---
> target/nios2/cpu.h | 2 --
> target/openrisc/cpu.h | 2 --
> target/ppc/cpu.h | 2 --
> target/riscv/cpu.h | 4 ----
> target/s390x/cpu.h | 2 --
> target/sh4/cpu.h | 2 --
> target/sparc/cpu.h | 2 --
> target/tilegx/cpu.h | 2 --
> target/tricore/cpu.h | 2 --
> target/unicore32/cpu.h | 2 --
> target/xtensa/cpu.h | 2 --
> 22 files changed, 2 insertions(+), 51 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 4cde7d611c..1f75a97701 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB;
>
> #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> -#define CPU_COMMON /* Nothing */
> -
> /*
> * This structure must be placed in ArchCPU immedately
> * before CPUArchState, as a field named "neg".
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index f4bb67c101..5bd90b7ce5 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -246,9 +246,6 @@ struct CPUAlphaState {
> /* This alarm doesn't exist in real hardware; we wish it did. */
> uint64_t alarm_expire;
>
> - /* Those resources are used only in QEMU core */
> - CPU_COMMON
> -
> int error_code;
>
> uint32_t features;
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 909cb4604d..135a16a351 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -643,9 +643,7 @@ typedef struct CPUARMState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> - /* Fields after CPU_COMMON are preserved across CPU reset. */
> + /* Fields after this point are preserved across CPU reset. */
>
> /* Internal CPU feature flags. */
> uint64_t features;
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index eeab483dba..6dc4502e9a 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -163,8 +163,6 @@ typedef struct CPUCRISState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Members from load_info on are preserved across resets. */
> void *load_info;
> } CPUCRISState;
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 0661ff60c1..3ed2ac3c25 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -197,9 +197,6 @@ struct CPUHPPAState {
> target_ureg cr_back[2]; /* back of cr17/cr18 */
> target_ureg shadow[7]; /* shadow registers */
>
> - /* Those resources are used only in QEMU core */
> - CPU_COMMON
> -
> /* ??? The number of entries isn't specified by the architecture. */
> /* ??? Implement a unified itlb/dtlb for the moment. */
> /* ??? We should use a more intelligent data structure. */
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 43bb6ab841..8069e5b19d 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1288,9 +1288,7 @@ typedef struct CPUX86State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> - /* Fields after CPU_COMMON are preserved across CPU reset. */
> + /* Fields after this point are preserved across CPU reset. */
>
> /* processor features (e.g. for CPUID insn) */
> /* Minimum level/xlevel/xlevel2, based on CPU model + features */
> diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
> index 0ec898eb1d..563600a30a 100644
> --- a/target/lm32/cpu.h
> +++ b/target/lm32/cpu.h
> @@ -159,8 +159,6 @@ struct CPULM32State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t eba; /* exception base address */
> uint32_t deba; /* debug exception base address */
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 096d1eb588..4e27ff677f 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -143,8 +143,6 @@ typedef struct CPUM68KState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t features;
> } CPUM68KState;
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 732653caed..6a470a2492 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -266,8 +266,6 @@ struct CPUMBState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* These fields are preserved on reset. */
>
> struct {
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 2d9c5f26eb..b9e58ed883 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1021,8 +1021,6 @@ struct CPUMIPSState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> CPUMIPSMVPContext *mvp;
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
> index f5ee8a02f4..a62cca1817 100644
> --- a/target/moxie/cpu.h
> +++ b/target/moxie/cpu.h
> @@ -45,9 +45,6 @@ typedef struct CPUMoxieState {
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> -
> - CPU_COMMON
> -
> } CPUMoxieState;
>
> #include "qom/cpu.h"
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index cd06a2ef41..75ea964632 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -166,8 +166,6 @@ struct CPUNios2State {
>
> uint32_t irq_pending;
> #endif
> -
> - CPU_COMMON
> };
>
> /**
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index e1acd48652..e3ffa618c9 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t cpucfgr; /* CPU configure register */
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bb57496212..bbc8eb0cfc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -999,8 +999,6 @@ struct CPUPPCState {
> /* when a memory exception occurs, the access type is stored here */
> int access_type;
>
> - CPU_COMMON
> -
> /* MMU context - only relevant for full system emulation */
> #if !defined(CONFIG_USER_ONLY)
> #if defined(TARGET_PPC64)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 30a01e8386..7086b336c6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -169,10 +169,6 @@ struct CPURISCVState {
>
> float_status fp_status;
>
> - /* QEMU */
> - CPU_COMMON
> -
> - /* Fields from here on are preserved across CPU reset. */
> QEMUTimer *timer; /* Internal timer */
> };
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index ebcf7863e4..17d54f9587 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -114,8 +114,6 @@ struct CPUS390XState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> #if !defined(CONFIG_USER_ONLY)
> uint32_t core_id; /* PoP "CPU address", same as cpu_index */
> uint64_t cpuid;
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index 944854dbe0..974d46aae1 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -179,8 +179,6 @@ typedef struct CPUSH4State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved over CPU reset. */
> int id; /* CPU model */
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index ae9ac07a9d..69e2199569 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -446,8 +446,6 @@ struct CPUSPARCState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> target_ulong version;
> uint32_t nwindows;
> diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
> index deb3e836ea..c2acb43c2b 100644
> --- a/target/tilegx/cpu.h
> +++ b/target/tilegx/cpu.h
> @@ -93,8 +93,6 @@ typedef struct CPUTLGState {
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> -
> - CPU_COMMON
> } CPUTLGState;
>
> #include "qom/cpu.h"
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index 43ef29b6bd..9fe501f98f 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -184,8 +184,6 @@ struct CPUTriCoreState {
> int error_code;
> uint32_t hflags; /* CPU State */
>
> - CPU_COMMON
> -
> /* Internal CPU feature flags. */
> uint64_t features;
>
> diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
> index 140c590ec1..1ae0d78f4f 100644
> --- a/target/unicore32/cpu.h
> +++ b/target/unicore32/cpu.h
> @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State {
> float_status fp_status;
> } ucf64;
>
> - CPU_COMMON
> -
> /* Internal CPU feature flags. */
> uint32_t features;
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 1bbb839bed..4e289dfa6e 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -511,8 +511,6 @@ typedef struct CPUXtensaState {
>
> /* Watchpoints for DBREAK registers */
> struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
> -
> - CPU_COMMON
> } CPUXtensaState;
>
> /**
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 37/39] tcg/aarch64: Use LDP to load tlb mask+table
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 37/39] tcg/aarch64: Use LDP to load tlb mask+table Richard Henderson
@ 2019-05-10 21:01 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-10 21:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:29 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This changes the code generation for the tlb from e.g.
>
> ldur x0, [x19, #0xffffffffffffffe0]
> ldur x1, [x19, #0xffffffffffffffe8]
> and x0, x0, x20, lsr #8
> add x1, x1, x0
> ldr x0, [x1]
> ldr x1, [x1, #0x18]
>
> to
>
> ldp x0, x1, [x19, #-0x20]
> and x0, x0, x20, lsr #8
> add x1, x1, x0
> ldr x0, [x1]
> ldr x1, [x1, #0x18]
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes.
> ---
> tcg/aarch64/tcg-target.inc.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
> index afac018301..2863a371a0 100644
> --- a/tcg/aarch64/tcg-target.inc.c
> +++ b/tcg/aarch64/tcg-target.inc.c
> @@ -1459,6 +1459,10 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
> QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512);
>
> +/* These offsets are built into the LDP below. */
> +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
> +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);
> +
> /* Load and compare a TLB entry, emitting the conditional jump to the
> slow path for the failure case, which will be patched later when finalizing
> the slow path. Generated code returns the host addend in X1,
> @@ -1467,23 +1471,20 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
> tcg_insn_unit **label_ptr, int mem_index,
> bool is_read)
> {
> - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index);
> - int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
> - int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
> unsigned a_bits = get_alignment_bits(opc);
> unsigned s_bits = opc & MO_SIZE;
> unsigned a_mask = (1u << a_bits) - 1;
> unsigned s_mask = (1u << s_bits) - 1;
> - TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0, x3;
> + TCGReg x3;
> TCGType mask_type;
> uint64_t compare_mask;
>
> mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32
> ? TCG_TYPE_I64 : TCG_TYPE_I32);
>
> - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
> - tcg_out_ld(s, mask_type, TCG_REG_X0, mask_base, mask_ofs);
> - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, table_base, table_ofs);
> + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */
> + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0,
> + TLB_MASK_TABLE_OFS(mem_index), 1, 0);
>
> /* Extract the TLB index from the address into X0. */
> tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64,
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 39/39] tcg/arm: Remove mostly unreachable tlb special case
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 39/39] tcg/arm: Remove mostly unreachable tlb special case Richard Henderson
@ 2019-05-10 21:04 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-10 21:04 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:34 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There was nothing armv7 specific about the bic+cmp sequence, however
> looking at the set of guests more closely shows that the 8-bit immediate
> operand for the bic can only be satisfied with one guest in tree:
> baseline m-profile -- 10-bit pages with aligned 4-byte memory ops.
> Therefore it does not seem useful to keep this path.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/arm/tcg-target.inc.c | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index ac813abfb8..e0fcc1d990 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -1290,19 +1290,20 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
> tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
> offsetof(CPUTLBEntry, addend));
>
> - /* Check alignment, check comparators. */
> - if (use_armv7_instructions) {
> + /*
> + * Check alignment, check comparators.
> + * Do this in no more than 3 insns. Use MOVW for v7, if possible,
> + * to reduce the number of sequential conditional instructions.
> + * Almost all guests have at least 4k pages, which means that we need
> + * to clear at least 9 bits even for an 8-byte memory, which means it
> + * isn't worth checking for an immediate operand for BIC.
> + */
> + if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
> tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
> - int rot = encode_imm(mask);
>
> - if (rot >= 0) {
> - tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo,
> - rotl(mask, rot) | (rot << 7));
> - } else {
> - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
> - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
> - addrlo, TCG_REG_TMP, 0);
> - }
> + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
> + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
> + addrlo, TCG_REG_TMP, 0);
> tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
> } else {
> if (a_bits) {
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD to load tlb mask+table
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD " Richard Henderson
@ 2019-05-10 21:08 ` Alistair Francis
2019-05-11 19:13 ` Richard Henderson
0 siblings, 1 reply; 81+ messages in thread
From: Alistair Francis @ 2019-05-10 21:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Tue, May 7, 2019 at 5:32 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This changes the code generation for the tlb from e.g.
>
> ldr ip, [r6, #-0x10]
> ldr r2, [r6, #-0xc]
> and ip, ip, r4, lsr #8
> ldrd r0, r1, [r2, ip]!
> ldr r2, [r2, #0x18]
>
> to
>
> ldrd r0, r1, [r6, #-0x10]
> and r0, r0, r4, lsr #8
> ldrd r2, r3, [r1, r0]!
> ldr r1, [r1, #0x18]
>
> for armv7 hosts. Rearranging the register allocation in
> order to avoid overlap between the two ldrd pairs causes
> the patch to be larger than it ordinarily would be.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v3: Add QEMU_BUILD_BUG_ON for mask/table ordering; comment fixes.
> ---
> tcg/arm/tcg-target.inc.c | 92 +++++++++++++++++++++++-----------------
> 1 file changed, 53 insertions(+), 39 deletions(-)
>
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index ad32b04e13..ac813abfb8 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -267,6 +267,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
> tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
> #endif
> break;
> @@ -1224,6 +1225,10 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
> QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
> QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
>
> +/* These offsets are built into the LDRD below. */
> +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
> +QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
> +
> /* Load and compare a TLB entry, leaving the flags set. Returns the register
> containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
>
> @@ -1238,47 +1243,54 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
> unsigned s_bits = opc & MO_SIZE;
> unsigned a_bits = get_alignment_bits(opc);
>
> - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
> - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP, TCG_AREG0, mask_off);
> - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R2, TCG_AREG0, table_off);
> -
> - /* Extract the tlb index from the address into TMP. */
> - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, addrlo,
> - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
> -
> /*
> - * Add the tlb_table pointer, creating the CPUTLBEntry address in R2.
> - * Load the tlb comparator into R0/R1 and the fast path addend into R2.
> + * We don't support inline unaligned acceses, but we can easily
> + * support overalignment checks.
> */
> - if (cmp_off == 0) {
> - if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
> - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_TMP);
> - } else {
> - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R2, TCG_REG_TMP);
> - }
> - } else {
> - tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
> - TCG_REG_R2, TCG_REG_R2, TCG_REG_TMP, 0);
> - if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
> - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off);
> - } else {
> - tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R2, cmp_off);
> - }
> - }
> - if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
> - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2, cmp_off + 4);
> - }
> -
> - /* Load the tlb addend. */
> - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2,
> - offsetof(CPUTLBEntry, addend));
> -
> - /* Check alignment. We don't support inline unaligned acceses,
> - but we can easily support overalignment checks. */
> if (a_bits < s_bits) {
> a_bits = s_bits;
> }
>
> + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
> + if (use_armv6_instructions) {
> + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
> + } else {
> + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_AREG0, mask_off);
> + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R1, TCG_AREG0, table_off);
> + }
> +
> + /* Extract the tlb index from the address into R0. */
> + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
> + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
> +
> + /*
> + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
> + * Load the tlb comparator into R2/R3 and the fast path addend into R1.
> + */
> + if (cmp_off == 0) {
> + if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
> + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
> + } else {
> + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
> + }
> + } else {
> + tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
> + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
> + if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
> + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
> + } else {
> + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
> + }
> + }
> + if (!use_armv6_instructions && TARGET_LONG_BITS == 64) {
> + tcg_out_ld32_12(s, COND_AL, TCG_REG_R3, TCG_REG_R1, cmp_off + 4);
> + }
> +
> + /* Load the tlb addend. */
> + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
> + offsetof(CPUTLBEntry, addend));
> +
> + /* Check alignment, check comparators. */
> if (use_armv7_instructions) {
> tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
> int rot = encode_imm(mask);
> @@ -1291,22 +1303,24 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
> tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
> addrlo, TCG_REG_TMP, 0);
> }
> - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, 0);
> + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
> } else {
> if (a_bits) {
> tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo,
> (1 << a_bits) - 1);
> }
> + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo,
> + SHIFT_IMM_LSR(TARGET_PAGE_BITS));
> tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP,
> - 0, TCG_REG_R0, TCG_REG_TMP,
> + 0, TCG_REG_R2, TCG_REG_TMP,
> SHIFT_IMM_LSL(TARGET_PAGE_BITS));
> }
>
> if (TARGET_LONG_BITS == 64) {
> - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0);
> + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
This is complex and I'm probably misunderstanding something but isn't
it possible for TCG_REG_R3 to not be set if use_armv6_instructions is
true and TARGET_LONG_BITS is 64?
Alistair
> }
>
> - return TCG_REG_R2;
> + return TCG_REG_R1;
> }
>
> /* Record the context of a call to the out of line helper code for the slow
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON Richard Henderson
2019-05-10 20:58 ` Alistair Francis
@ 2019-05-11 13:21 ` Aleksandar Markovic
1 sibling, 0 replies; 81+ messages in thread
From: Aleksandar Markovic @ 2019-05-11 13:21 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On May 8, 2019 2:32 AM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> This macro is now always empty, so remove it. This leaves the
> entire contents of CPUArchState under the control of the guest
> architecture.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu-defs.h | 2 --
> target/alpha/cpu.h | 3 ---
> target/arm/cpu.h | 4 +---
> target/cris/cpu.h | 2 --
> target/hppa/cpu.h | 3 ---
> target/i386/cpu.h | 4 +---
> target/lm32/cpu.h | 2 --
> target/m68k/cpu.h | 2 --
> target/microblaze/cpu.h | 2 --
> target/mips/cpu.h | 2 --
> target/moxie/cpu.h | 3 ---
> target/nios2/cpu.h | 2 --
> target/openrisc/cpu.h | 2 --
> target/ppc/cpu.h | 2 --
> target/riscv/cpu.h | 4 ----
> target/s390x/cpu.h | 2 --
> target/sh4/cpu.h | 2 --
> target/sparc/cpu.h | 2 --
> target/tilegx/cpu.h | 2 --
> target/tricore/cpu.h | 2 --
> target/unicore32/cpu.h | 2 --
> target/xtensa/cpu.h | 2 --
> 22 files changed, 2 insertions(+), 51 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 4cde7d611c..1f75a97701 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB;
>
> #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> -#define CPU_COMMON /* Nothing */
> -
> /*
> * This structure must be placed in ArchCPU immedately
> * before CPUArchState, as a field named "neg".
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index f4bb67c101..5bd90b7ce5 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -246,9 +246,6 @@ struct CPUAlphaState {
> /* This alarm doesn't exist in real hardware; we wish it did. */
> uint64_t alarm_expire;
>
> - /* Those resources are used only in QEMU core */
> - CPU_COMMON
> -
> int error_code;
>
> uint32_t features;
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 909cb4604d..135a16a351 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -643,9 +643,7 @@ typedef struct CPUARMState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> - /* Fields after CPU_COMMON are preserved across CPU reset. */
> + /* Fields after this point are preserved across CPU reset. */
>
> /* Internal CPU feature flags. */
> uint64_t features;
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index eeab483dba..6dc4502e9a 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -163,8 +163,6 @@ typedef struct CPUCRISState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Members from load_info on are preserved across resets. */
> void *load_info;
> } CPUCRISState;
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 0661ff60c1..3ed2ac3c25 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -197,9 +197,6 @@ struct CPUHPPAState {
> target_ureg cr_back[2]; /* back of cr17/cr18 */
> target_ureg shadow[7]; /* shadow registers */
>
> - /* Those resources are used only in QEMU core */
> - CPU_COMMON
> -
> /* ??? The number of entries isn't specified by the architecture. */
> /* ??? Implement a unified itlb/dtlb for the moment. */
> /* ??? We should use a more intelligent data structure. */
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 43bb6ab841..8069e5b19d 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1288,9 +1288,7 @@ typedef struct CPUX86State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> - /* Fields after CPU_COMMON are preserved across CPU reset. */
> + /* Fields after this point are preserved across CPU reset. */
>
> /* processor features (e.g. for CPUID insn) */
> /* Minimum level/xlevel/xlevel2, based on CPU model + features */
> diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
> index 0ec898eb1d..563600a30a 100644
> --- a/target/lm32/cpu.h
> +++ b/target/lm32/cpu.h
> @@ -159,8 +159,6 @@ struct CPULM32State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t eba; /* exception base address */
> uint32_t deba; /* debug exception base address */
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 096d1eb588..4e27ff677f 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -143,8 +143,6 @@ typedef struct CPUM68KState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t features;
> } CPUM68KState;
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 732653caed..6a470a2492 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -266,8 +266,6 @@ struct CPUMBState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* These fields are preserved on reset. */
>
> struct {
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 2d9c5f26eb..b9e58ed883 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1021,8 +1021,6 @@ struct CPUMIPSState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> CPUMIPSMVPContext *mvp;
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
> index f5ee8a02f4..a62cca1817 100644
> --- a/target/moxie/cpu.h
> +++ b/target/moxie/cpu.h
> @@ -45,9 +45,6 @@ typedef struct CPUMoxieState {
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> -
> - CPU_COMMON
> -
> } CPUMoxieState;
>
> #include "qom/cpu.h"
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index cd06a2ef41..75ea964632 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -166,8 +166,6 @@ struct CPUNios2State {
>
> uint32_t irq_pending;
> #endif
> -
> - CPU_COMMON
> };
>
> /**
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index e1acd48652..e3ffa618c9 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t cpucfgr; /* CPU configure register */
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bb57496212..bbc8eb0cfc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -999,8 +999,6 @@ struct CPUPPCState {
> /* when a memory exception occurs, the access type is stored here */
> int access_type;
>
> - CPU_COMMON
> -
> /* MMU context - only relevant for full system emulation */
> #if !defined(CONFIG_USER_ONLY)
> #if defined(TARGET_PPC64)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 30a01e8386..7086b336c6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -169,10 +169,6 @@ struct CPURISCVState {
>
> float_status fp_status;
>
> - /* QEMU */
> - CPU_COMMON
> -
> - /* Fields from here on are preserved across CPU reset. */
Why is this comment line deleted in this patch? If you want to delete this
line, you should do it in a separate patch, with a separate explanation, as
the comment has nothing to do with CPU_COMMON.
Thanks,
Aleksandar
> QEMUTimer *timer; /* Internal timer */
> };
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index ebcf7863e4..17d54f9587 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -114,8 +114,6 @@ struct CPUS390XState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> #if !defined(CONFIG_USER_ONLY)
> uint32_t core_id; /* PoP "CPU address", same as cpu_index */
> uint64_t cpuid;
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index 944854dbe0..974d46aae1 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -179,8 +179,6 @@ typedef struct CPUSH4State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved over CPU reset. */
> int id; /* CPU model */
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index ae9ac07a9d..69e2199569 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -446,8 +446,6 @@ struct CPUSPARCState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> target_ulong version;
> uint32_t nwindows;
> diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
> index deb3e836ea..c2acb43c2b 100644
> --- a/target/tilegx/cpu.h
> +++ b/target/tilegx/cpu.h
> @@ -93,8 +93,6 @@ typedef struct CPUTLGState {
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> -
> - CPU_COMMON
> } CPUTLGState;
>
> #include "qom/cpu.h"
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index 43ef29b6bd..9fe501f98f 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -184,8 +184,6 @@ struct CPUTriCoreState {
> int error_code;
> uint32_t hflags; /* CPU State */
>
> - CPU_COMMON
> -
> /* Internal CPU feature flags. */
> uint64_t features;
>
> diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
> index 140c590ec1..1ae0d78f4f 100644
> --- a/target/unicore32/cpu.h
> +++ b/target/unicore32/cpu.h
> @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State {
> float_status fp_status;
> } ucf64;
>
> - CPU_COMMON
> -
> /* Internal CPU feature flags. */
> uint32_t features;
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 1bbb839bed..4e289dfa6e 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -511,8 +511,6 @@ typedef struct CPUXtensaState {
>
> /* Watchpoints for DBREAK registers */
> struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
> -
> - CPU_COMMON
> } CPUXtensaState;
>
> /**
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 14:32 ` Richard Henderson
2019-05-08 21:53 ` Philippe Mathieu-Daudé
@ 2019-05-11 14:31 ` Aleksandar Markovic
2019-05-16 6:29 ` Aleksandar Markovic
2 siblings, 0 replies; 81+ messages in thread
From: Aleksandar Markovic @ 2019-05-11 14:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On May 8, 2019 4:33 PM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> On 5/8/19 1:15 AM, Aleksandar Markovic wrote:
> >
> > On May 8, 2019 2:19 AM, "Richard Henderson" <
richard.henderson@linaro.org
> > <mailto:richard.henderson@linaro.org>> wrote:
> >>
> >>
> >>
> >
> > This commit message doesnˊt explain the reason for the change, and why
is this
> > an improvement. The underlyng reason for distingishing between env_cpu
and
> > env_archcpu cases is not explained too.
>
> It's certainly explained in the preceeding patches that introduce those
functions.
>
A commit (code+message) should be as standalone as possible, and one should
not be forced to resort to reverse-engineering and perusing mailing list or
patchwork in order to reveal its true meaning in another commit message
altogether.
Thanks,
Aleksandar
> Are you suggesting that it is beneficial to copy-and-paste a common block
> explanation into 21 commit messages for each of target/foo/?
>
>
> r~
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD to load tlb mask+table
2019-05-10 21:08 ` Alistair Francis
@ 2019-05-11 19:13 ` Richard Henderson
2019-05-13 23:10 ` Alistair Francis
0 siblings, 1 reply; 81+ messages in thread
From: Richard Henderson @ 2019-05-11 19:13 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel@nongnu.org Developers
On 5/10/19 2:08 PM, Alistair Francis wrote:
>> + if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
>> + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
...
>
> This is complex and I'm probably misunderstanding something but isn't
> it possible for TCG_REG_R3 to not be set if use_armv6_instructions is
> true and TARGET_LONG_BITS is 64?
No, the LDRD instruction loads data into both R2 and R2+1 = R3.
r~
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD to load tlb mask+table
2019-05-11 19:13 ` Richard Henderson
@ 2019-05-13 23:10 ` Alistair Francis
0 siblings, 0 replies; 81+ messages in thread
From: Alistair Francis @ 2019-05-13 23:10 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers
On Sat, May 11, 2019 at 12:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 5/10/19 2:08 PM, Alistair Francis wrote:
> >> + if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
> >> + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
> ...
> >
> > This is complex and I'm probably misunderstanding something but isn't
> > it possible for TCG_REG_R3 to not be set if use_armv6_instructions is
> > true and TARGET_LONG_BITS is 64?
>
> No, the LDRD instruction loads data into both R2 and R2+1 = R3.
Ah ok. This looks fine to me then but I don't think I fully grasp it
enough to Ack it.
Alistair
>
>
> r~
^ permalink raw reply [flat|nested] 81+ messages in thread
* Re: [Qemu-devel] [PATCH v3 18/39] target/mips: Use env_cpu, env_archcpu
2019-05-08 14:32 ` Richard Henderson
2019-05-08 21:53 ` Philippe Mathieu-Daudé
2019-05-11 14:31 ` Aleksandar Markovic
@ 2019-05-16 6:29 ` Aleksandar Markovic
2 siblings, 0 replies; 81+ messages in thread
From: Aleksandar Markovic @ 2019-05-16 6:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On May 8, 2019 4:33 PM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> On 5/8/19 1:15 AM, Aleksandar Markovic wrote:
> >
> > On May 8, 2019 2:19 AM, "Richard Henderson" <
richard.henderson@linaro.org
> > <mailto:richard.henderson@linaro.org>> wrote:
> >>
> >>
> >>
> >
> > This commit message doesnˊt explain the reason for the change, and why
is this
> > an improvement. The underlyng reason for distingishing between env_cpu
and
> > env_archcpu cases is not explained too.
>
> It's certainly explained in the preceeding patches that introduce those
functions.
>
> Are you suggesting that it is beneficial to copy-and-paste a common block
> explanation into 21 commit messages for each of target/foo/?
My objection, as I am the maintainer for MIPS part, is about this very
commit.
If you can't put together a classical standalone commit message which will
be according to our guidelines for writing a good commit message, the
minimum I expect from you is the following commit message:
“Please refer to the commit message(s) for commit(s) <here you list the
titles of the commits that contain explanation for this commit> for
details.”
If I were you, I would do the same in all similar cases, but again, at this
moment I am talking about this commit only, and I am insisting on not
allowing empty commit messages for any code I maintain, without exceptions.
Regards,
Aleksandar
>
> r~
^ permalink raw reply [flat|nested] 81+ messages in thread
end of thread, other threads:[~2019-05-16 6:30 UTC | newest]
Thread overview: 81+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-08 0:06 [Qemu-devel] [PATCH v3 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc Richard Henderson
2019-05-09 17:48 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 02/39] tcg: Split out target/arch/cpu-param.h Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 03/39] tcg: Create struct CPUTLB Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 04/39] cpu: Define CPUArchState with typedef Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 05/39] cpu: Define ArchCPU Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 06/39] cpu: Replace ENV_GET_CPU with env_cpu Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 07/39] cpu: Introduce env_archcpu Richard Henderson
2019-05-09 17:52 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 08/39] target/alpha: Use env_cpu, env_archcpu Richard Henderson
2019-05-09 17:56 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 09/39] target/arm: " Richard Henderson
2019-05-09 17:57 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 10/39] target/cris: Reindent mmu.c Richard Henderson
2019-05-08 6:26 ` Philippe Mathieu-Daudé
2019-05-09 18:01 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 11/39] target/cris: Reindent op_helper.c Richard Henderson
2019-05-08 6:28 ` Philippe Mathieu-Daudé
2019-05-09 18:03 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 12/39] target/cris: Use env_cpu, env_archcpu Richard Henderson
2019-05-09 18:04 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 13/39] target/hppa: " Richard Henderson
2019-05-09 18:05 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 14/39] target/i386: " Richard Henderson
2019-05-09 18:07 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 15/39] target/lm32: " Richard Henderson
2019-05-09 18:08 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 16/39] target/m68k: " Richard Henderson
2019-05-09 18:16 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 17/39] target/microblaze: " Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 18/39] target/mips: " Richard Henderson
2019-05-08 8:15 ` Aleksandar Markovic
2019-05-08 14:32 ` Richard Henderson
2019-05-08 21:53 ` Philippe Mathieu-Daudé
2019-05-09 21:19 ` Aleksandar Markovic
2019-05-11 14:31 ` Aleksandar Markovic
2019-05-16 6:29 ` Aleksandar Markovic
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 19/39] target/moxie: " Richard Henderson
2019-05-09 18:19 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 20/39] target/nios2: " Richard Henderson
2019-05-09 18:20 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 21/39] target/openrisc: " Richard Henderson
2019-05-09 18:20 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 22/39] target/ppc: " Richard Henderson
2019-05-09 18:28 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 23/39] target/riscv: " Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 24/39] target/s390x: " Richard Henderson
2019-05-09 18:31 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 25/39] target/sh4: " Richard Henderson
2019-05-09 20:14 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 26/39] target/sparc: " Richard Henderson
2019-05-09 20:15 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 27/39] target/tilegx: Use env_cpu Richard Henderson
2019-05-09 20:16 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 28/39] target/tricore: " Richard Henderson
2019-05-09 20:16 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu Richard Henderson
2019-05-09 20:17 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 30/39] target/xtensa: " Richard Henderson
2019-05-09 20:19 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h Richard Henderson
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 32/39] cpu: Introduce cpu_set_cpustate_pointers Richard Henderson
2019-05-09 20:32 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 33/39] cpu: Introduce CPUNegativeOffsetState Richard Henderson
2019-05-09 20:36 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 34/39] cpu: Move icount_decr to CPUNegativeOffsetState Richard Henderson
2019-05-09 20:26 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 35/39] cpu: Move the softmmu tlb " Richard Henderson
2019-05-10 20:57 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 36/39] cpu: Remove CPU_COMMON Richard Henderson
2019-05-10 20:58 ` Alistair Francis
2019-05-11 13:21 ` Aleksandar Markovic
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 37/39] tcg/aarch64: Use LDP to load tlb mask+table Richard Henderson
2019-05-10 21:01 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD " Richard Henderson
2019-05-10 21:08 ` Alistair Francis
2019-05-11 19:13 ` Richard Henderson
2019-05-13 23:10 ` Alistair Francis
2019-05-08 0:06 ` [Qemu-devel] [PATCH v3 39/39] tcg/arm: Remove mostly unreachable tlb special case Richard Henderson
2019-05-10 21:04 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.