From: Jerin Jacob <jerinjacobk@gmail.com>
To: Pavan Nikhilesh <pbhagavatula@marvell.com>
Cc: Jerin Jacob <jerinj@marvell.com>,
Nithin Dabilpuram <ndabilpuram@marvell.com>,
Vamsi Attunuru <vattunuru@marvell.com>, dpdk-dev <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] mempool/octeontx2: optimize for L1D cache architecture
Date: Fri, 31 Jan 2020 21:25:36 +0530 [thread overview]
Message-ID: <CALBAE1MCqUpT6dV2Uug5WKSGPoX2TgV1GHi926iRGZ=8tNj3zA@mail.gmail.com> (raw)
In-Reply-To: <20200131125059.1556-1-pbhagavatula@marvell.com>
On Fri, Jan 31, 2020 at 6:21 PM <pbhagavatula@marvell.com> wrote:
>
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>
> OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate
> the set selection.
> Add additional padding to ensure that the element size always
> occupies odd number of cachelines to ensure even distribution
> of elements among L1D cache sets.
>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
> drivers/mempool/octeontx2/otx2_mempool_ops.c | 41 ++++++++++++++++++++
> 1 file changed, 41 insertions(+)
Please fix the 32-bit build issues(i.e use PRIx64)
/export/dpdk.org/drivers/mempool/octeontx2/otx2_mempool_ops.c:782:41:
note: format string is defined here
782 | otx2_npa_dbg("iova %lx, aligned iova %lx", iova - off, iova);
| ~~^
| |
| long unsigned int
| %llx
next prev parent reply other threads:[~2020-01-31 15:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-31 12:50 [dpdk-dev] [PATCH] mempool/octeontx2: optimize for L1D cache architecture pbhagavatula
2020-01-31 15:55 ` Jerin Jacob [this message]
2020-01-31 17:23 ` [dpdk-dev] [PATCH v2] " pbhagavatula
2020-02-01 11:51 ` Jerin Jacob
2020-02-16 20:33 ` Thomas Monjalon
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