From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD4AAC433EF for ; Tue, 21 Sep 2021 06:43:51 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 189D260200 for ; Tue, 21 Sep 2021 06:43:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 189D260200 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0AD3C40DF7; Tue, 21 Sep 2021 08:43:50 +0200 (CEST) Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) by mails.dpdk.org (Postfix) with ESMTP id 1F77C40683 for ; Tue, 21 Sep 2021 08:43:48 +0200 (CEST) Received: by mail-io1-f52.google.com with SMTP id z6so18792507iof.5 for ; Mon, 20 Sep 2021 23:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=2C0qXzDRViLg1+IdWZpiUMlcfAD7SMSgfacJmgb06hk=; b=EJJ/qBv+QzHhm3EdMIWIjZ+0qfszY+6hw2Vxq0T7CnbpLL8vS7IbhhR2TlFzxsCMej NPF3ssElcySHTegtSradFGcfNYL0fC+DaiyGSBnIOetbs7VJpQ+hP+S716hYRzvHtg97 RlryZfFVoUbTx9oXeDbtipMpOxOFTu2LnhZvlRQn0DaAn2ByyafSdekbO7OpfRv9JUKY Es2p2SB1abksA0K4a459N0Gqt6io5SXJH5goHBt5GKZPR9MKMLF9fN/D2xV0SqYed5Dv AxjuWjez4IOYX8Y9Pk44GeWiaXFqc/Sj+pnT9SXFm3D5ZVlZN1WHlaiVjsi0PrhXU+ER 2yMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=2C0qXzDRViLg1+IdWZpiUMlcfAD7SMSgfacJmgb06hk=; b=oWS5xp2ywfYjhvdDnKDbmYF1f263y2IF7gQ3IteUaKb5iv4nH+O6nLao6qh5bWaegF vPT31R5rgRZSR+tJKoymU6VGqft2cm0wFpM2WzqHba8y32ENR4axG+wyVcjwF80bWoOs XJFaGevVBHvUBtEsObpDplzzV99FvTiwhH/kvOXYM81ywMM1BSViQyOB5T0OM8VW1Qqo rnz0KMc9wJRu7ie3wZzIUMFAE6L60Rnc6yGnqOz2VLyx4pTs+3j0RML3nFNjXHov9LSh XTZb1rMPl8ntHkHUdZbBn3dIlMLwrmjtt7OmmnPCvZBrPKNqOsmW/gsuQm2PktwfEtoZ u9fA== X-Gm-Message-State: AOAM531hDwwdVGNXvusevAs2TjriQperqNzy5dYk7oTDgj6HA8U2I6H+ mfATdduSNhQICC/Qh/RNKFM2YHvTWD5Kz9ZAb5axHhnM+vo05A== X-Google-Smtp-Source: ABdhPJwAVslIgtQMt120HBL2RCUDxLSnGc9yQgPrSAy2pOr9XYUgDuT+qb8oxVB2XXSn/4N0L2DCEPIYPwplEjpIRmA= X-Received: by 2002:a05:6638:94c:: with SMTP id f12mr14130490jad.126.1632206627305; Mon, 20 Sep 2021 23:43:47 -0700 (PDT) MIME-Version: 1.0 References: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-1-git-send-email-skoteshwar@marvell.com> <1631975519-30924-8-git-send-email-skoteshwar@marvell.com> In-Reply-To: <1631975519-30924-8-git-send-email-skoteshwar@marvell.com> From: Jerin Jacob Date: Tue, 21 Sep 2021 12:13:21 +0530 Message-ID: To: Satha Koteswara Rao Kottidi Cc: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , dpdk-dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v2 7/8] net/cnxk: tm capabilities and queue rate limit handlers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Sat, Sep 18, 2021 at 8:03 PM wrote: > > From: Satha Rao > > Initial version of TM implementation added basic infrastructure, > tm node_get, capabilities operations and rate limit queue operation. > > Signed-off-by: Satha Rao tm-> TM in subject. # Could you rebase on top dpdk-next-net-mrvl.git it has following[1] build issue to "common/cnxk: update ROC models" commit # Please add Nithin's Acked-by in the next version. [1] FAILED: drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_nix_irq.c.o ccache gcc -Idrivers/libtmp_rte_common_cnxk.a.p -Idrivers -I../drivers -Idrivers/common/cnxk -I../drivers/common/cnxk -Idrivers/bus/pci -I../drivers/bus/pci -Ilib/net -I../lib/net -Ilib/ethdev -I../lib/ethdev -Ilib/meter -I../lib/meter -I. -I.. -Iconfig -I../config -Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include -I../lib/eal/linux/include -Ilib/eal/x86/include -I../lib/eal/x86/include -Ilib/eal/common -I../lib/eal/common -Ilib/eal -I../lib/eal -Ilib/kvargs -I.. /lib/kvargs -Ilib/metrics -I../lib/metrics -Ilib/telemetry -I../lib/telemetry -Ilib/pci -I../lib/pci -I../drivers/bus/pci/linux -Ilib/mbuf -I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/ring -I../lib/ring -Ilib/security -I../lib/securit y -Ilib/cryptodev -I../lib/cryptodev -Ilib/rcu -I../lib/rcu -fdiagnostics-color=3Dalways -D_FILE_OFFSET_BITS=3D64 -Wall -Winvalid-pch -Werror -O2 -g -include rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat -Wformat-nonliteral -Wformat-se curity -Wmissing-declarations -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef -Wwrite-strings -Wno-address-of-packed-member -Wno-packed-not-aligned -Wno-missing-field-i nitializers -Wno-zero-length-bounds -D_GNU_SOURCE -fPIC -march=3Dnative -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API -Wno-format-truncation -DRTE_LOG_DEFAULT_LOGTYPE=3Dpmd.common.cnxk -MD -MQ drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_ nix_irq.c.o -MF drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_nix_irq.c.o.d -o drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_nix_irq.c.o -c ../drivers/common/cnxk/roc_nix_irq.c In file included from ../drivers/common/cnxk/roc_api.h:86, from ../drivers/common/cnxk/roc_nix_irq.c:5: ../drivers/common/cnxk/roc_model.h:120:1: error: redefinition of =E2=80=98roc_model_is_cn96_cx=E2=80=99 120 | roc_model_is_cn96_cx(void) | ^~~~~~~~~~~~~~~~~~~~ ../drivers/common/cnxk/roc_model.h:114:1: note: previous definition of =E2=80=98roc_model_is_cn96_cx=E2=80=99 with type =E2=80=98uint64_t(void)=E2= =80=99 {aka =E2=80=98long unsigned int(void)=E2=80=99} 114 | roc_model_is_cn96_cx(void) | ^~~~~~~~~~~~~~~~~~~~ > --- > drivers/net/cnxk/cnxk_ethdev.c | 2 + > drivers/net/cnxk/cnxk_ethdev.h | 3 + > drivers/net/cnxk/cnxk_tm.c | 322 +++++++++++++++++++++++++++++++++++= ++++++ > drivers/net/cnxk/cnxk_tm.h | 18 +++ > drivers/net/cnxk/meson.build | 1 + > 5 files changed, 346 insertions(+) > create mode 100644 drivers/net/cnxk/cnxk_tm.c > create mode 100644 drivers/net/cnxk/cnxk_tm.h > > diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethde= v.c > index 7152dcd..8629193 100644 > --- a/drivers/net/cnxk/cnxk_ethdev.c > +++ b/drivers/net/cnxk/cnxk_ethdev.c > @@ -1276,6 +1276,8 @@ struct eth_dev_ops cnxk_eth_dev_ops =3D { > .rss_hash_update =3D cnxk_nix_rss_hash_update, > .rss_hash_conf_get =3D cnxk_nix_rss_hash_conf_get, > .set_mc_addr_list =3D cnxk_nix_mc_addr_list_configure, > + .set_queue_rate_limit =3D cnxk_nix_tm_set_queue_rate_limit, > + .tm_ops_get =3D cnxk_nix_tm_ops_get, > }; > > static int > diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethde= v.h > index 27920c8..10e05e6 100644 > --- a/drivers/net/cnxk/cnxk_ethdev.h > +++ b/drivers/net/cnxk/cnxk_ethdev.h > @@ -330,6 +330,9 @@ int cnxk_nix_timesync_write_time(struct rte_eth_dev *= eth_dev, > int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock); > > uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); > +int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops); > +int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev, > + uint16_t queue_idx, uint16_t tx_rate= ); > > /* RSS */ > uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethde= v_rss, > diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c > new file mode 100644 > index 0000000..87fd8be > --- /dev/null > +++ b/drivers/net/cnxk/cnxk_tm.c > @@ -0,0 +1,322 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(C) 2021 Marvell. > + */ > +#include > +#include > +#include > + > +static int > +cnxk_nix_tm_node_type_get(struct rte_eth_dev *eth_dev, uint32_t node_id, > + int *is_leaf, struct rte_tm_error *error) > +{ > + struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > + struct roc_nix *nix =3D &dev->nix; > + struct roc_nix_tm_node *node; > + > + if (is_leaf =3D=3D NULL) { > + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; > + return -EINVAL; > + } > + > + node =3D roc_nix_tm_node_get(nix, node_id); > + if (node_id =3D=3D RTE_TM_NODE_ID_NULL || !node) { > + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; > + return -EINVAL; > + } > + > + if (roc_nix_tm_lvl_is_leaf(nix, node->lvl)) > + *is_leaf =3D true; > + else > + *is_leaf =3D false; > + > + return 0; > +} > + > +static int > +cnxk_nix_tm_capa_get(struct rte_eth_dev *eth_dev, > + struct rte_tm_capabilities *cap, > + struct rte_tm_error *error) > +{ > + struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > + int rc, max_nr_nodes =3D 0, i, n_lvl; > + struct roc_nix *nix =3D &dev->nix; > + uint16_t schq[ROC_TM_LVL_MAX]; > + > + memset(cap, 0, sizeof(*cap)); > + > + rc =3D roc_nix_tm_rsrc_count(nix, schq); > + if (rc) { > + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; > + error->message =3D "unexpected fatal error"; > + return rc; > + } > + > + for (i =3D 0; i < NIX_TXSCH_LVL_TL1; i++) > + max_nr_nodes +=3D schq[i]; > + > + cap->n_nodes_max =3D max_nr_nodes + dev->nb_txq; > + > + n_lvl =3D roc_nix_tm_lvl_cnt_get(nix); > + /* Consider leaf level */ > + cap->n_levels_max =3D n_lvl + 1; > + cap->non_leaf_nodes_identical =3D 1; > + cap->leaf_nodes_identical =3D 1; > + > + /* Shaper Capabilities */ > + cap->shaper_private_n_max =3D max_nr_nodes; > + cap->shaper_n_max =3D max_nr_nodes; > + cap->shaper_private_dual_rate_n_max =3D max_nr_nodes; > + cap->shaper_private_rate_min =3D NIX_TM_MIN_SHAPER_RATE / 8; > + cap->shaper_private_rate_max =3D NIX_TM_MAX_SHAPER_RATE / 8; > + cap->shaper_private_packet_mode_supported =3D 1; > + cap->shaper_private_byte_mode_supported =3D 1; > + cap->shaper_pkt_length_adjust_min =3D NIX_TM_LENGTH_ADJUST_MIN; > + cap->shaper_pkt_length_adjust_max =3D NIX_TM_LENGTH_ADJUST_MAX; > + > + /* Schedule Capabilities */ > + cap->sched_n_children_max =3D schq[n_lvl - 1]; > + cap->sched_sp_n_priorities_max =3D NIX_TM_TLX_SP_PRIO_MAX; > + cap->sched_wfq_n_children_per_group_max =3D cap->sched_n_children= _max; > + cap->sched_wfq_n_groups_max =3D 1; > + cap->sched_wfq_weight_max =3D roc_nix_tm_max_sched_wt_get(); > + cap->sched_wfq_packet_mode_supported =3D 1; > + cap->sched_wfq_byte_mode_supported =3D 1; > + > + cap->dynamic_update_mask =3D RTE_TM_UPDATE_NODE_PARENT_KEEP_LEVEL= | > + RTE_TM_UPDATE_NODE_SUSPEND_RESUME; > + cap->stats_mask =3D RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES | > + RTE_TM_STATS_N_PKTS_RED_DROPPED | > + RTE_TM_STATS_N_BYTES_RED_DROPPED; > + > + for (i =3D 0; i < RTE_COLORS; i++) { > + cap->mark_vlan_dei_supported[i] =3D false; > + cap->mark_ip_ecn_tcp_supported[i] =3D false; > + cap->mark_ip_dscp_supported[i] =3D false; > + } > + > + return 0; > +} > + > +static int > +cnxk_nix_tm_level_capa_get(struct rte_eth_dev *eth_dev, uint32_t lvl, > + struct rte_tm_level_capabilities *cap, > + struct rte_tm_error *error) > +{ > + struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > + struct roc_nix *nix =3D &dev->nix; > + uint16_t schq[ROC_TM_LVL_MAX]; > + int rc, n_lvl; > + > + memset(cap, 0, sizeof(*cap)); > + > + rc =3D roc_nix_tm_rsrc_count(nix, schq); > + if (rc) { > + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; > + error->message =3D "unexpected fatal error"; > + return rc; > + } > + > + n_lvl =3D roc_nix_tm_lvl_cnt_get(nix); > + > + if (roc_nix_tm_lvl_is_leaf(nix, lvl)) { > + /* Leaf */ > + cap->n_nodes_max =3D dev->nb_txq; > + cap->n_nodes_leaf_max =3D dev->nb_txq; > + cap->leaf_nodes_identical =3D 1; > + cap->leaf.stats_mask =3D > + RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES; > + > + } else if (lvl =3D=3D ROC_TM_LVL_ROOT) { > + /* Root node, a.k.a. TL2(vf)/TL1(pf) */ > + cap->n_nodes_max =3D 1; > + cap->n_nodes_nonleaf_max =3D 1; > + cap->non_leaf_nodes_identical =3D 1; > + > + cap->nonleaf.shaper_private_supported =3D true; > + cap->nonleaf.shaper_private_dual_rate_supported =3D > + roc_nix_tm_lvl_have_link_access(nix, lvl) ? false= : > + true; > + cap->nonleaf.shaper_private_rate_min =3D > + NIX_TM_MIN_SHAPER_RATE / 8; > + cap->nonleaf.shaper_private_rate_max =3D > + NIX_TM_MAX_SHAPER_RATE / 8; > + cap->nonleaf.shaper_private_packet_mode_supported =3D 1; > + cap->nonleaf.shaper_private_byte_mode_supported =3D 1; > + > + cap->nonleaf.sched_n_children_max =3D schq[lvl]; > + cap->nonleaf.sched_sp_n_priorities_max =3D > + roc_nix_tm_max_prio(nix, lvl) + 1; > + cap->nonleaf.sched_wfq_n_groups_max =3D 1; > + cap->nonleaf.sched_wfq_weight_max =3D > + roc_nix_tm_max_sched_wt_get(); > + cap->nonleaf.sched_wfq_packet_mode_supported =3D 1; > + cap->nonleaf.sched_wfq_byte_mode_supported =3D 1; > + > + if (roc_nix_tm_lvl_have_link_access(nix, lvl)) > + cap->nonleaf.stats_mask =3D > + RTE_TM_STATS_N_PKTS_RED_DROPPED | > + RTE_TM_STATS_N_BYTES_RED_DROPPED; > + } else if (lvl < ROC_TM_LVL_MAX) { > + /* TL2, TL3, TL4, MDQ */ > + cap->n_nodes_max =3D schq[lvl]; > + cap->n_nodes_nonleaf_max =3D cap->n_nodes_max; > + cap->non_leaf_nodes_identical =3D 1; > + > + cap->nonleaf.shaper_private_supported =3D true; > + cap->nonleaf.shaper_private_dual_rate_supported =3D true; > + cap->nonleaf.shaper_private_rate_min =3D > + NIX_TM_MIN_SHAPER_RATE / 8; > + cap->nonleaf.shaper_private_rate_max =3D > + NIX_TM_MAX_SHAPER_RATE / 8; > + cap->nonleaf.shaper_private_packet_mode_supported =3D 1; > + cap->nonleaf.shaper_private_byte_mode_supported =3D 1; > + > + /* MDQ doesn't support Strict Priority */ > + if ((int)lvl =3D=3D (n_lvl - 1)) > + cap->nonleaf.sched_n_children_max =3D dev->nb_txq= ; > + else > + cap->nonleaf.sched_n_children_max =3D schq[lvl - = 1]; > + cap->nonleaf.sched_sp_n_priorities_max =3D > + roc_nix_tm_max_prio(nix, lvl) + 1; > + cap->nonleaf.sched_wfq_n_groups_max =3D 1; > + cap->nonleaf.sched_wfq_weight_max =3D > + roc_nix_tm_max_sched_wt_get(); > + cap->nonleaf.sched_wfq_packet_mode_supported =3D 1; > + cap->nonleaf.sched_wfq_byte_mode_supported =3D 1; > + } else { > + /* unsupported level */ > + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; > + return rc; > + } > + return 0; > +} > + > +static int > +cnxk_nix_tm_node_capa_get(struct rte_eth_dev *eth_dev, uint32_t node_id, > + struct rte_tm_node_capabilities *cap, > + struct rte_tm_error *error) > +{ > + struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > + struct cnxk_nix_tm_node *tm_node; > + struct roc_nix *nix =3D &dev->nix; > + uint16_t schq[ROC_TM_LVL_MAX]; > + int rc, n_lvl, lvl; > + > + memset(cap, 0, sizeof(*cap)); > + > + tm_node =3D (struct cnxk_nix_tm_node *)roc_nix_tm_node_get(nix, n= ode_id); > + if (!tm_node) { > + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; > + error->message =3D "no such node"; > + return -EINVAL; > + } > + > + lvl =3D tm_node->nix_node.lvl; > + n_lvl =3D roc_nix_tm_lvl_cnt_get(nix); > + > + /* Leaf node */ > + if (roc_nix_tm_lvl_is_leaf(nix, lvl)) { > + cap->stats_mask =3D RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_= BYTES; > + return 0; > + } > + > + rc =3D roc_nix_tm_rsrc_count(nix, schq); > + if (rc) { > + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; > + error->message =3D "unexpected fatal error"; > + return rc; > + } > + > + /* Non Leaf Shaper */ > + cap->shaper_private_supported =3D true; > + cap->shaper_private_rate_min =3D NIX_TM_MIN_SHAPER_RATE / 8; > + cap->shaper_private_rate_max =3D NIX_TM_MAX_SHAPER_RATE / 8; > + cap->shaper_private_packet_mode_supported =3D 1; > + cap->shaper_private_byte_mode_supported =3D 1; > + > + /* Non Leaf Scheduler */ > + if (lvl =3D=3D (n_lvl - 1)) > + cap->nonleaf.sched_n_children_max =3D dev->nb_txq; > + else > + cap->nonleaf.sched_n_children_max =3D schq[lvl - 1]; > + > + cap->nonleaf.sched_sp_n_priorities_max =3D > + roc_nix_tm_max_prio(nix, lvl) + 1; > + cap->nonleaf.sched_wfq_n_children_per_group_max =3D > + cap->nonleaf.sched_n_children_max; > + cap->nonleaf.sched_wfq_n_groups_max =3D 1; > + cap->nonleaf.sched_wfq_weight_max =3D roc_nix_tm_max_sched_wt_get= (); > + cap->nonleaf.sched_wfq_packet_mode_supported =3D 1; > + cap->nonleaf.sched_wfq_byte_mode_supported =3D 1; > + > + cap->shaper_private_dual_rate_supported =3D true; > + if (roc_nix_tm_lvl_have_link_access(nix, lvl)) { > + cap->shaper_private_dual_rate_supported =3D false; > + cap->stats_mask =3D RTE_TM_STATS_N_PKTS_RED_DROPPED | > + RTE_TM_STATS_N_BYTES_RED_DROPPED; > + } > + > + return 0; > +} > + > +const struct rte_tm_ops cnxk_tm_ops =3D { > + .node_type_get =3D cnxk_nix_tm_node_type_get, > + .capabilities_get =3D cnxk_nix_tm_capa_get, > + .level_capabilities_get =3D cnxk_nix_tm_level_capa_get, > + .node_capabilities_get =3D cnxk_nix_tm_node_capa_get, > +}; > + > +int > +cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev __rte_unused, void *arg) > +{ > + if (!arg) > + return -EINVAL; > + > + /* Check for supported revisions */ > + if (roc_model_is_cn96_ax() || roc_model_is_cn95_a0()) > + return -EINVAL; > + > + *(const void **)arg =3D &cnxk_tm_ops; > + > + return 0; > +} > + > +int > +cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev, > + uint16_t queue_idx, uint16_t tx_rate_mbp= s) > +{ > + struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > + uint64_t tx_rate =3D tx_rate_mbps * (uint64_t)1E6; > + struct roc_nix *nix =3D &dev->nix; > + int rc =3D -EINVAL; > + > + /* Check for supported revisions */ > + if (roc_model_is_cn96_ax() || roc_model_is_cn95_a0()) > + goto exit; > + > + if (queue_idx >=3D eth_dev->data->nb_tx_queues) > + goto exit; > + > + if ((roc_nix_tm_tree_type_get(nix) !=3D ROC_NIX_TM_RLIMIT) && > + eth_dev->data->nb_tx_queues > 1) { > + /* > + * Disable xmit will be enabled when > + * new topology is available. > + */ > + rc =3D roc_nix_tm_hierarchy_disable(nix); > + if (rc) > + goto exit; > + > + rc =3D roc_nix_tm_prepare_rate_limited_tree(nix); > + if (rc) > + goto exit; > + > + rc =3D roc_nix_tm_hierarchy_enable(nix, ROC_NIX_TM_RLIMIT= , true); > + if (rc) > + goto exit; > + } > + > + return roc_nix_tm_rlimit_sq(nix, queue_idx, tx_rate); > +exit: > + return rc; > +} > diff --git a/drivers/net/cnxk/cnxk_tm.h b/drivers/net/cnxk/cnxk_tm.h > new file mode 100644 > index 0000000..f7470c2 > --- /dev/null > +++ b/drivers/net/cnxk/cnxk_tm.h > @@ -0,0 +1,18 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(C) 2021 Marvell. > + */ > +#ifndef __CNXK_TM_H__ > +#define __CNXK_TM_H__ > + > +#include > + > +#include > + > +#include "roc_api.h" > + > +struct cnxk_nix_tm_node { > + struct roc_nix_tm_node nix_node; > + struct rte_tm_node_params params; > +}; > + > +#endif /* __CNXK_TM_H__ */ > diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build > index d4cdd17..1e86144 100644 > --- a/drivers/net/cnxk/meson.build > +++ b/drivers/net/cnxk/meson.build > @@ -17,6 +17,7 @@ sources =3D files( > 'cnxk_ptp.c', > 'cnxk_rte_flow.c', > 'cnxk_stats.c', > + 'cnxk_tm.c', > ) > > # CN9K > -- > 1.8.3.1 >