From: Andy Lutomirski <luto@kernel.org>
To: Dave Hansen <dave.hansen@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>,
"Andersen, John" <john.s.andersen@intel.com>,
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Subject: Re: [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning
Date: Thu, 9 Jul 2020 09:27:43 -0700 [thread overview]
Message-ID: <CALCETrUHcpqjDfAM9SbrZUM7xcS2wkVm=r1Nb1JmxV7A-KAeUQ@mail.gmail.com> (raw)
In-Reply-To: <6040c3b3-cac9-cc0e-f0de-baaa274920a2@intel.com>
On Thu, Jul 9, 2020 at 9:22 AM Dave Hansen <dave.hansen@intel.com> wrote:
>
> On 7/9/20 9:07 AM, Andy Lutomirski wrote:
> > On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen <dave.hansen@intel.com> wrote:
> >> On 7/9/20 8:44 AM, Andersen, John wrote:
> >>> Bits which are allowed to be pinned default to WP for CR0 and SMEP,
> >>> SMAP, and UMIP for CR4.
> >> I think it also makes sense to have FSGSBASE in this set.
> >>
> >> I know it hasn't been tested, but I think we should do the legwork to
> >> test it. If not in this set, can we agree that it's a logical next step?
> > I have no objection to pinning FSGSBASE, but is there a clear
> > description of the threat model that this whole series is meant to
> > address? The idea is to provide a degree of protection against an
> > attacker who is able to convince a guest kernel to write something
> > inappropriate to CR4, right? How realistic is this?
>
> If a quick search can find this:
>
> > https://googleprojectzero.blogspot.com/2017/05/exploiting-linux-kernel-via-packet.html
>
> I'd pretty confident that the guys doing actual bad things have it in
> their toolbox too.
>
True, but we have the existing software CR4 pinning. I suppose the
virtualization version is stronger.
--Andy
next prev parent reply other threads:[~2020-07-09 16:28 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 19:07 [PATCH 0/4] Paravirtualized Control Register pinning John Andersen
2020-06-17 19:07 ` [PATCH 1/4] X86: Update mmu_cr4_features during feature identification John Andersen
2020-06-18 14:09 ` Dave Hansen
2020-06-17 19:07 ` [PATCH 2/4] KVM: x86: Introduce paravirt feature CR0/CR4 pinning John Andersen
2020-06-18 14:18 ` Dave Hansen
2020-06-18 14:43 ` Andersen, John
2020-06-18 14:51 ` Dave Hansen
2020-07-07 21:12 ` Sean Christopherson
2020-07-07 21:48 ` Dave Hansen
2020-07-07 21:51 ` Paolo Bonzini
2020-07-09 15:44 ` Andersen, John
2020-07-09 15:56 ` Dave Hansen
2020-07-09 16:07 ` Andy Lutomirski
2020-07-09 16:22 ` Dave Hansen
2020-07-09 16:22 ` Dave Hansen
2020-07-09 16:27 ` Andy Lutomirski [this message]
2020-07-14 5:36 ` Andersen, John, Arvind Sankar
2020-07-14 5:36 ` Andersen, John, Arvind Sankar
2020-07-14 5:39 ` Andersen, John
2020-07-14 5:39 ` Andersen, John
2020-07-15 4:41 ` Sean Christopherson
2020-07-15 4:41 ` Sean Christopherson
2020-07-15 19:58 ` Andersen, John
2020-07-15 19:58 ` Andersen, John
2020-07-09 23:37 ` Kees Cook
2020-07-09 23:37 ` Kees Cook
2020-06-17 19:07 ` [PATCH 3/4] selftests: kvm: add test for CR pinning with SMM John Andersen
2020-06-17 19:07 ` [PATCH 4/4] X86: Use KVM CR pin MSRs John Andersen
2020-06-18 14:41 ` Dave Hansen
2020-06-18 15:26 ` Andersen, John
2020-06-18 15:38 ` Dave Hansen
2020-06-18 15:49 ` Andersen, John
2020-06-20 5:13 ` Andy Lutomirski
2020-06-20 5:13 ` Andy Lutomirski
2020-06-23 20:03 ` Andersen, John
2020-06-23 20:03 ` Andersen, John
2020-07-03 21:48 ` Andersen, John
2020-07-03 21:48 ` Andersen, John
2020-07-04 15:11 ` Arvind Sankar
2020-07-04 15:11 ` Arvind Sankar
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