From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752830AbbBXBAG (ORCPT ); Mon, 23 Feb 2015 20:00:06 -0500 Received: from mail-lb0-f174.google.com ([209.85.217.174]:36453 "EHLO mail-lb0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751712AbbBXBAF (ORCPT ); Mon, 23 Feb 2015 20:00:05 -0500 MIME-Version: 1.0 In-Reply-To: References: <20150221093150.GA27841@gmail.com> <20150221163840.GA32073@pd.tnic> <20150221172914.GB32073@pd.tnic> <54EB99E8.2060500@redhat.com> From: Andy Lutomirski Date: Mon, 23 Feb 2015 16:59:41 -0800 Message-ID: Subject: Re: [RFC PATCH] x86, fpu: Use eagerfpu by default on all CPUs To: "Maciej W. Rozycki" Cc: Linus Torvalds , Rik van Riel , Borislav Petkov , Ingo Molnar , Oleg Nesterov , X86 ML , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 23, 2015 at 4:56 PM, Maciej W. Rozycki wrote: > On Mon, 23 Feb 2015, Linus Torvalds wrote: > >> We have one traditional special case, which actually did something >> like Maciej's nightmare scenario: the completely broken "FPU errors >> over irq13" IBM PC/AT FPU linkage. >> >> But since we don't actually support old i386 machines any more, we >> don't really need to care. The only way you can get into that >> situation is with an external i387. I don't think we need to worry >> about it. >> >> But with the old horrid irq13 error handling, you literally could get >> into a situation that you got an error "exception" (irq) from the >> previous state, *after* you had already switched to the new one. We >> had some code to mitigate the problem, but as mentioned, I don't think >> it's an issue any more. > > Correct, the horrid hack is gone, it was so horrible (though I understand > why IBM had to do it with their PC/AT) that back in mid 1990s, some 10 > years after the inception of the problem, Intel felt so compelled to make > people get the handling of it right as to release a dedicated application > note: "AP-578 Software and Hardware Considerations for FPU Exception > Handlers for Intel Architecture Processors", Order Number 243291-002. > > Anyway, my point through this consideration has been about the > performance benefit from continuing the execution of an x87 instruction in > parallel, perhaps until after a context has been fully switched. Which > benefit is lost if a FSAVE/FXSAVE executed eagerly at the context switch > stalls waiting for the instruction to complete instead. And the save is indeed executed eagerly. Conceivably we could get rid of that on UP, but that seems to be a lot of complexity for extremely little gain. --Andy