From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF643C67790 for ; Fri, 27 Jul 2018 21:06:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6314720877 for ; Fri, 27 Jul 2018 21:06:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="xvQd5U8t" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6314720877 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389715AbeG0W3o (ORCPT ); Fri, 27 Jul 2018 18:29:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:60420 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389211AbeG0W3o (ORCPT ); Fri, 27 Jul 2018 18:29:44 -0400 Received: from mail-wm0-f47.google.com (mail-wm0-f47.google.com [74.125.82.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6B7992089B for ; Fri, 27 Jul 2018 21:06:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1532725564; bh=zT74hnl5692JFnw385aRNriLeubfh6BjrDVI/Qey2xs=; h=In-Reply-To:References:From:Date:Subject:To:Cc:From; b=xvQd5U8tc0CaiBdZkisvqqrh71rIsysw1r/5WpFF4QjkRMmAbs5Xlud7UJve+Rx3C 4bK0bVW07lrZmu5LESPDw0SukaGkDa/Y/jrnbaauSxqtwVGFLxyWZTsnb3t/EUFcUw 4FwsI1jhROC68ksqyPwUBAUcMs7rfn662UFwABOU= Received: by mail-wm0-f47.google.com with SMTP id l2-v6so3004447wme.1 for ; Fri, 27 Jul 2018 14:06:04 -0700 (PDT) X-Gm-Message-State: AOUpUlEtjdhNRVcOaU8UjgmrLiLNnYRJ5tn20rCjg11b1JkGVIJ/92co lQ1PHbfszt0OD1aNzHeXwhh4tjd3b8jz9VhnmVUB+Q== X-Google-Smtp-Source: AAOMgpc4HM8xxJYSUHjnMT+KiW23kfDlilBadzl9N9SOMFPZywNK7aD0L+IT+Wvcc5EFY3pUtnpJjUvR706Rvss1c88= X-Received: by 2002:a1c:8313:: with SMTP id f19-v6mr5417001wmd.144.1532725560973; Fri, 27 Jul 2018 14:06:00 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a1c:548:0:0:0:0:0 with HTTP; Fri, 27 Jul 2018 14:05:40 -0700 (PDT) In-Reply-To: References: <20170208080917.24320-1-khuey@kylehuey.com> <20170208080917.24320-9-khuey@kylehuey.com> <6F48D384-B29C-41B4-83F1-B02FC2480205@amacapital.net> From: Andy Lutomirski Date: Fri, 27 Jul 2018 14:05:40 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v14 8/9] KVM: x86: virtualize cpuid faulting To: Jim Mattson Cc: Andy Lutomirski , Kyle Huey , "Robert O'Callahan" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , X86 ML , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , David Matlack , Nadav Amit , Andi Kleen , LKML , user-mode-linux-devel@lists.sourceforge.net, "open list:USER-MODE LINUX (UML)" , Linux FS Devel , "open list:KERNEL SELFTEST FRAMEWORK" , kvm list Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 27, 2018 at 2:03 PM, Jim Mattson wrote: > On Fri, Jul 27, 2018 at 1:46 PM, Andy Lutomirski wr= ote: >>> On Jul 27, 2018, at 1:28 PM, Jim Mattson wrote: >>> Initializing this bit to zero helps with migration, but then if the >>> CPUID faulting bits in both MSRs are set, userspace has to take pains >>> to ensure that MSR_PLATFORM_INFO is restored first, or the >>> MSR_MISC_FEATURES_ENABLES value will be rejected. >> >> The code could drop the constraint and just let the entry possibly fail = if the MSRs are set wrong > > That would be an improvement, I think. I personally don't know enough about the QEMU, kvmtool, etc architecture to know whether this would be a good idea. > >>> I'm also concerned about the 0 in the "Maximum Non-Turbo Ratio" field >>> feeding into someone's calculated TSC frequency. >> >> Hmm. I don=E2=80=99t have a good answer to that. Are there any real CPUs= that have this MSR but don=E2=80=99t have that field? > > No. The reason I bring this up is that a customer has code that > expects to be able to derive the TSC frequency from this MSR (per > Intel's instructions in SDM volume 3, section 18.7.3), and they were > surprised to find that the MSR raises #GP on our platform. We're > looking into cherry-picking this support from upstream as a start, but > I know the customer would be unhappy to read zero from bits 15:8. Does KVM *have* a concept of "maximum non-turbo frequency" of the guest that it would make sense to expose here? If so, presumably the right solution is to expose it. From mboxrd@z Thu Jan 1 00:00:00 1970 From: luto at kernel.org (Andy Lutomirski) Date: Fri, 27 Jul 2018 14:05:40 -0700 Subject: [PATCH v14 8/9] KVM: x86: virtualize cpuid faulting In-Reply-To: References: <20170208080917.24320-1-khuey@kylehuey.com> <20170208080917.24320-9-khuey@kylehuey.com> <6F48D384-B29C-41B4-83F1-B02FC2480205@amacapital.net> Message-ID: On Fri, Jul 27, 2018 at 2:03 PM, Jim Mattson wrote: > On Fri, Jul 27, 2018 at 1:46 PM, Andy Lutomirski wrote: >>> On Jul 27, 2018, at 1:28 PM, Jim Mattson wrote: >>> Initializing this bit to zero helps with migration, but then if the >>> CPUID faulting bits in both MSRs are set, userspace has to take pains >>> to ensure that MSR_PLATFORM_INFO is restored first, or the >>> MSR_MISC_FEATURES_ENABLES value will be rejected. >> >> The code could drop the constraint and just let the entry possibly fail if the MSRs are set wrong > > That would be an improvement, I think. I personally don't know enough about the QEMU, kvmtool, etc architecture to know whether this would be a good idea. > >>> I'm also concerned about the 0 in the "Maximum Non-Turbo Ratio" field >>> feeding into someone's calculated TSC frequency. >> >> Hmm. I don’t have a good answer to that. Are there any real CPUs that have this MSR but don’t have that field? > > No. The reason I bring this up is that a customer has code that > expects to be able to derive the TSC frequency from this MSR (per > Intel's instructions in SDM volume 3, section 18.7.3), and they were > surprised to find that the MSR raises #GP on our platform. We're > looking into cherry-picking this support from upstream as a start, but > I know the customer would be unhappy to read zero from bits 15:8. Does KVM *have* a concept of "maximum non-turbo frequency" of the guest that it would make sense to expose here? If so, presumably the right solution is to expose it. -- To unsubscribe from this list: send the line "unsubscribe linux-kselftest" in the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: luto@kernel.org (Andy Lutomirski) Date: Fri, 27 Jul 2018 14:05:40 -0700 Subject: [PATCH v14 8/9] KVM: x86: virtualize cpuid faulting In-Reply-To: References: <20170208080917.24320-1-khuey@kylehuey.com> <20170208080917.24320-9-khuey@kylehuey.com> <6F48D384-B29C-41B4-83F1-B02FC2480205@amacapital.net> Message-ID: Content-Type: text/plain; charset="UTF-8" Message-ID: <20180727210540.c5ismuZ2BwbYwtPkeWT4LQ8Tr8UyPJBGcoRAlGRpecI@z> On Fri, Jul 27, 2018@2:03 PM, Jim Mattson wrote: > On Fri, Jul 27, 2018@1:46 PM, Andy Lutomirski wrote: >>> On Jul 27, 2018,@1:28 PM, Jim Mattson wrote: >>> Initializing this bit to zero helps with migration, but then if the >>> CPUID faulting bits in both MSRs are set, userspace has to take pains >>> to ensure that MSR_PLATFORM_INFO is restored first, or the >>> MSR_MISC_FEATURES_ENABLES value will be rejected. >> >> The code could drop the constraint and just let the entry possibly fail if the MSRs are set wrong > > That would be an improvement, I think. I personally don't know enough about the QEMU, kvmtool, etc architecture to know whether this would be a good idea. > >>> I'm also concerned about the 0 in the "Maximum Non-Turbo Ratio" field >>> feeding into someone's calculated TSC frequency. >> >> Hmm. I don’t have a good answer to that. Are there any real CPUs that have this MSR but don’t have that field? > > No. The reason I bring this up is that a customer has code that > expects to be able to derive the TSC frequency from this MSR (per > Intel's instructions in SDM volume 3, section 18.7.3), and they were > surprised to find that the MSR raises #GP on our platform. We're > looking into cherry-picking this support from upstream as a start, but > I know the customer would be unhappy to read zero from bits 15:8. Does KVM *have* a concept of "maximum non-turbo frequency" of the guest that it would make sense to expose here? If so, presumably the right solution is to expose it. -- To unsubscribe from this list: send the line "unsubscribe linux-kselftest" in the body of a message to majordomo at vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Lutomirski Subject: Re: [PATCH v14 8/9] KVM: x86: virtualize cpuid faulting Date: Fri, 27 Jul 2018 14:05:40 -0700 Message-ID: References: <20170208080917.24320-1-khuey@kylehuey.com> <20170208080917.24320-9-khuey@kylehuey.com> <6F48D384-B29C-41B4-83F1-B02FC2480205@amacapital.net> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Cc: Andy Lutomirski , Kyle Huey , "Robert O'Callahan" , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , X86 ML , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , "Rafael J. Wysocki" , Dmitry Safonov , To: Jim Mattson Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Fri, Jul 27, 2018 at 2:03 PM, Jim Mattson wrote: > On Fri, Jul 27, 2018 at 1:46 PM, Andy Lutomirski wr= ote: >>> On Jul 27, 2018, at 1:28 PM, Jim Mattson wrote: >>> Initializing this bit to zero helps with migration, but then if the >>> CPUID faulting bits in both MSRs are set, userspace has to take pains >>> to ensure that MSR_PLATFORM_INFO is restored first, or the >>> MSR_MISC_FEATURES_ENABLES value will be rejected. >> >> The code could drop the constraint and just let the entry possibly fail = if the MSRs are set wrong > > That would be an improvement, I think. I personally don't know enough about the QEMU, kvmtool, etc architecture to know whether this would be a good idea. > >>> I'm also concerned about the 0 in the "Maximum Non-Turbo Ratio" field >>> feeding into someone's calculated TSC frequency. >> >> Hmm. I don=E2=80=99t have a good answer to that. Are there any real CPUs= that have this MSR but don=E2=80=99t have that field? > > No. The reason I bring this up is that a customer has code that > expects to be able to derive the TSC frequency from this MSR (per > Intel's instructions in SDM volume 3, section 18.7.3), and they were > surprised to find that the MSR raises #GP on our platform. We're > looking into cherry-picking this support from upstream as a start, but > I know the customer would be unhappy to read zero from bits 15:8. Does KVM *have* a concept of "maximum non-turbo frequency" of the guest that it would make sense to expose here? If so, presumably the right solution is to expose it.