From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753748AbbEUFse (ORCPT ); Thu, 21 May 2015 01:48:34 -0400 Received: from mail-la0-f41.google.com ([209.85.215.41]:33662 "EHLO mail-la0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751784AbbEUFsb (ORCPT ); Thu, 21 May 2015 01:48:31 -0400 MIME-Version: 1.0 In-Reply-To: <555D3629.8080002@kernel.org> References: <1432022472-2224-1-git-send-email-ray.huang@amd.com> <1432022472-2224-3-git-send-email-ray.huang@amd.com> <555D3629.8080002@kernel.org> From: Andy Lutomirski Date: Wed, 20 May 2015 22:48:09 -0700 Message-ID: Subject: Re: [RFC PATCH 2/4] x86, mwaitt: introduce mwaitx idle with a configurable timer To: Huang Rui , Thomas Gleixner , "Rafael J. Wysocki" , Len Brown , Borislav Petkov Cc: John Stultz , Tony Li , X86 ML , Peter Zijlstra , Aaron Lu , Fengguang Wu , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On May 20, 2015 6:34 PM, "Andy Lutomirski" wrote: > If we did that *and* we had a non-crappy mwaitx, then we could apply an optimization: when going idle, we could turn off the TSC deadline timer and use mwaitx instead. This would about an interrupt if the event that wakes us is our timer. > Hey, Intel, want to document your secret "Timed MWAIT" feature? It causes a transition to C0 when the deadline expires (see 4.2.4 of the Desktop 4th Generation Intel Core Processor Family Datasheet Volume 1, order number 328897-001) and it even has an erratum (HSD63 / BDM32), but the instruction itself doesn't appear to be documented. --Andy