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From: Andy Lutomirski <luto@amacapital.net>
Date: Tue, 26 May 2015 18:01:03 -0700
Message-ID: <CALCETrXgeMcC-H-S7Y=mP9cbP057m7a2dDEnACK-fJbz3cRjKw@mail.gmail.com>
Subject: Re: [RFC PATCH 2/4] x86, mwaitt: introduce mwaitx idle with a
 configurable timer
To: Huang Rui <ray.huang@amd.com>, Thomas Gleixner <tglx@linutronix.de>,
        "Rafael J. Wysocki" <rjw@rjwysocki.net>, Len Brown <lenb@kernel.org>,
        Borislav Petkov <bp@suse.de>
Cc: John Stultz <john.stultz@linaro.org>, Tony Li <tony.li@amd.com>,
        X86 ML <x86@kernel.org>, Peter Zijlstra <peterz@infradead.org>,
        Aaron Lu <aaron.lu@intel.com>, Fengguang Wu <fengguang.wu@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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On Wed, May 20, 2015 at 10:48 PM, Andy Lutomirski <luto@amacapital.net> wrote:
> On May 20, 2015 6:34 PM, "Andy Lutomirski" <luto@kernel.org> wrote:
>> If we did that *and* we had a non-crappy mwaitx, then we could apply an optimization: when going idle, we could turn off the TSC deadline timer and use mwaitx instead.  This would about an interrupt if the event that wakes us is our timer.
>>
>
> Hey, Intel, want to document your secret "Timed MWAIT" feature?  It
> causes a transition to C0 when the deadline expires (see 4.2.4 of the
> Desktop 4th Generation Intel Core Processor Family Datasheet Volume 1,
> order number 328897-001) and it even has an erratum (HSD63 / BDM32),
> but the instruction itself doesn't appear to be documented.
>

Found more:

https://chromium-review.googlesource.com/#/c/205161/

Oddly, Coreboot seems to have mis-spelled that MSR.  It's
MSR_PKG_CST_CONFIG_CONTROL, and bit 31 isn't defined in the SDM
(unsurprisingly).

--Andy