From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_MED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D3D6C3F2D1 for ; Wed, 4 Mar 2020 17:13:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E3D2822B48 for ; Wed, 4 Mar 2020 17:13:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="tGDKQyb0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729675AbgCDRNx (ORCPT ); Wed, 4 Mar 2020 12:13:53 -0500 Received: from mail-io1-f41.google.com ([209.85.166.41]:41761 "EHLO mail-io1-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726748AbgCDRNw (ORCPT ); Wed, 4 Mar 2020 12:13:52 -0500 Received: by mail-io1-f41.google.com with SMTP id m25so3220853ioo.8 for ; Wed, 04 Mar 2020 09:13:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LccCV/NpVCNcplwkMeJmlIoskRRTJ9nTNKn+RvMhq/k=; b=tGDKQyb0/66dbSez+d1maOoZX+onksVYfC4cikQmXFQkkGEOo4T+DpBGhLgsCJJ3bJ 4qahjgysHT90te4gmUoEY7CyAmFV+ioPpMuTEE/ZiB+PBIgG5RlBFt8mSRwDswIKz/0J /WUC96qae6zacHoL5JBWRCLIMKMP/aED6A/IWxp6AILmz5XtKQzFV3/GhTv1clXvjkfh z5WCreUYIUZbqdVMAyIYqW3tDOmpvPvId9wtVdzte/4T9N4F/uwowzNGalA1begZ4GO0 fUyp7y/0SZKBb4Gn/MR4b41Smq2I7WXfQS8f4YpuX3ty++Wnrh720799wEO042UhmaUY Zfyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LccCV/NpVCNcplwkMeJmlIoskRRTJ9nTNKn+RvMhq/k=; b=FZ5TZSt4ZeUN15GXdUWBwe6XNbIot6tXcKUBUfFhaoJ9na6kavvuVyBePa6MOC8LAO 6PN93xSqqSbscE3JuxALv8Mx2BTR/6uYvtCImU+eLSZZsEeSeUrSCQ9ykkvf3VJNGB0v YdgW1LuZbDnjU64efeUPRnnpwG5j5fn5k/OK32RDQhEsXfkIur0qo7BDM7GGOrbihp6P 7qJuz+i3qPTi4aYIFWhlMfiFAEWxUFvOBescOkA6mXqk7TQGi4Dmf5esBD7PvsDhSERS 8RpVutEuu2yICzmwzZoEuvy13OCeUHWY7ErB7A2Yo03qfU/eLFrMUnpl9xUuuaJI7eeA IEBQ== X-Gm-Message-State: ANhLgQ0PBsZfpO0iuacgdv8FonNd/iN0lJSIAAS3AgShqs9tqFxU4W2N sB/MCrOXT1DUJL0CiQb+Z1kavw0k25sPBh736n5HcA== X-Google-Smtp-Source: ADFU+vvLfOuiiw3NhbcYxvmwxCcubxcZbCtZ543KSrZpyd18SOMJycPFGgYRCCMoPYZfks1EN9ElTG2o/FvHG+z7xRM= X-Received: by 2002:a6b:4e15:: with SMTP id c21mr2856195iob.119.1583342031673; Wed, 04 Mar 2020 09:13:51 -0800 (PST) MIME-Version: 1.0 References: <20200304161912.GC21662@linux.intel.com> In-Reply-To: <20200304161912.GC21662@linux.intel.com> From: Jim Mattson Date: Wed, 4 Mar 2020 09:13:40 -0800 Message-ID: Subject: Re: Nested virtualization and software page walks in the L1 hypervsior To: Sean Christopherson Cc: Peter Feiner , kvm list Content-Type: text/plain; charset="UTF-8" Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, Mar 4, 2020 at 8:19 AM Sean Christopherson wrote: > > On Tue, Mar 03, 2020 at 04:22:57PM -0800, Peter Feiner wrote: > > On Sat, Feb 29, 2020 at 2:31 PM Jim Mattson wrote: > > > > > > Peter Feiner asked me an intriguing question the other day. If you > > > have a hypervisor that walks its guest's x86 page tables in software > > > during emulation, how can you make that software page walk behave > > > exactly like a hardware page walk? In particular, when the hypervisor > > > is running as an L1 guest, how is it possible to write the software > > > page walk so that accesses to L2's x86 page tables are treated as > > > reads if L0 isn't using EPT A/D bits, but they're treated as writes if > > > L0 is using EPT A/D bits? (Paravirtualization is not allowed.) > > > > > > It seems to me that this behavior isn't virtualizable. Am I wrong? > > > > Jim, I thought about this some more after talking to you. I think it's > > entirely moot what L0 sees so long as L1 and L2 work correctly. So, > > the question becomes, is there anything that L0 could possibly rely on > > this behavior for? My first thought was dirty tracking, but that's not > > a problem because *writes* to the L2 x86 page tables' A/D bits will > > still be intercepted by L0. The missing D bit on a guest page that > > doesn't actually change doesn't matter :-) > > Ya. The hardware behavior of setting the Dirty bit is effectively a > spurious update. Not emulating that behavior is arguably a good thing :-). > > Presumably, the EPT walks are overzealous in treating IA32 page walks as > writes to allow for simpler hardware implementations, e.g. the mechanism to > handle A/D bit updates doesn't need to handle the case where setting an A/D > bit in an IA32 page walk would also trigger an D bit update for the > associated EPT walk. I was actually more concerned about the EPT permissions aspect. With EPT A/D bits enabled, a non-writable EPT page can't be used for a hardware page walk, but it can be used for a software page walk. Maybe that's neither here nor there.