[PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Marek Behún]

From: Pali Rohár <pali@kernel.org>

This property specifies slot power limit in mW unit. It is a form-factor
and board specific value and must be initialized by hardware.

Some PCIe controllers delegate this work to software to allow hardware
flexibility and therefore this property basically specifies what should
host bridge program into PCIe Slot Capabilities registers.

The property needs to be specified in mW unit instead of the special format
defined by Slot Capabilities (which encodes scaling factor or different
unit). Host drivers should convert the value from mW to needed format.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
 Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 6a8f2874a24d..7296d599c5ac 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -32,6 +32,12 @@ driver implementation may support the following properties:
    root port to downstream device and host bridge drivers can do programming
    which depends on CLKREQ signal existence. For example, programming root port
    not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
+- slot-power-limit-miliwatt:
+   If present, this property specifies slot power limit in milliwatts. Host
+   drivers can parse this property and use it for programming Root Port or host
+   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
+   through the Root Port or host bridge when transitioning PCIe link from a
+   non-DL_Up Status to a DL_Up Status.
 
 PCI-PCI Bridge properties
 -------------------------
-- 
2.32.0

[PATCH dt + pci 2/2] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property

[Marek Behún]

From: Pali Rohár <pali@kernel.org>

Add function of_pci_get_slot_power_limit(), which parses the
`slot-power-limit-milliwatt` DT property, returning the value in
milliwatts and in format ready for the PCIe Slot Capabilities Register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/pci/of.c  | 64 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/pci.h | 15 +++++++++++
 2 files changed, 79 insertions(+)

diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index d84381ce82b5..9c1a38d5dd99 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -627,3 +627,67 @@ int of_pci_get_max_link_speed(struct device_node *node)
 	return max_link_speed;
 }
 EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
+
+/**
+ * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt"
+ *				 property.
+ *
+ * @node: device tree node with the slot power limit information
+ * @slot_power_limit_value: pointer where the value should be stored in PCIe
+ *			    Slot Capabilities Register format
+ * @slot_power_limit_scale: pointer where the scale should be stored in PCIe
+ *			    Slot Capabilities Register format
+ *
+ * Returns the slot power limit in milliwatts and if @slot_power_limit_value
+ * and @slot_power_limit_scale pointers are non-NULL, fills in the value and
+ * scale in format used by PCIe Slot Capabilities Register.
+ *
+ * If the property is not found or is invalid, returns 0.
+ */
+u32 of_pci_get_slot_power_limit(struct device_node *node,
+				u8 *slot_power_limit_value,
+				u8 *slot_power_limit_scale)
+{
+	u32 slot_power_limit;
+	u8 value, scale;
+
+	if (of_property_read_u32(node, "slot-power-limit-milliwatt",
+				 &slot_power_limit))
+		slot_power_limit = 0;
+
+	/* Calculate Slot Power Limit Value and Slot Power Limit Scale */
+	if (slot_power_limit == 0) {
+		value = 0x00;
+		scale = 0;
+	} else if (slot_power_limit <= 255) {
+		value = slot_power_limit;
+		scale = 3;
+	} else if (slot_power_limit <= 255*10) {
+		value = slot_power_limit / 10;
+		scale = 2;
+	} else if (slot_power_limit <= 255*100) {
+		value = slot_power_limit / 100;
+		scale = 1;
+	} else if (slot_power_limit <= 239*1000) {
+		value = slot_power_limit / 1000;
+		scale = 0;
+	} else if (slot_power_limit <= 250*1000) {
+		value = 0xF0;
+		scale = 0;
+	} else if (slot_power_limit <= 275*1000) {
+		value = 0xF1;
+		scale = 0;
+	} else {
+		value = 0xF2;
+		scale = 0;
+	}
+
+	if (slot_power_limit_value)
+		*slot_power_limit_value = value;
+
+	if (slot_power_limit_scale)
+		*slot_power_limit_scale = scale;
+
+	return slot_power_limit;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 1cce56c2aea0..9352278141be 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -665,6 +665,9 @@ struct device_node;
 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 int of_get_pci_domain_nr(struct device_node *node);
 int of_pci_get_max_link_speed(struct device_node *node);
+u32 of_pci_get_slot_power_limit(struct device_node *node,
+				u8 *slot_power_limit_value,
+				u8 *slot_power_limit_scale);
 void pci_set_of_node(struct pci_dev *dev);
 void pci_release_of_node(struct pci_dev *dev);
 void pci_set_bus_of_node(struct pci_bus *bus);
@@ -691,6 +694,18 @@ of_pci_get_max_link_speed(struct device_node *node)
 	return -EINVAL;
 }
 
+static inline u32
+of_pci_get_slot_power_limit(struct device_node *node,
+			    u8 *slot_power_limit_value,
+			    u8 *slot_power_limit_scale)
+{
+	if (slot_power_limit_value)
+		*slot_power_limit_value = 0;
+	if (slot_power_limit_scale)
+		*slot_power_limit_scale = 0;
+	return 0;
+}
+
 static inline void pci_set_of_node(struct pci_dev *dev) { }
 static inline void pci_release_of_node(struct pci_dev *dev) { }
 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
-- 
2.32.0

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Rob Herring]

On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> This property specifies slot power limit in mW unit. It is a form-factor
> and board specific value and must be initialized by hardware.
> 
> Some PCIe controllers delegate this work to software to allow hardware
> flexibility and therefore this property basically specifies what should
> host bridge program into PCIe Slot Capabilities registers.
> 
> The property needs to be specified in mW unit instead of the special format
> defined by Slot Capabilities (which encodes scaling factor or different
> unit). Host drivers should convert the value from mW to needed format.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> index 6a8f2874a24d..7296d599c5ac 100644
> --- a/Documentation/devicetree/bindings/pci/pci.txt
> +++ b/Documentation/devicetree/bindings/pci/pci.txt
> @@ -32,6 +32,12 @@ driver implementation may support the following properties:
>     root port to downstream device and host bridge drivers can do programming
>     which depends on CLKREQ signal existence. For example, programming root port
>     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> +- slot-power-limit-miliwatt:

Typo.

But we shouldn't be adding to pci.txt. This needs to go in the 
schema[1]. Patch to devicetree-spec list or GH PR is fine.

> +   If present, this property specifies slot power limit in milliwatts. Host
> +   drivers can parse this property and use it for programming Root Port or host
> +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> +   through the Root Port or host bridge when transitioning PCIe link from a
> +   non-DL_Up Status to a DL_Up Status.

If your slots are behind a switch, then doesn't this apply to any bridge 
port?

[1] https://github.com/devicetree-org/dt-schema/blob/main/schemas/pci/pci-bus.yaml

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Friday 12 November 2021 09:25:20 Rob Herring wrote:
> On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > +   If present, this property specifies slot power limit in milliwatts. Host
> > +   drivers can parse this property and use it for programming Root Port or host
> > +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> > +   through the Root Port or host bridge when transitioning PCIe link from a
> > +   non-DL_Up Status to a DL_Up Status.
> 
> If your slots are behind a switch, then doesn't this apply to any bridge 
> port?

The main issue here is that pci.txt (and also scheme on github) is
mixing host bridge and root ports into one node. This new property
should be defined at the same place where is supports-clkreq or
reset-gpios, as it belongs to them.

And you are right, that this new property should be defined only for
root ports and downstream ports of switch.

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Rob Herring]

On Fri, Nov 12, 2021 at 9:32 AM Pali Rohár <pali@kernel.org> wrote:
>
> On Friday 12 November 2021 09:25:20 Rob Herring wrote:
> > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > +   If present, this property specifies slot power limit in milliwatts. Host
> > > +   drivers can parse this property and use it for programming Root Port or host
> > > +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> > > +   through the Root Port or host bridge when transitioning PCIe link from a
> > > +   non-DL_Up Status to a DL_Up Status.
> >
> > If your slots are behind a switch, then doesn't this apply to any bridge
> > port?
>
> The main issue here is that pci.txt (and also scheme on github) is
> mixing host bridge and root ports into one node. This new property
> should be defined at the same place where is supports-clkreq or
> reset-gpios, as it belongs to them.

Unfortunately that ship has already sailed. So we can split things up,
but we still have to allow for the existing cases. I'm happy to take
changes splitting up pci-bus.yaml to 2 or 3 schemas (host bridge,
root-port, and PCI(e)-PCI(e) bridge?).

> And you are right, that this new property should be defined only for
> root ports and downstream ports of switch.

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Friday 12 November 2021 10:30:01 Rob Herring wrote:
> On Fri, Nov 12, 2021 at 9:32 AM Pali Rohár <pali@kernel.org> wrote:
> >
> > On Friday 12 November 2021 09:25:20 Rob Herring wrote:
> > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > > +   If present, this property specifies slot power limit in milliwatts. Host
> > > > +   drivers can parse this property and use it for programming Root Port or host
> > > > +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> > > > +   through the Root Port or host bridge when transitioning PCIe link from a
> > > > +   non-DL_Up Status to a DL_Up Status.
> > >
> > > If your slots are behind a switch, then doesn't this apply to any bridge
> > > port?
> >
> > The main issue here is that pci.txt (and also scheme on github) is
> > mixing host bridge and root ports into one node. This new property
> > should be defined at the same place where is supports-clkreq or
> > reset-gpios, as it belongs to them.
> 
> Unfortunately that ship has already sailed. So we can split things up,
> but we still have to allow for the existing cases. I'm happy to take
> changes splitting up pci-bus.yaml to 2 or 3 schemas (host bridge,
> root-port, and PCI(e)-PCI(e) bridge?).

Well, no problem. I just need to know how you want to handle backward
compatibility definitions in YAML. Because it is possible via versioning
(like in JSONSchema-like structures in OpenAPI versioning) or via
deprecated attributes or via defining two schemas (one strict and one
loose)... There are lot of options and I saw all these options in
different projects which use YAML or JSON.

I did not know about github repository, I always looked at schemas and
definitions only in linux kernel tree and external files which were
mentioned in kernel tree.

Something I wrote in my RFC email, but I wrote this email patch...
https://lore.kernel.org/linux-pci/20211023144252.z7ou2l2tvm6cvtf7@pali/

> > And you are right, that this new property should be defined only for
> > root ports and downstream ports of switch.

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Marek Behún]

On Fri, 12 Nov 2021 18:12:49 +0100
Pali Rohár <pali@kernel.org> wrote:

> On Friday 12 November 2021 10:30:01 Rob Herring wrote:
> > On Fri, Nov 12, 2021 at 9:32 AM Pali Rohár <pali@kernel.org> wrote:  
> > >
> > > On Friday 12 November 2021 09:25:20 Rob Herring wrote:  
> > > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:  
> > > > > +   If present, this property specifies slot power limit in milliwatts. Host
> > > > > +   drivers can parse this property and use it for programming Root Port or host
> > > > > +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> > > > > +   through the Root Port or host bridge when transitioning PCIe link from a
> > > > > +   non-DL_Up Status to a DL_Up Status.  
> > > >
> > > > If your slots are behind a switch, then doesn't this apply to any bridge
> > > > port?  
> > >
> > > The main issue here is that pci.txt (and also scheme on github) is
> > > mixing host bridge and root ports into one node. This new property
> > > should be defined at the same place where is supports-clkreq or
> > > reset-gpios, as it belongs to them.  
> > 
> > Unfortunately that ship has already sailed. So we can split things up,
> > but we still have to allow for the existing cases. I'm happy to take
> > changes splitting up pci-bus.yaml to 2 or 3 schemas (host bridge,
> > root-port, and PCI(e)-PCI(e) bridge?).  
> 
> Well, no problem. I just need to know how you want to handle backward
> compatibility definitions in YAML. Because it is possible via versioning
> (like in JSONSchema-like structures in OpenAPI versioning) or via
> deprecated attributes or via defining two schemas (one strict and one
> loose)... There are lot of options and I saw all these options in
> different projects which use YAML or JSON.
> 
> I did not know about github repository, I always looked at schemas and
> definitions only in linux kernel tree and external files which were
> mentioned in kernel tree.
> 
> Something I wrote in my RFC email, but I wrote this email patch...
> https://lore.kernel.org/linux-pci/20211023144252.z7ou2l2tvm6cvtf7@pali/

New kernel should always work with old device-tree. But does also new
device-tree need to work with old kernels?

Marek

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Rob Herring]

On Fri, Nov 12, 2021 at 11:12 AM Pali Rohár <pali@kernel.org> wrote:
>
> On Friday 12 November 2021 10:30:01 Rob Herring wrote:
> > On Fri, Nov 12, 2021 at 9:32 AM Pali Rohár <pali@kernel.org> wrote:
> > >
> > > On Friday 12 November 2021 09:25:20 Rob Herring wrote:
> > > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > > > +   If present, this property specifies slot power limit in milliwatts. Host
> > > > > +   drivers can parse this property and use it for programming Root Port or host
> > > > > +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> > > > > +   through the Root Port or host bridge when transitioning PCIe link from a
> > > > > +   non-DL_Up Status to a DL_Up Status.
> > > >
> > > > If your slots are behind a switch, then doesn't this apply to any bridge
> > > > port?
> > >
> > > The main issue here is that pci.txt (and also scheme on github) is
> > > mixing host bridge and root ports into one node. This new property
> > > should be defined at the same place where is supports-clkreq or
> > > reset-gpios, as it belongs to them.
> >
> > Unfortunately that ship has already sailed. So we can split things up,
> > but we still have to allow for the existing cases. I'm happy to take
> > changes splitting up pci-bus.yaml to 2 or 3 schemas (host bridge,
> > root-port, and PCI(e)-PCI(e) bridge?).
>
> Well, no problem. I just need to know how you want to handle backward
> compatibility definitions in YAML. Because it is possible via versioning
> (like in JSONSchema-like structures in OpenAPI versioning) or via

Got a pointer to that?

> deprecated attributes or via defining two schemas (one strict and one
> loose)... There are lot of options and I saw all these options in
> different projects which use YAML or JSON.

The short answer is we don't have a defined way beyond deprecating
properties within a given binding with 'deprecated: true'. The only
versioning we have ATM is the kernel requires a minimum version of
dtschema (which we'll have to bump for all this).

We could have something like:

old-pci-bridge.yaml:
  allOf:
    - $ref: pci-host-bridge.yaml#
    - $ref: pcie-port.yaml#

new-pci-bridge.yaml:
  allOf:
    - $ref: pci-host-bridge.yaml#
  properties:
    pci@0:
      $ref: pcie-port.yaml#

And then both of the above schemas will have $ref to a pci-bridge.yaml
schema which should be most of pci-bus.yaml. linux,pci-domain and
dma-ranges? go to pci-host-bridge.yaml. max-link-speed, num-lanes,
reset-gpios, slot-power-limit-milliwatt, and the pending supply
additions (Broadcom) go to pcie-port.yaml.

> I did not know about github repository, I always looked at schemas and
> definitions only in linux kernel tree and external files which were
> mentioned in kernel tree.
>
> Something I wrote in my RFC email, but I wrote this email patch...
> https://lore.kernel.org/linux-pci/20211023144252.z7ou2l2tvm6cvtf7@pali/

I think we're pretty much in alignment. Look at the Broadcom portdrv
changes proposed if you haven't already. It's all interrelated.

Rob

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Friday 12 November 2021 14:56:26 Rob Herring wrote:
> On Fri, Nov 12, 2021 at 11:12 AM Pali Rohár <pali@kernel.org> wrote:
> >
> > On Friday 12 November 2021 10:30:01 Rob Herring wrote:
> > > On Fri, Nov 12, 2021 at 9:32 AM Pali Rohár <pali@kernel.org> wrote:
> > > >
> > > > On Friday 12 November 2021 09:25:20 Rob Herring wrote:
> > > > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > > > > +   If present, this property specifies slot power limit in milliwatts. Host
> > > > > > +   drivers can parse this property and use it for programming Root Port or host
> > > > > > +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> > > > > > +   through the Root Port or host bridge when transitioning PCIe link from a
> > > > > > +   non-DL_Up Status to a DL_Up Status.
> > > > >
> > > > > If your slots are behind a switch, then doesn't this apply to any bridge
> > > > > port?
> > > >
> > > > The main issue here is that pci.txt (and also scheme on github) is
> > > > mixing host bridge and root ports into one node. This new property
> > > > should be defined at the same place where is supports-clkreq or
> > > > reset-gpios, as it belongs to them.
> > >
> > > Unfortunately that ship has already sailed. So we can split things up,
> > > but we still have to allow for the existing cases. I'm happy to take
> > > changes splitting up pci-bus.yaml to 2 or 3 schemas (host bridge,
> > > root-port, and PCI(e)-PCI(e) bridge?).
> >
> > Well, no problem. I just need to know how you want to handle backward
> > compatibility definitions in YAML. Because it is possible via versioning
> > (like in JSONSchema-like structures in OpenAPI versioning) or via
> 
> Got a pointer to that?

I'm not sure which pointer you want. OpenAPI is used for defining
application APIs which use either JSON or YAML (or something other)
content over HTTP protocol. Specification of OpenAPI is here:

https://swagger.io/specification/

Lot of times API schemas are written in YAML format (even when API
content is JSON) and OpenAPI uses JSONSchema-like schemas (at least in
version 3.0, they are not same as JSONSchema, it is some subset with own
extensions) and looks very similar to DT schemas.

> > deprecated attributes or via defining two schemas (one strict and one
> > loose)... There are lot of options and I saw all these options in
> > different projects which use YAML or JSON.
> 
> The short answer is we don't have a defined way beyond deprecating
> properties within a given binding with 'deprecated: true'.

Is there any formal definition what this 'deprecated: true' means? It
throw some warning during validation? Or it is disallowed to use
deprecated properties in newly written DTS files? Or it is just a
syntax decorator without any semantic meaning?

> The only
> versioning we have ATM is the kernel requires a minimum version of
> dtschema (which we'll have to bump for all this).
> 
> We could have something like:
> 
> old-pci-bridge.yaml:
>   allOf:
>     - $ref: pci-host-bridge.yaml#
>     - $ref: pcie-port.yaml#
> 
> new-pci-bridge.yaml:
>   allOf:
>     - $ref: pci-host-bridge.yaml#
>   properties:
>     pci@0:
>       $ref: pcie-port.yaml#
> 
> And then both of the above schemas will have $ref to a pci-bridge.yaml
> schema which should be most of pci-bus.yaml. linux,pci-domain and
> dma-ranges? go to pci-host-bridge.yaml. max-link-speed, num-lanes,
> reset-gpios, slot-power-limit-milliwatt, and the pending supply
> additions (Broadcom) go to pcie-port.yaml.

This looks like a nice solution.

I would propose just one other thing: Do not allow new kernel drivers
to use old-pci-bridge.yaml schema, so new drivers would not use old
"deprecated" APIs...

So should I prepare some schemas and send it for review via github pull
request mechanism? (I'm not sure how is that github project related to
kernel DTS bindings and how is reviewing on it going...)

> > I did not know about github repository, I always looked at schemas and
> > definitions only in linux kernel tree and external files which were
> > mentioned in kernel tree.
> >
> > Something I wrote in my RFC email, but I wrote this email patch...
> > https://lore.kernel.org/linux-pci/20211023144252.z7ou2l2tvm6cvtf7@pali/
> 
> I think we're pretty much in alignment. Look at the Broadcom portdrv
> changes proposed if you haven't already. It's all interrelated.

Do you have link to DTS file, how it looks like in real usage?

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Saturday 13 November 2021 12:31:06 Pali Rohár wrote:
> On Friday 12 November 2021 14:56:26 Rob Herring wrote:
> > The only
> > versioning we have ATM is the kernel requires a minimum version of
> > dtschema (which we'll have to bump for all this).
> > 
> > We could have something like:
> > 
> > old-pci-bridge.yaml:
> >   allOf:
> >     - $ref: pci-host-bridge.yaml#
> >     - $ref: pcie-port.yaml#
> > 
> > new-pci-bridge.yaml:
> >   allOf:
> >     - $ref: pci-host-bridge.yaml#
> >   properties:
> >     pci@0:
> >       $ref: pcie-port.yaml#
> > 
> > And then both of the above schemas will have $ref to a pci-bridge.yaml
> > schema which should be most of pci-bus.yaml. linux,pci-domain and
> > dma-ranges? go to pci-host-bridge.yaml. max-link-speed, num-lanes,
> > reset-gpios, slot-power-limit-milliwatt, and the pending supply
> > additions (Broadcom) go to pcie-port.yaml.
> 
> This looks like a nice solution.
> 
> I would propose just one other thing: Do not allow new kernel drivers
> to use old-pci-bridge.yaml schema, so new drivers would not use old
> "deprecated" APIs...
> 
> So should I prepare some schemas and send it for review via github pull
> request mechanism? (I'm not sure how is that github project related to
> kernel DTS bindings and how is reviewing on it going...)

I prepared something for discussion:
https://github.com/devicetree-org/dt-schema/pull/64

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Marek Behún]

On Fri, 12 Nov 2021 09:25:20 -0600
Rob Herring <robh@kernel.org> wrote:

> On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > From: Pali Rohár <pali@kernel.org>
> > 
> > This property specifies slot power limit in mW unit. It is a form-factor
> > and board specific value and must be initialized by hardware.
> > 
> > Some PCIe controllers delegate this work to software to allow hardware
> > flexibility and therefore this property basically specifies what should
> > host bridge program into PCIe Slot Capabilities registers.
> > 
> > The property needs to be specified in mW unit instead of the special format
> > defined by Slot Capabilities (which encodes scaling factor or different
> > unit). Host drivers should convert the value from mW to needed format.
> > 
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > Signed-off-by: Marek Behún <kabel@kernel.org>
> > ---
> >  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> > index 6a8f2874a24d..7296d599c5ac 100644
> > --- a/Documentation/devicetree/bindings/pci/pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/pci.txt
> > @@ -32,6 +32,12 @@ driver implementation may support the following properties:
> >     root port to downstream device and host bridge drivers can do programming
> >     which depends on CLKREQ signal existence. For example, programming root port
> >     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > +- slot-power-limit-miliwatt:  
> 
> Typo.
> 
> But we shouldn't be adding to pci.txt. This needs to go in the 
> schema[1]. Patch to devicetree-spec list or GH PR is fine.

Hello Rob,

Pali's PR draft https://github.com/devicetree-org/dt-schema/pull/64
looks like it's going to take some time to work out.

In the meantime, is it possible to somehow get the
slot-power-limit-milliwatt property merged into pci.txt so that we can start
putting it into existing device-trees?

Or would it break dt_bindings_check if it isn't put into dt-schema's
pci-bus.yaml?

Or should we simply put it into current version of pci-bus.yaml and
work out the split proposed by Pali's PR afterwards?

Marek

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Rob Herring]

On Wed, Jan 5, 2022 at 8:14 AM Marek Behún <kabel@kernel.org> wrote:
>
> On Fri, 12 Nov 2021 09:25:20 -0600
> Rob Herring <robh@kernel.org> wrote:
>
> > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > From: Pali Rohár <pali@kernel.org>
> > >
> > > This property specifies slot power limit in mW unit. It is a form-factor
> > > and board specific value and must be initialized by hardware.
> > >
> > > Some PCIe controllers delegate this work to software to allow hardware
> > > flexibility and therefore this property basically specifies what should
> > > host bridge program into PCIe Slot Capabilities registers.
> > >
> > > The property needs to be specified in mW unit instead of the special format
> > > defined by Slot Capabilities (which encodes scaling factor or different
> > > unit). Host drivers should convert the value from mW to needed format.
> > >
> > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > Signed-off-by: Marek Behún <kabel@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> > > index 6a8f2874a24d..7296d599c5ac 100644
> > > --- a/Documentation/devicetree/bindings/pci/pci.txt
> > > +++ b/Documentation/devicetree/bindings/pci/pci.txt
> > > @@ -32,6 +32,12 @@ driver implementation may support the following properties:
> > >     root port to downstream device and host bridge drivers can do programming
> > >     which depends on CLKREQ signal existence. For example, programming root port
> > >     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > > +- slot-power-limit-miliwatt:
> >
> > Typo.
> >
> > But we shouldn't be adding to pci.txt. This needs to go in the
> > schema[1]. Patch to devicetree-spec list or GH PR is fine.
>
> Hello Rob,
>
> Pali's PR draft https://github.com/devicetree-org/dt-schema/pull/64
> looks like it's going to take some time to work out.
>
> In the meantime, is it possible to somehow get the
> slot-power-limit-milliwatt property merged into pci.txt so that we can start
> putting it into existing device-trees?
>
> Or would it break dt_bindings_check if it isn't put into dt-schema's
> pci-bus.yaml?
>
> Or should we simply put it into current version of pci-bus.yaml and
> work out the split proposed by Pali's PR afterwards?

In the existing pci-bus.yaml is fine.

Rob

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Wednesday 05 January 2022 08:27:21 Rob Herring wrote:
> On Wed, Jan 5, 2022 at 8:14 AM Marek Behún <kabel@kernel.org> wrote:
> >
> > On Fri, 12 Nov 2021 09:25:20 -0600
> > Rob Herring <robh@kernel.org> wrote:
> >
> > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > > From: Pali Rohár <pali@kernel.org>
> > > >
> > > > This property specifies slot power limit in mW unit. It is a form-factor
> > > > and board specific value and must be initialized by hardware.
> > > >
> > > > Some PCIe controllers delegate this work to software to allow hardware
> > > > flexibility and therefore this property basically specifies what should
> > > > host bridge program into PCIe Slot Capabilities registers.
> > > >
> > > > The property needs to be specified in mW unit instead of the special format
> > > > defined by Slot Capabilities (which encodes scaling factor or different
> > > > unit). Host drivers should convert the value from mW to needed format.
> > > >
> > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > Signed-off-by: Marek Behún <kabel@kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
> > > >  1 file changed, 6 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> > > > index 6a8f2874a24d..7296d599c5ac 100644
> > > > --- a/Documentation/devicetree/bindings/pci/pci.txt
> > > > +++ b/Documentation/devicetree/bindings/pci/pci.txt
> > > > @@ -32,6 +32,12 @@ driver implementation may support the following properties:
> > > >     root port to downstream device and host bridge drivers can do programming
> > > >     which depends on CLKREQ signal existence. For example, programming root port
> > > >     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > > > +- slot-power-limit-miliwatt:
> > >
> > > Typo.
> > >
> > > But we shouldn't be adding to pci.txt. This needs to go in the
> > > schema[1]. Patch to devicetree-spec list or GH PR is fine.
> >
> > Hello Rob,
> >
> > Pali's PR draft https://github.com/devicetree-org/dt-schema/pull/64
> > looks like it's going to take some time to work out.
> >
> > In the meantime, is it possible to somehow get the
> > slot-power-limit-milliwatt property merged into pci.txt so that we can start
> > putting it into existing device-trees?
> >
> > Or would it break dt_bindings_check if it isn't put into dt-schema's
> > pci-bus.yaml?
> >
> > Or should we simply put it into current version of pci-bus.yaml and
> > work out the split proposed by Pali's PR afterwards?
> 
> In the existing pci-bus.yaml is fine.

Hello Rob! I do not think that it is possible to add this property
correctly in to the existing pci-bus.yaml file. As this file is not
prepared for slot properties. And I guess that adding new property at
"random" place is against the idea of schema validation (that validation
procedure accepts only valid DTS files).

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Rob Herring]

On Wed, Jan 5, 2022 at 9:14 AM Pali Rohár <pali@kernel.org> wrote:
>
> On Wednesday 05 January 2022 08:27:21 Rob Herring wrote:
> > On Wed, Jan 5, 2022 at 8:14 AM Marek Behún <kabel@kernel.org> wrote:
> > >
> > > On Fri, 12 Nov 2021 09:25:20 -0600
> > > Rob Herring <robh@kernel.org> wrote:
> > >
> > > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > > > From: Pali Rohár <pali@kernel.org>
> > > > >
> > > > > This property specifies slot power limit in mW unit. It is a form-factor
> > > > > and board specific value and must be initialized by hardware.
> > > > >
> > > > > Some PCIe controllers delegate this work to software to allow hardware
> > > > > flexibility and therefore this property basically specifies what should
> > > > > host bridge program into PCIe Slot Capabilities registers.
> > > > >
> > > > > The property needs to be specified in mW unit instead of the special format
> > > > > defined by Slot Capabilities (which encodes scaling factor or different
> > > > > unit). Host drivers should convert the value from mW to needed format.
> > > > >
> > > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > > Signed-off-by: Marek Behún <kabel@kernel.org>
> > > > > ---
> > > > >  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
> > > > >  1 file changed, 6 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> > > > > index 6a8f2874a24d..7296d599c5ac 100644
> > > > > --- a/Documentation/devicetree/bindings/pci/pci.txt
> > > > > +++ b/Documentation/devicetree/bindings/pci/pci.txt
> > > > > @@ -32,6 +32,12 @@ driver implementation may support the following properties:
> > > > >     root port to downstream device and host bridge drivers can do programming
> > > > >     which depends on CLKREQ signal existence. For example, programming root port
> > > > >     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > > > > +- slot-power-limit-miliwatt:
> > > >
> > > > Typo.
> > > >
> > > > But we shouldn't be adding to pci.txt. This needs to go in the
> > > > schema[1]. Patch to devicetree-spec list or GH PR is fine.
> > >
> > > Hello Rob,
> > >
> > > Pali's PR draft https://github.com/devicetree-org/dt-schema/pull/64
> > > looks like it's going to take some time to work out.
> > >
> > > In the meantime, is it possible to somehow get the
> > > slot-power-limit-milliwatt property merged into pci.txt so that we can start
> > > putting it into existing device-trees?
> > >
> > > Or would it break dt_bindings_check if it isn't put into dt-schema's
> > > pci-bus.yaml?
> > >
> > > Or should we simply put it into current version of pci-bus.yaml and
> > > work out the split proposed by Pali's PR afterwards?
> >
> > In the existing pci-bus.yaml is fine.
>
> Hello Rob! I do not think that it is possible to add this property
> correctly in to the existing pci-bus.yaml file. As this file is not
> prepared for slot properties. And I guess that adding new property at
> "random" place is against the idea of schema validation (that validation
> procedure accepts only valid DTS files).

The only issue I see is the property would be allowed in host bridge
nodes rather than only root port or PCIe-PCIe bridge nodes because the
current file is a mixture of all of those. I think a note that the
property is not valid in host bridge nodes would be sufficient. It's
still better than documenting in pci.txt.

Rob

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Wednesday 05 January 2022 09:26:22 Rob Herring wrote:
> On Wed, Jan 5, 2022 at 9:14 AM Pali Rohár <pali@kernel.org> wrote:
> >
> > On Wednesday 05 January 2022 08:27:21 Rob Herring wrote:
> > > On Wed, Jan 5, 2022 at 8:14 AM Marek Behún <kabel@kernel.org> wrote:
> > > >
> > > > On Fri, 12 Nov 2021 09:25:20 -0600
> > > > Rob Herring <robh@kernel.org> wrote:
> > > >
> > > > > On Sun, Oct 31, 2021 at 04:07:05PM +0100, Marek Behún wrote:
> > > > > > From: Pali Rohár <pali@kernel.org>
> > > > > >
> > > > > > This property specifies slot power limit in mW unit. It is a form-factor
> > > > > > and board specific value and must be initialized by hardware.
> > > > > >
> > > > > > Some PCIe controllers delegate this work to software to allow hardware
> > > > > > flexibility and therefore this property basically specifies what should
> > > > > > host bridge program into PCIe Slot Capabilities registers.
> > > > > >
> > > > > > The property needs to be specified in mW unit instead of the special format
> > > > > > defined by Slot Capabilities (which encodes scaling factor or different
> > > > > > unit). Host drivers should convert the value from mW to needed format.
> > > > > >
> > > > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > > > Signed-off-by: Marek Behún <kabel@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
> > > > > >  1 file changed, 6 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> > > > > > index 6a8f2874a24d..7296d599c5ac 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/pci.txt
> > > > > > +++ b/Documentation/devicetree/bindings/pci/pci.txt
> > > > > > @@ -32,6 +32,12 @@ driver implementation may support the following properties:
> > > > > >     root port to downstream device and host bridge drivers can do programming
> > > > > >     which depends on CLKREQ signal existence. For example, programming root port
> > > > > >     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > > > > > +- slot-power-limit-miliwatt:
> > > > >
> > > > > Typo.
> > > > >
> > > > > But we shouldn't be adding to pci.txt. This needs to go in the
> > > > > schema[1]. Patch to devicetree-spec list or GH PR is fine.
> > > >
> > > > Hello Rob,
> > > >
> > > > Pali's PR draft https://github.com/devicetree-org/dt-schema/pull/64
> > > > looks like it's going to take some time to work out.
> > > >
> > > > In the meantime, is it possible to somehow get the
> > > > slot-power-limit-milliwatt property merged into pci.txt so that we can start
> > > > putting it into existing device-trees?
> > > >
> > > > Or would it break dt_bindings_check if it isn't put into dt-schema's
> > > > pci-bus.yaml?
> > > >
> > > > Or should we simply put it into current version of pci-bus.yaml and
> > > > work out the split proposed by Pali's PR afterwards?
> > >
> > > In the existing pci-bus.yaml is fine.
> >
> > Hello Rob! I do not think that it is possible to add this property
> > correctly in to the existing pci-bus.yaml file. As this file is not
> > prepared for slot properties. And I guess that adding new property at
> > "random" place is against the idea of schema validation (that validation
> > procedure accepts only valid DTS files).
> 
> The only issue I see is the property would be allowed in host bridge
> nodes rather than only root port or PCIe-PCIe bridge nodes because the
> current file is a mixture of all of those. I think a note that the
> property is not valid in host bridge nodes would be sufficient. It's
> still better than documenting in pci.txt.

Ok!

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Marek Behún]

On Wed, 5 Jan 2022 09:26:22 -0600
Rob Herring <robh@kernel.org> wrote:

> The only issue I see is the property would be allowed in host bridge
> nodes rather than only root port or PCIe-PCIe bridge nodes because the
> current file is a mixture of all of those. I think a note that the
> property is not valid in host bridge nodes would be sufficient. It's
> still better than documenting in pci.txt.
> 
> Rob

Created PR
  https://github.com/devicetree-org/dt-schema/pull/66

Marek

Re: [PATCH dt + pci 2/2] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property

[Marek Behún]

Hello Bjorn,

the property was merged into dt-schema, see
  https://github.com/devicetree-org/dt-schema/commit/7b2d7c521ba55903846cbba00518e1c4038699b4
so we don't need to add it to linux git anymore.

Since the property is documented id dt-schema, can we now merge this
patch, which adds the of_pci_get_slot_power_limit() function? Both
aardvark and mvebu driver will use this function.

Marek

On Sun, 31 Oct 2021 16:07:06 +0100
Marek Behún <kabel@kernel.org> wrote:

> From: Pali Rohár <pali@kernel.org>
> 
> Add function of_pci_get_slot_power_limit(), which parses the
> `slot-power-limit-milliwatt` DT property, returning the value in
> milliwatts and in format ready for the PCIe Slot Capabilities Register.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---
>  drivers/pci/of.c  | 64 +++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/pci/pci.h | 15 +++++++++++
>  2 files changed, 79 insertions(+)
> 
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index d84381ce82b5..9c1a38d5dd99 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -627,3 +627,67 @@ int of_pci_get_max_link_speed(struct device_node *node)
>  	return max_link_speed;
>  }
>  EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
> +
> +/**
> + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt"
> + *				 property.
> + *
> + * @node: device tree node with the slot power limit information
> + * @slot_power_limit_value: pointer where the value should be stored in PCIe
> + *			    Slot Capabilities Register format
> + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe
> + *			    Slot Capabilities Register format
> + *
> + * Returns the slot power limit in milliwatts and if @slot_power_limit_value
> + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and
> + * scale in format used by PCIe Slot Capabilities Register.
> + *
> + * If the property is not found or is invalid, returns 0.
> + */
> +u32 of_pci_get_slot_power_limit(struct device_node *node,
> +				u8 *slot_power_limit_value,
> +				u8 *slot_power_limit_scale)
> +{
> +	u32 slot_power_limit;
> +	u8 value, scale;
> +
> +	if (of_property_read_u32(node, "slot-power-limit-milliwatt",
> +				 &slot_power_limit))
> +		slot_power_limit = 0;
> +
> +	/* Calculate Slot Power Limit Value and Slot Power Limit Scale */
> +	if (slot_power_limit == 0) {
> +		value = 0x00;
> +		scale = 0;
> +	} else if (slot_power_limit <= 255) {
> +		value = slot_power_limit;
> +		scale = 3;
> +	} else if (slot_power_limit <= 255*10) {
> +		value = slot_power_limit / 10;
> +		scale = 2;
> +	} else if (slot_power_limit <= 255*100) {
> +		value = slot_power_limit / 100;
> +		scale = 1;
> +	} else if (slot_power_limit <= 239*1000) {
> +		value = slot_power_limit / 1000;
> +		scale = 0;
> +	} else if (slot_power_limit <= 250*1000) {
> +		value = 0xF0;
> +		scale = 0;
> +	} else if (slot_power_limit <= 275*1000) {
> +		value = 0xF1;
> +		scale = 0;
> +	} else {
> +		value = 0xF2;
> +		scale = 0;
> +	}
> +
> +	if (slot_power_limit_value)
> +		*slot_power_limit_value = value;
> +
> +	if (slot_power_limit_scale)
> +		*slot_power_limit_scale = scale;
> +
> +	return slot_power_limit;
> +}
> +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 1cce56c2aea0..9352278141be 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -665,6 +665,9 @@ struct device_node;
>  int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
>  int of_get_pci_domain_nr(struct device_node *node);
>  int of_pci_get_max_link_speed(struct device_node *node);
> +u32 of_pci_get_slot_power_limit(struct device_node *node,
> +				u8 *slot_power_limit_value,
> +				u8 *slot_power_limit_scale);
>  void pci_set_of_node(struct pci_dev *dev);
>  void pci_release_of_node(struct pci_dev *dev);
>  void pci_set_bus_of_node(struct pci_bus *bus);
> @@ -691,6 +694,18 @@ of_pci_get_max_link_speed(struct device_node *node)
>  	return -EINVAL;
>  }
>  
> +static inline u32
> +of_pci_get_slot_power_limit(struct device_node *node,
> +			    u8 *slot_power_limit_value,
> +			    u8 *slot_power_limit_scale)
> +{
> +	if (slot_power_limit_value)
> +		*slot_power_limit_value = 0;
> +	if (slot_power_limit_scale)
> +		*slot_power_limit_scale = 0;
> +	return 0;
> +}
> +
>  static inline void pci_set_of_node(struct pci_dev *dev) { }
>  static inline void pci_release_of_node(struct pci_dev *dev) { }
>  static inline void pci_set_bus_of_node(struct pci_bus *bus) { }

Re: [PATCH dt + pci 2/2] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property

[Rob Herring]

On Sun, Oct 31, 2021 at 10:07 AM Marek Behún <kabel@kernel.org> wrote:
>
> From: Pali Rohár <pali@kernel.org>
>
> Add function of_pci_get_slot_power_limit(), which parses the
> `slot-power-limit-milliwatt` DT property, returning the value in
> milliwatts and in format ready for the PCIe Slot Capabilities Register.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---
>  drivers/pci/of.c  | 64 +++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/pci/pci.h | 15 +++++++++++
>  2 files changed, 79 insertions(+)

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH dt + pci 2/2] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property

[Bjorn Helgaas]

On Sun, Oct 31, 2021 at 04:07:06PM +0100, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> Add function of_pci_get_slot_power_limit(), which parses the
> `slot-power-limit-milliwatt` DT property, returning the value in
> milliwatts and in format ready for the PCIe Slot Capabilities Register.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

Do we have a caller of of_pci_get_slot_power_limit() yet?  I didn't
see one from a quick look
(https://lore.kernel.org/linux-pci/?q=b%3Aof_pci_get_slot_power_limit).

Let's merge this when we have a user for it.

> ---
>  drivers/pci/of.c  | 64 +++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/pci/pci.h | 15 +++++++++++
>  2 files changed, 79 insertions(+)
> 
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index d84381ce82b5..9c1a38d5dd99 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -627,3 +627,67 @@ int of_pci_get_max_link_speed(struct device_node *node)
>  	return max_link_speed;
>  }
>  EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
> +
> +/**
> + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt"
> + *				 property.
> + *
> + * @node: device tree node with the slot power limit information
> + * @slot_power_limit_value: pointer where the value should be stored in PCIe
> + *			    Slot Capabilities Register format
> + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe
> + *			    Slot Capabilities Register format
> + *
> + * Returns the slot power limit in milliwatts and if @slot_power_limit_value
> + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and
> + * scale in format used by PCIe Slot Capabilities Register.
> + *
> + * If the property is not found or is invalid, returns 0.
> + */
> +u32 of_pci_get_slot_power_limit(struct device_node *node,
> +				u8 *slot_power_limit_value,
> +				u8 *slot_power_limit_scale)
> +{
> +	u32 slot_power_limit;
> +	u8 value, scale;
> +
> +	if (of_property_read_u32(node, "slot-power-limit-milliwatt",
> +				 &slot_power_limit))
> +		slot_power_limit = 0;
> +
> +	/* Calculate Slot Power Limit Value and Slot Power Limit Scale */
> +	if (slot_power_limit == 0) {
> +		value = 0x00;
> +		scale = 0;
> +	} else if (slot_power_limit <= 255) {
> +		value = slot_power_limit;
> +		scale = 3;
> +	} else if (slot_power_limit <= 255*10) {
> +		value = slot_power_limit / 10;
> +		scale = 2;
> +	} else if (slot_power_limit <= 255*100) {
> +		value = slot_power_limit / 100;
> +		scale = 1;
> +	} else if (slot_power_limit <= 239*1000) {
> +		value = slot_power_limit / 1000;
> +		scale = 0;
> +	} else if (slot_power_limit <= 250*1000) {
> +		value = 0xF0;
> +		scale = 0;
> +	} else if (slot_power_limit <= 275*1000) {
> +		value = 0xF1;
> +		scale = 0;
> +	} else {
> +		value = 0xF2;
> +		scale = 0;
> +	}
> +
> +	if (slot_power_limit_value)
> +		*slot_power_limit_value = value;
> +
> +	if (slot_power_limit_scale)
> +		*slot_power_limit_scale = scale;
> +
> +	return slot_power_limit;
> +}
> +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 1cce56c2aea0..9352278141be 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -665,6 +665,9 @@ struct device_node;
>  int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
>  int of_get_pci_domain_nr(struct device_node *node);
>  int of_pci_get_max_link_speed(struct device_node *node);
> +u32 of_pci_get_slot_power_limit(struct device_node *node,
> +				u8 *slot_power_limit_value,
> +				u8 *slot_power_limit_scale);
>  void pci_set_of_node(struct pci_dev *dev);
>  void pci_release_of_node(struct pci_dev *dev);
>  void pci_set_bus_of_node(struct pci_bus *bus);
> @@ -691,6 +694,18 @@ of_pci_get_max_link_speed(struct device_node *node)
>  	return -EINVAL;
>  }
>  
> +static inline u32
> +of_pci_get_slot_power_limit(struct device_node *node,
> +			    u8 *slot_power_limit_value,
> +			    u8 *slot_power_limit_scale)
> +{
> +	if (slot_power_limit_value)
> +		*slot_power_limit_value = 0;
> +	if (slot_power_limit_scale)
> +		*slot_power_limit_scale = 0;
> +	return 0;
> +}
> +
>  static inline void pci_set_of_node(struct pci_dev *dev) { }
>  static inline void pci_release_of_node(struct pci_dev *dev) { }
>  static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
> -- 
> 2.32.0
> 

Re: [PATCH dt + pci 2/2] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property

[Pali Rohár]

On Wednesday 12 January 2022 16:08:15 Bjorn Helgaas wrote:
> On Sun, Oct 31, 2021 at 04:07:06PM +0100, Marek Behún wrote:
> > From: Pali Rohár <pali@kernel.org>
> > 
> > Add function of_pci_get_slot_power_limit(), which parses the
> > `slot-power-limit-milliwatt` DT property, returning the value in
> > milliwatts and in format ready for the PCIe Slot Capabilities Register.
> > 
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > Signed-off-by: Marek Behún <kabel@kernel.org>
> 
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> 
> Do we have a caller of of_pci_get_slot_power_limit() yet?  I didn't
> see one from a quick look
> (https://lore.kernel.org/linux-pci/?q=b%3Aof_pci_get_slot_power_limit).
> 
> Let's merge this when we have a user for it.

I have a patch for both pci-mvebu.c and pci-aardvark.c drivers. But
there are lot of patches for these drivers waiting on mailing list for
review... Should I sent another patch for pci-mvebu.c which will use
this of_pci_get_slot_power_limit() function?

> > ---
> >  drivers/pci/of.c  | 64 +++++++++++++++++++++++++++++++++++++++++++++++
> >  drivers/pci/pci.h | 15 +++++++++++
> >  2 files changed, 79 insertions(+)
> > 
> > diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> > index d84381ce82b5..9c1a38d5dd99 100644
> > --- a/drivers/pci/of.c
> > +++ b/drivers/pci/of.c
> > @@ -627,3 +627,67 @@ int of_pci_get_max_link_speed(struct device_node *node)
> >  	return max_link_speed;
> >  }
> >  EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
> > +
> > +/**
> > + * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt"
> > + *				 property.
> > + *
> > + * @node: device tree node with the slot power limit information
> > + * @slot_power_limit_value: pointer where the value should be stored in PCIe
> > + *			    Slot Capabilities Register format
> > + * @slot_power_limit_scale: pointer where the scale should be stored in PCIe
> > + *			    Slot Capabilities Register format
> > + *
> > + * Returns the slot power limit in milliwatts and if @slot_power_limit_value
> > + * and @slot_power_limit_scale pointers are non-NULL, fills in the value and
> > + * scale in format used by PCIe Slot Capabilities Register.
> > + *
> > + * If the property is not found or is invalid, returns 0.
> > + */
> > +u32 of_pci_get_slot_power_limit(struct device_node *node,
> > +				u8 *slot_power_limit_value,
> > +				u8 *slot_power_limit_scale)
> > +{
> > +	u32 slot_power_limit;
> > +	u8 value, scale;
> > +
> > +	if (of_property_read_u32(node, "slot-power-limit-milliwatt",
> > +				 &slot_power_limit))
> > +		slot_power_limit = 0;
> > +
> > +	/* Calculate Slot Power Limit Value and Slot Power Limit Scale */
> > +	if (slot_power_limit == 0) {
> > +		value = 0x00;
> > +		scale = 0;
> > +	} else if (slot_power_limit <= 255) {
> > +		value = slot_power_limit;
> > +		scale = 3;
> > +	} else if (slot_power_limit <= 255*10) {
> > +		value = slot_power_limit / 10;
> > +		scale = 2;
> > +	} else if (slot_power_limit <= 255*100) {
> > +		value = slot_power_limit / 100;
> > +		scale = 1;
> > +	} else if (slot_power_limit <= 239*1000) {
> > +		value = slot_power_limit / 1000;
> > +		scale = 0;
> > +	} else if (slot_power_limit <= 250*1000) {
> > +		value = 0xF0;
> > +		scale = 0;
> > +	} else if (slot_power_limit <= 275*1000) {
> > +		value = 0xF1;
> > +		scale = 0;
> > +	} else {
> > +		value = 0xF2;
> > +		scale = 0;
> > +	}
> > +
> > +	if (slot_power_limit_value)
> > +		*slot_power_limit_value = value;
> > +
> > +	if (slot_power_limit_scale)
> > +		*slot_power_limit_scale = scale;
> > +
> > +	return slot_power_limit;
> > +}
> > +EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index 1cce56c2aea0..9352278141be 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -665,6 +665,9 @@ struct device_node;
> >  int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
> >  int of_get_pci_domain_nr(struct device_node *node);
> >  int of_pci_get_max_link_speed(struct device_node *node);
> > +u32 of_pci_get_slot_power_limit(struct device_node *node,
> > +				u8 *slot_power_limit_value,
> > +				u8 *slot_power_limit_scale);
> >  void pci_set_of_node(struct pci_dev *dev);
> >  void pci_release_of_node(struct pci_dev *dev);
> >  void pci_set_bus_of_node(struct pci_bus *bus);
> > @@ -691,6 +694,18 @@ of_pci_get_max_link_speed(struct device_node *node)
> >  	return -EINVAL;
> >  }
> >  
> > +static inline u32
> > +of_pci_get_slot_power_limit(struct device_node *node,
> > +			    u8 *slot_power_limit_value,
> > +			    u8 *slot_power_limit_scale)
> > +{
> > +	if (slot_power_limit_value)
> > +		*slot_power_limit_value = 0;
> > +	if (slot_power_limit_scale)
> > +		*slot_power_limit_scale = 0;
> > +	return 0;
> > +}
> > +
> >  static inline void pci_set_of_node(struct pci_dev *dev) { }
> >  static inline void pci_release_of_node(struct pci_dev *dev) { }
> >  static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
> > -- 
> > 2.32.0
> > 

Re: [PATCH dt + pci 2/2] PCI: Add function for parsing `slot-power-limit-milliwatt` DT property

[Bjorn Helgaas]

On Wed, Jan 12, 2022 at 11:28:22PM +0100, Pali Rohár wrote:
> On Wednesday 12 January 2022 16:08:15 Bjorn Helgaas wrote:
> > On Sun, Oct 31, 2021 at 04:07:06PM +0100, Marek Behún wrote:
> > > From: Pali Rohár <pali@kernel.org>
> > > 
> > > Add function of_pci_get_slot_power_limit(), which parses the
> > > `slot-power-limit-milliwatt` DT property, returning the value in
> > > milliwatts and in format ready for the PCIe Slot Capabilities Register.
> > > 
> > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > Signed-off-by: Marek Behún <kabel@kernel.org>
> > 
> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > 
> > Do we have a caller of of_pci_get_slot_power_limit() yet?  I didn't
> > see one from a quick look
> > (https://lore.kernel.org/linux-pci/?q=b%3Aof_pci_get_slot_power_limit).
> > 
> > Let's merge this when we have a user for it.
> 
> I have a patch for both pci-mvebu.c and pci-aardvark.c drivers. But
> there are lot of patches for these drivers waiting on mailing list for
> review... Should I sent another patch for pci-mvebu.c which will use
> this of_pci_get_slot_power_limit() function?

If the of_pci_get_slot_power_limit() patches are independent of the
ones waiting for review, they could be added to *this* series.

Bjorn

Re: [PATCH dt + pci 1/2] dt-bindings: Add 'slot-power-limit-milliwatt' PCIe port property

[Pali Rohár]

On Sunday 31 October 2021 16:07:05 Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> This property specifies slot power limit in mW unit. It is a form-factor
> and board specific value and must be initialized by hardware.
> 
> Some PCIe controllers delegate this work to software to allow hardware
> flexibility and therefore this property basically specifies what should
> host bridge program into PCIe Slot Capabilities registers.
> 
> The property needs to be specified in mW unit instead of the special format
> defined by Slot Capabilities (which encodes scaling factor or different
> unit). Host drivers should convert the value from mW to needed format.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> index 6a8f2874a24d..7296d599c5ac 100644
> --- a/Documentation/devicetree/bindings/pci/pci.txt
> +++ b/Documentation/devicetree/bindings/pci/pci.txt
> @@ -32,6 +32,12 @@ driver implementation may support the following properties:
>     root port to downstream device and host bridge drivers can do programming
>     which depends on CLKREQ signal existence. For example, programming root port
>     not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> +- slot-power-limit-miliwatt:

                      ^^^^^^^^
                typo: milliwatt

> +   If present, this property specifies slot power limit in milliwatts. Host
> +   drivers can parse this property and use it for programming Root Port or host
> +   bridge, or for composing and sending PCIe Set_Slot_Power_Limit messages
> +   through the Root Port or host bridge when transitioning PCIe link from a
> +   non-DL_Up Status to a DL_Up Status.
>  
>  PCI-PCI Bridge properties
>  -------------------------
> -- 
> 2.32.0
>