From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 09/17 v1] irqchip: ixp4xx: Add DT bindings Date: Mon, 18 Feb 2019 15:25:15 -0600 Message-ID: References: <20190203214205.13594-1-linus.walleij@linaro.org> <20190203214205.13594-10-linus.walleij@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190203214205.13594-10-linus.walleij@linaro.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Linus Walleij Cc: devicetree@vger.kernel.org, Jason Cooper , Arnd Bergmann , Marc Zyngier , Tim Harvey , Krzysztof Halasa , Olof Johansson , Thomas Gleixner , Imre Kaloz , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" List-Id: devicetree@vger.kernel.org On Sun, Feb 3, 2019 at 3:42 PM Linus Walleij wrote: > > This adds device tree bindings for the IXP4xx interrupt > controller. It's a standard 2-cell controller. Not required, but writing as a schema would be great. Looks like it would be straight forward. > Cc: Marc Zyngier > Cc: Jason Cooper > Cc: Thomas Gleixner > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij > --- > irqchip maintainers: I am requesting an ACK for this once > you're happy with the bindings, as I intend to merge all of > this IXP4xx rework through ARM SoC. > --- > .../intel,ixp4xx-interrupt.txt | 33 +++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 34 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt > new file mode 100644 > index 000000000000..70ee93b9a6c0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt > @@ -0,0 +1,33 @@ > +* Intel IXP4xx XScale Networking Processors Interrupt Controller > + > +This interrupt controller is found in the Intel IXP4xx processors. > +Some processors have 32 interrupts, some have up to 64 interrupts. > +The exact number of interrupts is determined from the compatible > +string. > + > +The distinct IXP4xx families with different interrupt controller > +variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four > +families were the only ones to reach the developer and consumer > +market. > + > +Required properties: > +- compatible: must be one of > + "intel,ixp42x-interrupt" > + "intel,ixp43x-interrupt" > + "intel,ixp45x-interrupt" > + "intel,ixp46x-interrupt" While we normally don't allow wildcards, I'm guessing this is all so old^W mature that it will be fine. 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Mon, 18 Feb 2019 13:25:27 -0800 (PST) X-Gm-Message-State: AHQUAubiuhbXdRMkeB+AO5ns3xj2Sx44p8aAqCCZaDRlIxuYgMYOlPUT iyg2sd5++GvcDSbdcTXKUVRVhCS5dBhJl9jMsw== X-Google-Smtp-Source: AHgI3IZmWapeMkZ+fFOJfal+zulpN7Rv87ViIYw3zgDoLkCr02ZZNqHvqG1jgnTx1HOMT1jMm4Fe0O0jzgBYNUTF6ok= X-Received: by 2002:aed:2a2f:: with SMTP id c44mr20162844qtd.144.1550525126979; Mon, 18 Feb 2019 13:25:26 -0800 (PST) MIME-Version: 1.0 References: <20190203214205.13594-1-linus.walleij@linaro.org> <20190203214205.13594-10-linus.walleij@linaro.org> In-Reply-To: <20190203214205.13594-10-linus.walleij@linaro.org> From: Rob Herring Date: Mon, 18 Feb 2019 15:25:15 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 09/17 v1] irqchip: ixp4xx: Add DT bindings To: Linus Walleij X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190218_132529_409183_B6FECE55 X-CRM114-Status: GOOD ( 20.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jason Cooper , Arnd Bergmann , Marc Zyngier , Tim Harvey , Krzysztof Halasa , Olof Johansson , Thomas Gleixner , Imre Kaloz , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Feb 3, 2019 at 3:42 PM Linus Walleij wrote: > > This adds device tree bindings for the IXP4xx interrupt > controller. It's a standard 2-cell controller. Not required, but writing as a schema would be great. Looks like it would be straight forward. > Cc: Marc Zyngier > Cc: Jason Cooper > Cc: Thomas Gleixner > Cc: devicetree@vger.kernel.org > Signed-off-by: Linus Walleij > --- > irqchip maintainers: I am requesting an ACK for this once > you're happy with the bindings, as I intend to merge all of > this IXP4xx rework through ARM SoC. > --- > .../intel,ixp4xx-interrupt.txt | 33 +++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 34 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt > new file mode 100644 > index 000000000000..70ee93b9a6c0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt > @@ -0,0 +1,33 @@ > +* Intel IXP4xx XScale Networking Processors Interrupt Controller > + > +This interrupt controller is found in the Intel IXP4xx processors. > +Some processors have 32 interrupts, some have up to 64 interrupts. > +The exact number of interrupts is determined from the compatible > +string. > + > +The distinct IXP4xx families with different interrupt controller > +variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four > +families were the only ones to reach the developer and consumer > +market. > + > +Required properties: > +- compatible: must be one of > + "intel,ixp42x-interrupt" > + "intel,ixp43x-interrupt" > + "intel,ixp45x-interrupt" > + "intel,ixp46x-interrupt" While we normally don't allow wildcards, I'm guessing this is all so old^W mature that it will be fine. Reviewed-by: Rob Herring _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel