From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 617D9C3F68F for ; Thu, 16 Jan 2020 14:33:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 387F02051A for ; Thu, 16 Jan 2020 14:33:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579185225; bh=zCTzRzpxW45hf9zhu97cl/HH/TkaKoXKxG33ubUlcis=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=rnTVwwHXZLkzj293MRBQxPhVozu19eAuhbO6o//VZZuzcbNL1hMTyqezFthRaguaj +8gQLtYfTy2eSzsMFJVVCrUacgbYCcRgBEVl7tAolNGa64y9wE9+sDH+MG6dolEiGD Aw/84W0tYS7i0syQBAhtKdTVoWPO3FMDt2rQ9OD4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726867AbgAPOdo (ORCPT ); Thu, 16 Jan 2020 09:33:44 -0500 Received: from mail.kernel.org ([198.145.29.99]:56588 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726084AbgAPOdo (ORCPT ); Thu, 16 Jan 2020 09:33:44 -0500 Received: from mail-qv1-f46.google.com (mail-qv1-f46.google.com [209.85.219.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 197A62051A; Thu, 16 Jan 2020 14:33:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579185223; bh=zCTzRzpxW45hf9zhu97cl/HH/TkaKoXKxG33ubUlcis=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=lzvmVPxC0YoX1GCXF9xUvPrjSs4rABccejlMEYJBJejJBHBYBFbLHbl9I1uSYPV0s 3EY+xd0XAuDU9RZq3eOwaUXPY3w86rI2ei6fInbAhyjKcskoR3Ss6JG1AD0V/OTu72 nbcIyHgK5xQvFUJjrWjxwTqxbhEM7tjwPVQtLOqo= Received: by mail-qv1-f46.google.com with SMTP id z3so9148661qvn.0; Thu, 16 Jan 2020 06:33:43 -0800 (PST) X-Gm-Message-State: APjAAAUZf5JvTMUXWA4g4UdcXB4lVoK+7DPigTkv2Py4mEspQFKkbJ/2 P/VVfo4mqlhpeHtKffVLuqg6aioAepSjzS66vQ== X-Google-Smtp-Source: APXvYqxpzOz30rqleYyMHf6/FcDEmshzxEl/xINJJW+FtV85eSNgGaPEZdKTK/HozyW+hT6davB/mrOR0U63bbSIPFg= X-Received: by 2002:ad4:450a:: with SMTP id k10mr2710244qvu.136.1579185222222; Thu, 16 Jan 2020 06:33:42 -0800 (PST) MIME-Version: 1.0 References: <20200110134823.14882-1-ludovic.barre@st.com> <20200110134823.14882-6-ludovic.barre@st.com> <20200115145645.GA599@bogus> <2ce63f11-8b0c-8261-63fa-cd19e874c537@st.com> In-Reply-To: <2ce63f11-8b0c-8261-63fa-cd19e874c537@st.com> From: Rob Herring Date: Thu, 16 Jan 2020 08:33:30 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc To: Ludovic BARRE Cc: Ulf Hansson , Srinivas Kandagatla , Maxime Coquelin , Alexandre Torgue , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org, linux-mmc , linux-stm32@st-md-mailman.stormreply.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 16, 2020 at 3:21 AM Ludovic BARRE wrote: > > Hi Rob > > Le 1/15/20 =C3=A0 3:56 PM, Rob Herring a =C3=A9crit : > > On Fri, Jan 10, 2020 at 02:48:19PM +0100, Ludovic Barre wrote: > >> To support the sdr104 mode, the sdmmc variant has a > >> hardware delay block to manage the clock phase when sampling > >> data received by the card. > >> > >> This patch adds a second base register (optional) for > >> sdmmc delay block. > >> > >> Signed-off-by: Ludovic Barre > >> --- > >> Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++ > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Document= ation/devicetree/bindings/mmc/mmci.txt > >> index 6d3c626e017d..4ec921e4bf34 100644 > >> --- a/Documentation/devicetree/bindings/mmc/mmci.txt > >> +++ b/Documentation/devicetree/bindings/mmc/mmci.txt > >> @@ -28,6 +28,8 @@ specific for ux500 variant: > >> - st,sig-pin-fbclk : feedback clock signal pin used. > >> > >> specific for sdmmc variant: > >> +- reg : a second base register may be defined = if a delay > >> + block is present and used for tuning. > > > > Which compatibles have a 2nd reg entry? > > In fact, mmci driver is ARM Amba driver (arm,primecell) and has only one > compatible "arm,pl18x". > The variants are identified by primecell-periphid property > (discovered at runtime with HW block register or defined by > device tree property "arm,primecell-periphid"). > > The defaults "arm,pl18x" variants have only one base register, > but the SDMMC need a second base register for these > delay block registers. > > example of sdmmc node: > sdmmc1: sdmmc@58005000 { > compatible =3D "arm,pl18x", "arm,primecell"; > arm,primecell-periphid =3D <0x00253180>; > reg =3D <0x58005000 0x1000>, <0x58006000 0x1000>; > }; > > what do you advise? I missed that this is a primecell block. Just give some indication which variants have this 2nd range. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B901C33CB1 for ; Thu, 16 Jan 2020 14:33:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D4AA207E0 for ; Thu, 16 Jan 2020 14:33:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uOVjaVsQ"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="lzvmVPxC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D4AA207E0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hGA/bg7CEnGvXJS1yxO2S5mUt/94Sv5r8ICa1OWdAY0=; b=uOVjaVsQ1ty5an Urld3daNMFw+cEKUevmjvr2COe11cdAldsuBwVQPXmJwTAhLQcaRU0yFbVTMEGQ2L7Y8IvJxZUZeO aefHHfGBBEK2k6rUjP/vRfKTqz6tZHW9v3X02ZXy/MqtPkufUn5K9r8zKAPNjX8DWrWWklvfU8+c2 3jfEZ9G4PzY6fpjIOsYmkj7cF7pBQPrxzSm4mSuklSx+Q77E9x/7UqV0VbI+SpzTOmx1L/j82NfP+ zO/v8LFTWNhK2l4tL/mP5nDfXg5kUAgfZfXrvblW1gBIlg/E6ruoP6ylVlzdgXQSae43/BfJq/dYY 5aMBc5HZ0RIEiM3exN6w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1is6DW-0004TC-91; Thu, 16 Jan 2020 14:33:50 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1is6DP-0004SJ-VU for linux-arm-kernel@lists.infradead.org; Thu, 16 Jan 2020 14:33:48 +0000 Received: from mail-qv1-f52.google.com (mail-qv1-f52.google.com [209.85.219.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 200BC2087E for ; Thu, 16 Jan 2020 14:33:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579185223; bh=zCTzRzpxW45hf9zhu97cl/HH/TkaKoXKxG33ubUlcis=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=lzvmVPxC0YoX1GCXF9xUvPrjSs4rABccejlMEYJBJejJBHBYBFbLHbl9I1uSYPV0s 3EY+xd0XAuDU9RZq3eOwaUXPY3w86rI2ei6fInbAhyjKcskoR3Ss6JG1AD0V/OTu72 nbcIyHgK5xQvFUJjrWjxwTqxbhEM7tjwPVQtLOqo= Received: by mail-qv1-f52.google.com with SMTP id f16so9135469qvi.4 for ; Thu, 16 Jan 2020 06:33:43 -0800 (PST) X-Gm-Message-State: APjAAAWJ6IcleZYXF44XcabZ70mgqDy6W1HdoQh1fod28bJs/jpzTP7N TulJUitfXu8ud2JQyfs3vq409AYLBAfdOUbnSw== X-Google-Smtp-Source: APXvYqxpzOz30rqleYyMHf6/FcDEmshzxEl/xINJJW+FtV85eSNgGaPEZdKTK/HozyW+hT6davB/mrOR0U63bbSIPFg= X-Received: by 2002:ad4:450a:: with SMTP id k10mr2710244qvu.136.1579185222222; Thu, 16 Jan 2020 06:33:42 -0800 (PST) MIME-Version: 1.0 References: <20200110134823.14882-1-ludovic.barre@st.com> <20200110134823.14882-6-ludovic.barre@st.com> <20200115145645.GA599@bogus> <2ce63f11-8b0c-8261-63fa-cd19e874c537@st.com> In-Reply-To: <2ce63f11-8b0c-8261-63fa-cd19e874c537@st.com> From: Rob Herring Date: Thu, 16 Jan 2020 08:33:30 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc To: Ludovic BARRE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200116_063344_057753_7F5DF517 X-CRM114-Status: GOOD ( 21.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , Alexandre Torgue , linux-mmc , "linux-kernel@vger.kernel.org" , Srinivas Kandagatla , Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com, "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBKYW4gMTYsIDIwMjAgYXQgMzoyMSBBTSBMdWRvdmljIEJBUlJFIDxsdWRvdmljLmJh cnJlQHN0LmNvbT4gd3JvdGU6Cj4KPiBIaSBSb2IKPgo+IExlIDEvMTUvMjAgw6AgMzo1NiBQTSwg Um9iIEhlcnJpbmcgYSDDqWNyaXQgOgo+ID4gT24gRnJpLCBKYW4gMTAsIDIwMjAgYXQgMDI6NDg6 MTlQTSArMDEwMCwgTHVkb3ZpYyBCYXJyZSB3cm90ZToKPiA+PiBUbyBzdXBwb3J0IHRoZSBzZHIx MDQgbW9kZSwgdGhlIHNkbW1jIHZhcmlhbnQgaGFzIGEKPiA+PiBoYXJkd2FyZSBkZWxheSBibG9j ayB0byBtYW5hZ2UgdGhlIGNsb2NrIHBoYXNlIHdoZW4gc2FtcGxpbmcKPiA+PiBkYXRhIHJlY2Vp dmVkIGJ5IHRoZSBjYXJkLgo+ID4+Cj4gPj4gVGhpcyBwYXRjaCBhZGRzIGEgc2Vjb25kIGJhc2Ug cmVnaXN0ZXIgKG9wdGlvbmFsKSBmb3IKPiA+PiBzZG1tYyBkZWxheSBibG9jay4KPiA+Pgo+ID4+ IFNpZ25lZC1vZmYtYnk6IEx1ZG92aWMgQmFycmUgPGx1ZG92aWMuYmFycmVAc3QuY29tPgo+ID4+ IC0tLQo+ID4+ICAgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21tYy9tbWNpLnR4 dCB8IDIgKysKPiA+PiAgIDEgZmlsZSBjaGFuZ2VkLCAyIGluc2VydGlvbnMoKykKPiA+Pgo+ID4+ IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbW1jL21tY2ku dHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL21tYy9tbWNpLnR4dAo+ID4+ IGluZGV4IDZkM2M2MjZlMDE3ZC4uNGVjOTIxZTRiZjM0IDEwMDY0NAo+ID4+IC0tLSBhL0RvY3Vt ZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9tbWMvbW1jaS50eHQKPiA+PiArKysgYi9Eb2N1 bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbW1jL21tY2kudHh0Cj4gPj4gQEAgLTI4LDYg KzI4LDggQEAgc3BlY2lmaWMgZm9yIHV4NTAwIHZhcmlhbnQ6Cj4gPj4gICAtIHN0LHNpZy1waW4t ZmJjbGsgICAgICAgOiBmZWVkYmFjayBjbG9jayBzaWduYWwgcGluIHVzZWQuCj4gPj4KPiA+PiAg IHNwZWNpZmljIGZvciBzZG1tYyB2YXJpYW50Ogo+ID4+ICstIHJlZyAgICAgICAgICAgICAgICAg ICAgICAgIDogYSBzZWNvbmQgYmFzZSByZWdpc3RlciBtYXkgYmUgZGVmaW5lZCBpZiBhIGRlbGF5 Cj4gPj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgIGJsb2NrIGlzIHByZXNlbnQgYW5kIHVz ZWQgZm9yIHR1bmluZy4KPiA+Cj4gPiBXaGljaCBjb21wYXRpYmxlcyBoYXZlIGEgMm5kIHJlZyBl bnRyeT8KPgo+IEluIGZhY3QsIG1tY2kgZHJpdmVyIGlzIEFSTSBBbWJhIGRyaXZlciAoYXJtLHBy aW1lY2VsbCkgYW5kIGhhcyBvbmx5IG9uZQo+IGNvbXBhdGlibGUgImFybSxwbDE4eCIuCj4gVGhl IHZhcmlhbnRzIGFyZSBpZGVudGlmaWVkIGJ5IHByaW1lY2VsbC1wZXJpcGhpZCBwcm9wZXJ0eQo+ IChkaXNjb3ZlcmVkIGF0IHJ1bnRpbWUgd2l0aCBIVyBibG9jayByZWdpc3RlciBvciBkZWZpbmVk IGJ5Cj4gZGV2aWNlIHRyZWUgcHJvcGVydHkgImFybSxwcmltZWNlbGwtcGVyaXBoaWQiKS4KPgo+ IFRoZSBkZWZhdWx0cyAiYXJtLHBsMTh4IiB2YXJpYW50cyBoYXZlIG9ubHkgb25lIGJhc2UgcmVn aXN0ZXIsCj4gYnV0IHRoZSBTRE1NQyBuZWVkIGEgc2Vjb25kIGJhc2UgcmVnaXN0ZXIgZm9yIHRo ZXNlCj4gZGVsYXkgYmxvY2sgcmVnaXN0ZXJzLgo+Cj4gZXhhbXBsZSBvZiBzZG1tYyBub2RlOgo+ ICAgICAgICAgc2RtbWMxOiBzZG1tY0A1ODAwNTAwMCB7Cj4gICAgICAgICAgICAgICAgIGNvbXBh dGlibGUgPSAiYXJtLHBsMTh4IiwgImFybSxwcmltZWNlbGwiOwo+ICAgICAgICAgICAgICAgICBh cm0scHJpbWVjZWxsLXBlcmlwaGlkID0gPDB4MDAyNTMxODA+Owo+ICAgICAgICAgICAgICAgICBy ZWcgPSA8MHg1ODAwNTAwMCAweDEwMDA+LCA8MHg1ODAwNjAwMCAweDEwMDA+Owo+ICAgICAgICAg fTsKPgo+IHdoYXQgZG8geW91IGFkdmlzZT8KCkkgbWlzc2VkIHRoYXQgdGhpcyBpcyBhIHByaW1l Y2VsbCBibG9jay4gSnVzdCBnaXZlIHNvbWUgaW5kaWNhdGlvbgp3aGljaCB2YXJpYW50cyBoYXZl IHRoaXMgMm5kIHJhbmdlLgoKUm9iCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2Vy bmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1h bi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==